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* Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2011-02-09-0/+3
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| * ppc4xx: Add DLVision-10G board supportDirk Eibach2011-02-07-0/+3
| | | | | | | | | | | | | | | | | | | | Board support for the Guntermann & Drunck DLVision-10G. Adds support for multiple FPGAs per board for gdsys 405ep architecture. Adds support for dual link osd hardware for gdsys 405ep. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2011-02-06-8/+26
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| * | mpc83xx: Use correct register to calculate clocks.Joakim Tjernlund2011-02-05-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use SPMR instead of HRCWL when calculating clocks as HCRWL may be changed and the CPU will not pick up all changes until there is a POR. u-boot will think SPMF has changed and get the clocks wrong. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | mpc83xx: fix pcie configuration space read/writeLeo Liu2011-02-05-1/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fix a problem for the pcie enumeration when the mpc83xx pcie controller is connected with switch or we use both of the two pcie controller. Signed-off-by: Leo Liu <liucai.lfn@gmail.com> fix codingstyle and compiler warning: 'pcie_priv' defined but not used Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2011-02-06-6/+129
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| * | powerpc/8xxx: Fix possible compile issue related to P1013Kumar Gala2011-02-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The P1013 is a single core version of P1022 and thus should use the p1022_serdes.c code. It was acciently pointing to p1013_serdes.c which doesn't exist. Reported-by: Renaud Barbier <renaud.barbier@ge.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/mpc85xx: implement workaround for errata DDR111 and DDR134York Sun2011-02-03-1/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Workaround for the following errata: DDR111 - MCKE signal may not function correctly at assertion of HRESET DDR134 - The automatic CAS-to-Preamble feature of the DDR controller can calibrate to incorrect values These two workarounds must be implemented together because they touch common registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Rename MPC8572 DDR erratum to DDR115York Sun2011-02-03-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | Use unique erratum number instead of platform number. Enable command that reports errata on MPC8572DS. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Remove unnecessary polling loop from DDR initYork Sun2011-02-03-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | This polling loop is not required normally, unless specifically stated in workaround. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | fsl_esdhc: Add the workaround for erratum ESDHC-A001 (enable on P2020)Kumar Gala2011-02-03-0/+5
| | | | | | | | | | | | | | | | | | | | | Data timeout counter (SYSCTL[DTOCV]) is not reliable for values of 4, 8, and 12. Program one more than the desired value: 4 -> 5, 8 -> 9, 12 -> 13. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Enable ESDHC111 Erratum on P2010/P2020 SoCsKumar Gala2011-02-03-0/+2
| |/ | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-shWolfgang Denk2011-02-04-0/+226
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| * sh: add support for sh7757lcr boardYoshihiro Shimoda2011-02-02-0/+220
| | | | | | | | | | | | | | | | | | | | | | | | | | The R0P7757LC0030RL board has SH7757, 256MB DDR3-SDRAM, SPI ROM, Ethernet, and more. This patch supports the following functions: - 256MB DDR3-SDRAM - SPI ROM - Ethernet Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: add support the CONFIG_SYS_LDSCRIPTYoshihiro Shimoda2011-02-02-0/+6
| | | | | | | | | | Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | Minor Coding Style Cleanup.Wolfgang Denk2011-02-02-3/+3
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | armv7: add support for S5PC210 SoCMinkyu Kang2011-02-02-0/+1056
| | | | | | | | | | | | | | S5PC210 is a 32-bit RISC and Cortex-A9 Dual Core based micro-processor. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
* | S5P: serial: Use the inline function instead of static valueMinkyu Kang2011-02-02-1/+4
| | | | | | | | Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | arm926ejs: timer: Replace bss variable by gdrHeiko Schocher2011-02-02-16/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reuse the gd->tbl value for timestamp and add gd->lastinc for lastinc bss values in the arm926ejs timers implementation. The usage of bss values in drivers before initialisation of bss is forbidden. In that special case some data in .rel.dyn gets corrupted. This patch is similiar to the patch Dirk Behme posted for the armv7/omap-common/timer.c and added suggestions from Reinhard Meyer. Tested on the arm926ejs mx27 based magnesium board Tested on the arm926ejs kirkwood based suen3 board Signed-off-by: Heiko Schocher <hs@denx.de> cc: Albert ARIBAUD <albert.aribaud@free.fr> cc: Prafulla Wadaskar <prafulla@marvell.com> cc: Stefano Babic <sbabic@denx.de> cc: Reinhard Meyer <u-boot@emk-elektronik.de>
* | remove (double) LED initialization in arm920t start.sJens Scharsig2011-02-02-3/+0
| | | | | | | | | | | | * remove LED initialization in front of relocation and bss init Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
* | arm1136: timer: Replace bss variable by gdHeiko Schocher2011-02-02-20/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reuse the gd->tbl value for timestamp and add gd->lastinc for lastinc bss values in the arm1136 timer driver for mx31 and omap24xx The usage of bss values in drivers before initialisation of bss is forbidden. In that special case some data in .rel.dyn gets corrupted. This patch is similiar to the patch Dirk Behme posted for the armv7/omap-common/timer.c Tested on the mx31 based qong board Signed-off-by: Heiko Schocher <hs@denx.de> cc: Albert ARIBAUD <albert.aribaud@free.fr> Acked-by: Albert ARIBAUD <albert.aribaud@free.fr>
* | ARM: */start.S: code cleanupLiu Hui-R643432011-02-02-28/+0
| | | | | | | | | | | | | | Remove the useless code from start.S Signed-off-by: Jason Liu <r64343@freescale.com> Tested-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | ARM: Avoid compiler optimization for readb, writeb and friends.Alexander Holler2011-02-02-12/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc 4.5.1 seems to ignore (at least some) volatile definitions, avoid that as done in the kernel. Reading C99 6.7.3 8 and the comment 114) there, I think it is a bug of that gcc version to ignore the volatile type qualifier used e.g. in __arch_getl(). Anyway, using a definition as in the kernel headers avoids such optimizations when gcc 4.5.1 is used. Maybe the headers as used in the current linux-kernel should be used, but to avoid large changes, I've just added a small change to the current headers. Signed-off-by: Alexander Holler <holler@ahsoftware.de> Signed-off-by: Dirk Behme <dirk.behme@googlemail.com> Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Alessandro Rubini <rubini-list@gnudd.com> Tested-by: Thomas Weber <weber@corscience.de> Acked-by: Alexander Holler <holler@ahsoftware.de> Tested-by: Alexander Holler <holler@ahsoftware.de>
* | armv7: s5pc1xx: don't use function pointer for clock functionsMinkyu Kang2011-02-02-23/+27
| | | | | | | | | | | | | | | | Because of the bss area is cleared after relocation, we've lost pointers. This patch fixed it. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
* | DaVinci: Remove incorrect CONFIG optionSandeep Paulraj2011-02-02-6/+0
| | | | | | | | | | | | | | | | | | The option CONFIG_SOC_DM6447 seems to have ended up in the code by mistake. It is not used anywhere and there is no chip called DM6447. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | DaVinci DM6467: Fix Build ErrorSandeep Paulraj2011-02-02-0/+16
| | | | | | | | | | | | | | This commit fixes build errors on the DM6467 port. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | DaVinci DM6467: Enhance board SupportSandeep Paulraj2011-02-02-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Support for DM6467 was incomplete and the build failed as well. Patches were sent to the list but have not been added. This enhances the DM6467 support. Some more patches will need to be sent to bring it in line with what is available in internal TI trees Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | ARM: Update mach typesSandeep Paulraj2011-02-02-15/+2290
| | | | | | | | | | | | | | This commit updates the mach-types for ARM Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | DaVinci DM6467: Added ET1011C (LSI) PHY supportSandeep Paulraj2011-02-02-1/+59
| | | | | | | | | | | | | | | | | | | | Added arch/arm/cpu/arm926ejs/davinci/et1011c.c for handling ET1011C gigabit phy. which overrides get_link_speed function from default implementation. This enables output of 125 MHz reference clock on SYS_CLK pin. Signed-off-by: Prakash PM <prakash.pm@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | Davinci MMCSD SupportSandeep Paulraj2011-02-02-0/+175
| | | | | | | | | | | | | | | | | | | | Added support for MMC/SD cards for Davinci. This feature is enabled by CONFIG_DAVINCI_MMC and is dependant on CONFIG_MMC and CONFIG_GENERIC_MMC options. This is tested on DM355 and DM365 EVMs with both the available mmc controllers. Signed-off-by: Alagu Sankar <alagusankar@embwise.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | ARM: fix broken build of ARMStefano Babic2011-02-02-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 8aba9dceebb14144e07d19593111ee3a999c37fc breaks ARM boards because for ARM the -pie option is used for partial linking together with -r option. The patch adds the -pie option to link u-boot.bin only. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Jason Liu <liu.h.jason@gmail.com> CC: lool@dooz.org CC: Wolfgang Denk <wd@denx.de> CC: Albert Aribaud <albert.aribaud@free.fr> Tested-by: Alexander Holler <holler@ahsoftware.de>
* | MX5: Reuse the gd->tbl value for timestamp and add gd->lastinc for lastinc bssStefano Babic2011-02-02-2/+4
| | | | | | | | | | | | | | | | | | | | The usage of bss values in drivers before initialisation of bss is forbidden. In that special case some data in .rel.dyn gets corrupted. This patch is the same as recently applied for arm926js architecture. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Heiko Schocher <hs@denx.de>
* | SPI: mxc_spi: replace fixed offsets with structuresStefano Babic2011-02-02-0/+35
| | | | | | | | | | | | | | | | This patch cleans driver code replacing all accesses to registers with fixed offsets with a corresponding structure. Signed-off-by: Stefano Babic <sbabic@denx.de>
* | Add support for MX35 processorStefano Babic2011-02-02-0/+2092
| | | | | | | | | | | | | | | | | | | | | | The patch adds basic support for the Freescale's i.MX35 (arm1136 based) processor. The patch adds also a prototype for the initialization of the FEC(ethernet controller) to netdev.h to avoid warnings. Signed-off-by: Stefano Babic <sbabic@denx.de>
* | MX5: Add initial support for MX53 processorLiu Hui-R643432011-02-02-205/+596
|/ | | | | | | | | | Add initial support for Freescale MX53 processor, - Add the iomux support and the pin definition, - Add the regs definition, clean up some unused def from mx51, - Add the low level init support, make use the freq input of setup_pll macro Signed-off-by: Jason Liu <r64343@freescale.com>
* Divides variable of linker flags to LDFLAGS-u-boot and LDFLAGSNobuhiro Iwamatsu2011-01-25-7/+11
| | | | | | | | | | Linker needs to use the proper endian/bfd flags even when doing partial linking. LDFLAGS_u-boot sets linker option which is called it when U-boot is built (u-boot final). LDFLAGS sets necessary option by partial linking (use in cmd_link_o_target). CC: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* ftpmu010: support faraday ftpmu010 driverMacpaul Lin2011-01-25-146/+0
| | | | | | | | | Faraday's ftpmu010 is a power managemnet unit which support cpu sleep and frequency scaling. It has been integrated into many SoC. This patch also move ftpmu010 to a proper place for later enhancement. Signed-off-by: Macpaul Lin <macpaul@andestech.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2011-01-25-157/+1639
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| * powerpc/8xxx: Fix compile warning when build for a DDR1 or DDR2 boardKumar Gala2011-01-24-1/+1
| | | | | | | | | | | | | | | | | | ctrl_regs.c: In function 'set_ddr_sdram_mode_2': ctrl_regs.c:690:6: warning: unused variable 'i' 'i' is only used by DDR3 code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Protect all LBC code with CONFIG_FSL_LBCDipen Dudhat2011-01-19-2/+13
| | | | | | | | | | | | | | | | | | Future SoC (like the P1010) replace the LBC controller with the new IFC (Integrated Flash Controller) so ensure we properly protect code that is related to the LBC. Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/p4080: Fix warning in serdes code from early use of hwconfigYork Sun2011-01-19-3/+14
| | | | | | | | | | | | | | Hwconfig is called before relocating. Use the new hwconfig APIs. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * corenet_ds: Extend board specific parametersYork Sun2011-01-19-0/+3
| | | | | | | | | | | | | | | | | | Extend board specific parameters to include cpo, write leveling override Extend write leveling sample to 0xf Adding rcw overrid for quad-rank RDIMMs Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * mpc85xx: Implement workaround for erratum DDR-A003York Sun2011-01-19-1/+103
| | | | | | | | | | | | | | | | Erratum DDR-A003 requires workaround to correctly set RCW10 for registered DIMM. Also adding polling after enabling DDR controller to ensure completion. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * mpc85xx: Enable unique mode registers and dynamic ODT for DDR3York Sun2011-01-19-54/+530
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added fsl_ddr_get_version() function to for DDR3 to poll DDRC IP version (major, minor, errata) to determine if unique mode registers are available. If true, always use unique mode registers. Dynamic ODT is enabled if needed. The table is documented in doc/README.fsl-ddr. This function may also need to be extend for future other platforms if such a feature exists. Enable address parity and RCW by default for RDIMMs. Change default output driver impedance from 34 ohm to 40ohm. Make it 34ohm for quad-rank RDIMMs. Use a formula to calculate rodt_on for timing_cfg_5. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * mpc85xx: Adding more registers and optionsYork Sun2011-01-19-22/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch exposes more registers which can be used by the DDR drivers or interactive debugging. U-boot doesn't use all the registers in DDRC. When advanced tuning is required, writing to those registers is needed. Add writing to cdr1, cdr2, err_disable, err_int_en and debug registers Add options to override rcw, address parity to RDIMMs. Use array for debug registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * mpc8xxx: Enable ECC on/off control in hwconfigYork Sun2011-01-19-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add fsl_ddr:ecc=on in hwconfig. If ECC is enabled in board configuration file, ECC can be turned on/off by this switch. If this switch is omitted, it is ON by default. Updated hwconfig calls to use local buffer. Syntax is hwconfig=fsl_ddr:ecc=on Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * mpc8xxx: Display RDIMM if detectedYork Sun2011-01-19-12/+8
| | | | | | | | | | | | | | Print a message when a RDIMM is detected. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/8xxx: Introduce 85xx, 86xx, QorIQ config headersKumar Gala2011-01-19-31/+235
| | | | | | | | | | | | | | | | | | | | | | Add new headers that capture common defines for a given SoC/processor rather than duplicating that information in board config.h and random other places. Eventually this should be handled by Kconfig & defconfigs Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
| * powerpc/8xxx: Add hwconfig APIs to address early parsing used by DDR initKumar Gala2011-01-19-19/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are several users of the hwconfig APIs (8xxx DDR) before we have the environment properly setup. This causes issues because of the numerous ways the environment might be accessed because of the non-volatile memory it might be stored in. Additionally the access might be so early that memory isn't even properly setup for us. Towards resolving these issues we provide versions of all the hwconfig APIs that can be passed in a buffer to parse and leave it to the caller to determine how to allocate and populate the buffer. We use the _f naming convention for these new APIs even though they are perfectly useable after relocation and the environment being ready. We also now warn if the non-f APIs are called before the environment is ready to allow users to address the issues. Finally, we convert the 8xxx DDR code to utilize the new APIs to hopefully address the issue once and for all. We have the 8xxx DDR code create a buffer on the stack and populate it via getenv_f(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
| * powerpc/p2040: Add various p2040 specific informationKumar Gala2011-01-19-0/+72
| | | | | | | | | | | | | | | | | | | | Add P2040 SoC specific information: * SERDES Table * Added p2040 to cpu_type_list and SVR list * Added number of LAWs for p2040 * Set CONFIG_MAX_CPUS to 4 for p2040 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
generated by cgit v1.1 at 2024-12-28 07:16:14 +0000