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* arm: build some file(s) as ARM mode onlyDavid Müller (ELSOFT AG)2016-02-15-0/+6
| | | | Signed-off-by: David Müller <d.mueller@elsoft.ch>
* arm: the ARM920T is THUMB capable, so select the appropriate ISADavid Müller (ELSOFT AG)2016-02-15-1/+1
| | | | Signed-off-by: David Müller <d.mueller@elsoft.ch>
* arm: make sure board_init_r() is being called using the right mode (ARM / THUMB)David Müller (ELSOFT AG)2016-02-15-1/+5
| | | | Signed-off-by: David Müller <d.mueller@elsoft.ch>
* Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2016-02-14-124/+590
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| * ARM: uniphier: add support for PH1-Pro4 Ace and Sanji boardsMasahiro Yamada2016-02-14-0/+223
| | | | | | | | | | | | | | | | | | | | Initial commit for PH1-Pro4 Ace and Sanji boards. Note: There are two variants for the Ace board in terms of the amount of DDR memory; 1GB or 2GB. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: dts: uniphier: enable I2C channel 2 of ProXstream2 Gentil boardMasahiro Yamada2016-02-14-0/+5
| | | | | | | | | | | | This is used for on-board inter-connection. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: dts: uniphier: add EEPROM node for ProXstream2 Gentil boardMasahiro Yamada2016-02-14-0/+6
| | | | | | | | | | | | | | This board has an EEPROM connected to the I2C channel 0 of the SoC. Its slave address is 0x54. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: adjust DDR clock delay line for ProXstream2Masahiro Yamada2016-02-14-2/+10
| | | | | | | | | | | | | | | | It turned out that DDR channel 2 was not working on ProXstream2 Vodka board. Add the missing ACBLDR0 register setting to adjust the delay between the clock lines and the address/command lines. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: move cmd_ddrmphy.c to fix build errorMasahiro Yamada2016-02-14-0/+0
| | | | | | | | | | | | | | If CONFIG_CMD_DDRMPHY_DUMP is enabled, the build fails. Fixes: 93d92d46cd01 ("ARM: uniphier: add dump command for DDR Multi PHY registers") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: fix makefiles to build cmd_ddr(m)phy.cMasahiro Yamada2016-02-14-1/+8
| | | | | | | | | | | | | | | | The U-Boot proper building needs to descend arch/arm/mach-uniphier/dram to build these commands. Fixes: 93d92d46cd01 ("ARM: uniphier: add dump command for DDR Multi PHY registers") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: remove unused header mio-regs.hMasahiro Yamada2016-02-14-20/+0
| | | | | | | | | | | | | | | | | | This header is no longer used. This is the last file in arch/arm/mach-uniphier/include/mach/. At last, I've succeeded in eliminating the mach directory. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: drop unneeded EHCI pin mux settingsMasahiro Yamada2016-02-14-25/+0
| | | | | | | | | | | | | | These pin mux settings are cared by the pinctrl drivers. Remove the ad-hoc code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: switch over to generic EHCI driverMasahiro Yamada2016-02-14-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | The UniPhier EHCI driver (drivers/usb/host/ehci-uniphier.c) does nothing special but set the base address and handle reset/clock. Since commit 4feefdcfe916 ("usb: add clock support for generic EHCI"), the generic one (drivers/usb/host/ehci-generic.c) can do those, too. We no longer need to stick to the dedicated driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: dts: uniphier: add clocks properties to EHCI nodesMasahiro Yamada2016-02-14-0/+12
| | | | | | | | | | | | This allows the EHCI driver to get clocks from device tree. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: dts: uniphier: add device nodes for MIO control blockMasahiro Yamada2016-02-14-0/+44
| | | | | | | | | | | | | | This block provides clock and reset control for MIO (Media I/O) hardware blocks such as USB2.0, SD card, eMMC, etc. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: dts: uniphier: add device nodes for Peripheral control blockMasahiro Yamada2016-02-14-0/+36
| | | | | | | | | | | | | | This block provides clock and reset control for peripherals such as UART, I2C, IC card, etc. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: dts: uniphier: add device nodes for System Control blocksMasahiro Yamada2016-02-14-0/+36
| | | | | | | | | | | | These are mainly used for controlling clocks and resets. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: dts: uniphier: add reference clock nodesMasahiro Yamada2016-02-14-0/+33
| | | | | | | | | | | | | | | | | | | | Add master clock nodes generated by crystal oscillators. PH1-sLD3, PH1-LD4: 24.576 MHz PH1-Pro4, ProXstream2: 25.000 MHz PH1-Pro5: 20.000 MHz Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * clk: uniphier: add Media I/O clock driver for UniPhier SoCsMasahiro Yamada2016-02-14-0/+1
| | | | | | | | | | | | | | This is the initial commit for the UniPhier clock drivers. Currently, only the Media I/O clock is supported. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: support USB boot mode for ProXstream2 / PH1-LD6b SoCMasahiro Yamada2016-02-14-2/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The USB boot code is too fat and complicated to be included in SPL (at least for now). So, it was implemented as a separate project (what we call USB-loader). The expected boot sequence is as follows: Boot ROM -> USB-loader -> SPL -> U-Boot proper The USB-loader loads the SPL and U-Boot proper from a USB memory onto the locked L2 cache. Then, SPL needs to copy the U-Boot proper to DRAM, so this mode looks like a NOR boot from the view of SPL. However, we want to distinguish between (genuine) NOR boot and USB boot in some places. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: add missing static qualifierMasahiro Yamada2016-02-14-1/+1
| | | | | | | | | | | | This function is for local use in the file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: create early page table at run-timeMasahiro Yamada2016-02-14-38/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | UniPhier SoCs are not equipped with dedicated on-chip SRAM. Instead, locked outer cache is used as RAM area during the early boot stage where DRAM is not ready yet. This effectively means MMU must be always enabled while we are in SPL. Currently, the SPL image for UniPhier SoCs contains the page table statically defined at compile time. It has been a burden because the 16KB page table occupies a quarter memory footprint of the 64KB SPL image. Finally, there is no more room to implement new features in SPL. Setting aside the NOR boot mode, this issue can be solved by creating the page table onto RAM at run time. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: change stack pointer address for SPLMasahiro Yamada2016-02-14-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No special reason for the current stack address 0x0ff08000. Change it to 0x00100000 to simplify the init_page_table. There are two types of SoCs in terms of the load address of SPL. [1] PH1-sLD3, PH1-LD4, PH1-sLD8 SPL is loaded at 0x00040000-0x0004ffff [2] PH1-Pro4, PH1-Pro5, ProXstream2, PH1-LD6b SPL is loaded at 0x00100000-0x0010ffff The new stack area (0x000f8000-0x00100000) should be safe for all the cases. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * spl: define BOOT_DEVICE_USBMasahiro Yamada2016-02-14-0/+1
| | | | | | | | | | | | This enum is referenced from common/spl/spl.c. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: support some more DRAM use cases on PH1-Pro4 boardsMasahiro Yamada2016-02-14-27/+53
| | | | | | | | | | | | | | Some of PH1-Pro4 boards are equipped with larger amount of DRAM than the reference board. Add UMC settings to support them. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | zynqmp: nand: Add Nand driver support for zynqmpSiva Durga Prasad Paladugu2016-02-12-0/+2
|/ | | | | | | | | | Add nand driver support for zynqmp. The Nand controller used in ZynqMP is Arasan Nand Flash controller. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> [scottwood: Fix checkpatch warning] Signed-off-by: Scott Wood <oss@buserror.net>
* Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini2016-02-11-0/+1
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| * video: tegra: Enable the 'lcd' env variable work-aroundSimon Glass2016-02-11-0/+1
| | | | | | | | | | | | | | Enable this option on all tegra boards. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
* | Remove unused CONFIG_MODEM_SUPPORT option and associated dead code.David Müller (ELSOFT AG)2016-02-08-22/+0
| | | | | | | | Signed-off-by: David Müller <d.mueller@elsoft.ch>
* | ARM: dts: k2g: Add keystone net dts filesMugunthan V N2016-02-08-0/+176
| | | | | | | | | | | | | | | | Add keystone net DT support for k2g evm. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | OMAP3_LOGIC: Setup defconfig to enable SPL and NAND bootingAdam Ford2016-02-08-0/+1
| | | | | | | | | | | | | | | | | | | | The defconfig patch will enable the the SPL and NAND settings. The update to Kconfig will allow the SPL to configured in and built. Signed-off-by: Derald D. Woods <woods.technical@gmail.com> Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | serial: serial_stm32: move clock config from driver to boardVikas Manocha2016-02-08-0/+62
| | | | | | | | | | | | | | | | This patch removes the uart clock enable from serial driver & move it in the board code. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-stagingTom Rini2016-02-08-60/+60
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| * | Use correct spelling of "U-Boot"Bin Meng2016-02-06-60/+60
| |/ | | | | | | | | | | | | | | | | | | Correct spelling of "U-Boot" shall be used in all written text (documentation, comments in source files etc.). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-niosTom Rini2016-02-08-0/+7
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| * | nios2: set up the debug UART earlyThomas Chou2016-02-06-0/+7
| |/ | | | | | | | | | | | | Set up the debug UART early if enabled, so that it is ready to use. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com>
* | x86: Drop pci_type1.c and DEFINE_PCI_DEVICE_TABLEBin Meng2016-02-05-60/+0
| | | | | | | | | | | | | | | | | | Now that we have converted all x86 codes to DM PCI, drop pci_type1.c which is only built for legacy PCI. Also per checkpatch.pl warning, DEFINE_PCI_DEVICE_TABLE is now deprecated so drop that too. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | x86: Disable DM_PCI_COMPATBin Meng2016-02-05-3/+0
| | | | | | | | | | | | | | Now that all x86 codes have been converted to use proper DM PCI APIs, it's time to disable the legacy compatible layer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: quark: Use Quark's own PCI config APIsBin Meng2016-02-05-2/+3
| | | | | | | | | | | | | | | | | | There are still two places in Quark's MRC codes that use the generic legacy PCI APIs, but as we are phasing out these legacy APIs, switch to use Quark's own PCI config routines. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | x86: pci: Drop legacy PCI APIsBin Meng2016-02-05-65/+0
| | | | | | | | | | | | | | | | | | Now that we have converted all x86 codes to use DM PCI APIs, drop those legacy ones. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | x86: pci: Use DM PCI APIs in pci_assign_irqs()Bin Meng2016-02-05-3/+3
| | | | | | | | | | | | | | | | Drop legacy PCI APIs usage in pci_assign_irqs() as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | x86: qemu: Convert to use DM PCI APIBin Meng2016-02-05-17/+17
| | | | | | | | | | | | | | | | Use pci_[read|write]_config intead of x86_pci_[read|write]_config. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | x86: tnc: Remove IGD and SDVO devices from driver modelBin Meng2016-02-05-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With recent DM PCI changes to vesa_fb driver, external graphics card does not work any more. This is because: after setting the function disable bit, IGD and SDVO devices will disappear in the PCI configuration space. This however creates an inconsistent state from a driver model PCI controller point of view, as these two PCI devices are still attached to its parent's child device list as maintained by the driver model. Some driver model PCI APIs like dm_pci_find_class() used in the vesa_fb driver, are referring to the list to speed up the finding process instead of re-enumerating the whole PCI bus, so it gets the stale cached data which is wrong. To fix this, manually remove these two devices. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | x86: tnc: Use DM PCI API in disable_igd()Bin Meng2016-02-05-3/+19
| | | | | | | | | | | | | | | | | | Once we get udevice of IGD and SDVO, we can use its udevice to access PCI configuration space with dm_pci_write_config32(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | x86: tnc: Change disable_igd() to have a return valueBin Meng2016-02-05-3/+7
| | | | | | | | | | | | | | | | | | So far disable_igd() does not have any return value, but we may need that in the future. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | x86: irq: Convert to use DM PCI APIBin Meng2016-02-05-4/+4
| | | | | | | | | | | | | | | | | | Now that we have irq router's udevice passed as a parameter, it's time to start using the DM PCI API instead of those legacy ones. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | x86: irq: Move irq_router to a per driver privBin Meng2016-02-05-46/+51
| | | | | | | | | | | | | | | | | | | | | | At present irq_router is declared as a static struct irq_router in arch/x86/cpu/irq.c. Since it's a driver control block, it makes sense to move it to a per driver priv. Adjust existing APIs to accept an additional parameter of irq_router's udevice. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | x86: irq: Get irq_router's bdf via dm_pci_get_bdf()Bin Meng2016-02-05-8/+1
| | | | | | | | | | | | | | | | | | There is no need to parse PCH's <reg> property as we have already a DM PCI API dm_pci_get_bdf() that can handle this. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | x86: minnowmax: Drop io-base property in the pch_pinctrl nodeBin Meng2016-02-05-1/+0
| | | | | | | | | | | | | | | | IOBASE is now obtained from PCH driver, drop this <io-base> property. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | x86: Drop asm/arch/gpio.hBin Meng2016-02-05-89/+0
| | | | | | | | | | | | | | | | | | asm/arch/gpio.h is not needed anymore as we get the GPIO base from PCH driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-12-24 15:11:35 +0000