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* ARM: socfpga: Disable USB OC protection on SoCratesMarek Vasut2016-05-06-0/+1
| | | | | | | | This is mandatory, otherwise the USB does not work. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Dinh Nguyen <dinguyen@kernel.org>
* ARM: tegra: enable GPU node by compatible valueStephen Warren2016-05-04-15/+22
| | | | | | | | | | | | | | | | | | | In current Linux kernel Tegra DT files, 64-bit addresses are represented in unit addresses as a pair of comma-separated 32-bit values. Apparently this is no longer the correct representation for simple busses, and the unit address should be represented as a single 64-bit value. If this is changed in the DTs, arm/arm/mach-tegra/board2.c:ft_system_setup() will no longer be able to find and enable the GPU node, since it looks up the node by name. Fix that function to enable nodes based on their compatible value rather than their node name. This will work no matter what the node name is, i.e for DTs both before and after any rename operation. Cc: Thierry Reding <treding@nvidia.com> Cc: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Change my mailaddressAndreas Bießmann2016-05-02-7/+7
| | | | | | I'll switch my mails to my own server, so drop all gmail references. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* arch/arm/imx-common/Makefile: Update u-boot.uim MKIMAGEFLAGSTom Rini2016-05-02-1/+1
| | | | | | We need to be passing -T firmware here and aren't. Signed-off-by: Tom Rini <trini@konsulko.com>
* Revert "rockchip: rk3288: correct sdram setting"Vagrant Cascadian2016-05-02-7/+7
| | | | | | | | | | This reverts commit b5788dc0dd9570e98552833767f4373db965985d. Ram size is incorrectly reported as 512MB on a firefly-rk3288 board with 2GB of ram. Reverting this patch displays the full amount of ram. Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Acked-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2016-05-02-29/+47
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| * ARM: uniphier: move pin-mux code into pin_init functionMasahiro Yamada2016-05-01-27/+5
| | | | | | | | | | | | | | The code in uniphier_sld3_sbc_init() is pin-muxing, so it would be a better fit in uniphier_sld3_early_pin_init(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: allow to use System Bus for ROM boot mode of PH1-LD20Masahiro Yamada2016-05-01-1/+37
| | | | | | | | | | | | | | | | | | The System Bus is not available by default on the ROM boot mode of PH1-LD20. To use devices connected to the System Bus, such as the Micro Support Card, it is necessary to set up pin-muxing and some System Bus Controller register. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: enable Peripherl clock to use UART in SPLMasahiro Yamada2016-05-01-0/+4
| | | | | | | | | | | | This is needed to use UART on SPL. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: fix boot mode table of PH1-LD20Masahiro Yamada2016-05-01-1/+1
| | | | | | | | | | | | | | PH1-LD20 does not have the dedicated boot swap select latch. Instead, it is controlled from the boot mode select. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Revert "omap3: Use raw SPL by default for mmc1"Tom Rini2016-05-02-0/+2
|/ | | | | | | | | | | | | Unfortunately with this change we now are unable to do FS mode boots from MMC1 as with the way the code works today we will always load and assume that the hard-coded raw location contains U-Boot. Further, we cannot fix this by just changing other logic to try FS-then-RAW as it would also make us have to ignore what order the ROM is telling us to try. This reverts commit 22d90d560a2b01c47f180e196e6c6485eb8e65db. Signed-off-by: Tom Rini <trini@konsulko.com>
* sunxi: mctl_mem_matches: Add missing memory barrierHans de Goede2016-04-27-0/+2
| | | | | | | | | | | | | | | | | | | | | | | We are running with the caches disabled when mctl_mem_matches gets called, but the cpu's write buffer is still there and can still get in the way, add a memory barrier to fix this. This avoids mctl_mem_matches always returning false in some cases, which was resulting in: U-Boot SPL 2015.07 (Apr 14 2016 - 18:47:26) DRAM: 1024 MiB U-Boot 2015.07 (Apr 14 2016 - 18:47:26 +0200) Allwinner Technology CPU: Allwinner A23 (SUN8I) DRAM: 512 MiB Where 512 MiB is the right amount, but the DRAM controller would be initialized for 1024 MiB. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARM: DRA7: Add ABB setup for all domainsNishanth Menon2016-04-25-0/+52
| | | | | | | | | | | | | ABB should be initialized for all required domains voltage domain for DRA7: IVA, GPU, EVE in addition to the existing MPU domain. If we do not do this, kernel configuring just the frequency using the default boot loader configured voltage can fail on many corner lot units and has been hard to debug. This specifically is a concern with DRA7 generation of SoCs since other than VDD_MPU, all other domains are only permitted to setup the voltages to required OPP only at boot. Reported-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: OMAP5: Enable ABB configuration for MM voltage domainNishanth Menon2016-04-25-0/+19
| | | | | | | | | | Since we setup the voltage and frequency for the MM domain, we *must* setup the ABB configuration needed for the domain as well. If we do not do this, kernel configuring just the frequency using the default boot loader configured voltage can fail on many corner lot units. Reported-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: OMAP5/DRA7: Move ABB TXDONE mask to voltage structureNishanth Menon2016-04-25-2/+7
| | | | | | | | | | | ABB TX_DONE mask will vary depending on ABB module. For example, 3630 never had ABB on IVA domain, while OMAP5 does use ABB on MM domain, DRA7 has it on all domains with the exception of CORE, RTC. Hence, move the txdone mask definition over to structure describing voltage domain. Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: OMAP5/DRA7: Get rid of control_std_fuse_opp_vdd_mpu_2Nishanth Menon2016-04-25-5/+2
| | | | | | | | | | | | | This information is already available under vcores->volts.efuse.reg. There is no reason for duplicating the information since AVS Class 0 definitions are common for OMAP5 and DRA7 and defined with STD_FUSE_OPP_* macros. This allows a central location of defining the ABB and voltage definitions especially since they are reused. This also makes it simpler to prevent mistakes involved when changing the boot OPP for the device. Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: hisilicon: hikey: dts: Add pl011 additional clock binding.Peter Griffin2016-04-25-0/+5
| | | | | | | | This is a binding which only exists in U-Boot, but is required to get working serial in U-Boot. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: hisilicon: hikey: Enable OF_CONTROL for hikey board.Peter Griffin2016-04-25-0/+3
| | | | | | | | | | | Currently only the serial pl01x driver is using DT, and the other drivers still use platform data but as more DT lands in the upstream kernel the aim is to migrate the other drivers over to DT as well to have a fully DT configured hikey u-boot. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: hisilicon: hikey: Add hikey & hi6220 dts from v4.6-rc3.Peter Griffin2016-04-25-0/+254
| | | | | | | | | Import the upstream kernel dts into U-Boot. Currently only serial is supported, but a lot more DT changes are queued for v4.7. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* configs: Re-sync with cmd/KconfigTom Rini2016-04-25-6/+0
| | | | | | | Update the config.h and defconfig files for the commands that 8e3c036 converted over to Kconfig Signed-off-by: Tom Rini <trini@konsulko.com>
* configs: Re-sync almost all of cmd/KconfigTom Rini2016-04-25-4/+0
| | | | | | | | This syncs up the current cmd/Kconfig and include/configs/ files with the only exception being CMD_NAND. Due to how we have used this historically we need to take further care here when converting. Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-uniphierTom Rini2016-04-25-60/+969
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| * ARM: dts: uniphier: add SD controller node for PH1-LD20Masahiro Yamada2016-04-24-0/+17
| | | | | | | | | | | | | | PH1-LD20 does not support 1.8V signaling for SD card; only Default Speed and High Speed (up to 50MHz) with 3.3V signaling is supported. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: add PH1-LD20 SoC supportMasahiro Yamada2016-04-24-3/+888
| | | | | | | | | | | | This is the first ARMv8 SoC from Socionext Inc. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: rework uniphier_set_fdt_file()Masahiro Yamada2016-04-24-31/+31
| | | | | | | | | | | | | | | | | | | | | | | | The current table look-up for the DTB file name turned out bothersome in terms of maintainability; I ended up adding a new entry every time a new board is supported. There is a common pattern between the DT compatible string and the corresponding file name; drop the vendor prefix "socionext," and prefix it with "uniphier-" and suffix it with ".dtb". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: carry on booting for Unknown boot modeMasahiro Yamada2016-04-24-2/+2
| | | | | | | | | | | | | | | | No need to stop booting U-Boot even if boot mode is unknown. Setting the "bootmode" environment is only useful for booting Linux Kernel. Anyway, U-Boot has already booted by this point. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: add sg_set_iectrl_range()Masahiro Yamada2016-04-24-0/+8
| | | | | | | | | | | | | | | | For PH1-LD20 or later, per-pin input-enable control is supported, that is, we need to set-up IECTRL registers for a group of pins. This helper function will be useful for a bunch of register settings. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: dts: uniphier: move aliases node up to satisfy fdtgrepMasahiro Yamada2016-04-24-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, fdtgrep would not accept uniphier-ph1-ld20-ref.dtb and uniphier-ph1-ld11-ref.dtb unless the aliases node comes the first in the root node. $ make -s uniphier_pxs2_ld6b_defconfig $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-ld20-ref [snip] LDS spl/u-boot-spl.lds LD spl/u-boot-spl OBJCOPY spl/u-boot-spl-nodtb.bin FDTGREP spl/u-boot-spl.dtb Error at 'fdt_find_regions': FDT_ERR_BADLAYOUT /aliases node must come before all other nodes Error: FDT_ERR_BADMAGIC make[1]: *** [spl/u-boot-spl.dtb] Error 1 make: *** [spl/u-boot-spl] Error 2 This commit moves the aliases node as the error message from the fdtgrep tool suggests, although this requirement does not sound reasonable to me. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: dts: uniphier: use Ref Daughter board on PH1-LD20 Ref boardMasahiro Yamada2016-04-24-0/+1
| | | | | | | | | | | | | | This makes the EEPROM device on the Reference Daughter board available. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: avoid unaligned access to DT on 64bit SoCMasahiro Yamada2016-04-24-6/+4
| | | | | | | | | | | | | | Because DT properties are 4-byte aligned, the pointer access *(fdt64_t *) in this code causes unaligned access. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-04-25-1/+167
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| * Add initial support for Technexion's PICO-IMX6UL-EMMC boardFabio Estevam2016-04-19-0/+5
| | | | | | | | | | | | | | | | | | | | Add support for Technexion's PICO-IMX6UL-EMMC board. For information about this board, please visit: http://www.technexion.com/products/pico/pico-som/pico-imx6-emmc Signed-off-by: Richard Hu <richard.hu@technexion.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
| * MX6UL: Add definition for UART6 base addressFabio Estevam2016-04-19-0/+1
| | | | | | | | | | | | Define the UART6_BASE_ADDR for MX6UL. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
| * imx: mx6: Fix procedure to switch the parent of LDB_DI_CLKAkshay Bhat2016-04-19-0/+160
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to enter the ldb_di_ipu_div divider. If the divider gets locked up, no ldb_di[x]_clk is generated, and the LVDS display will hang when the ipu_di_clk is sourced from ldb_di_clk. To fix the problem, both the new and current parent of the ldb_di_clk should be disabled before the switch. This patch ensures that correct steps are followed when ldb_di_clk parent is switched in the beginning of boot. This patch was ported from the 3.10.17 NXP kernel http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_3.10.17_1.0.1_ga&id=eecbe9a52587cf9eec30132fb9b8a6761f3a1e6d NXP errata number: ERR009219, EB821 Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com>
| * arm: mx5: Fix NAND image generationMarek Vasut2016-04-19-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The echo -ne "\xNN" does not work in certain bourne-compatible shells, like dash. The recommended way of hex->char conversion is using printf(1), but there is a pitfall here. The GNU printf does support "\xNN" format, but according to the opengroup documentation, this is not part of POSIX. The POSIX printf only defines "\NNN" where N is octal. Thus, for the sake of compatibility, we use that. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2016-04-22-891/+1
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| * | x86: Correct typo of Miao Yan's email addressBin Meng2016-04-22-1/+1
| | | | | | | | | | | | | | | | | | Miao Yan's email address is wrong in fw_cfg.c. Fix it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: qemu: Drop our own ACPI implementationBin Meng2016-04-22-890/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Our own ACPI implementation (when CONFIG_QEMU_ACPI_TABLE is not set) does not build anymore after x86 has been fully converted to DM PCI. Instead of trying to fix the build errors, given we now have the ACPI support via QEMU's fw_cfg interface, which is a more reliable way to generate correct ACPI tables than by ourselves, hence drop our own ACPI implementation. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | arc/cache: really do flush_dcache_all() even if IOC existsAlexey Brodkin2016-04-21-5/+2
|/ / | | | | | | | | | | | | | | | | | | | | | | flush_dcache_all() is used in the very end of U-Boot self relocation to write back all copied and then patched code and data to their new location in the very end of available memory space. Since that has nothing to do with IO (i.e. no external DMA happens here) IOC won't help here and we need to write back data cache contents manually. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2016-04-20-3/+8
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| * | arm: socfpga: socrates: Add eth0 alias to enable ethernetStefan Roese2016-04-20-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This enables full ethernet usage, including U-Boot to write the board specific MAC address (ethaddr) into the DT blob before passing it to Linux. Without this, the ethaddr is not detected in U-Boot at all, resulting in this error upon bootup: ... Model: EBV SOCrates Net: Error: ethernet@ff702000 address not set. No ethernet found. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
| * | arm: socfpga: Fix typos in DT files (environmnet -> environment)Stefan Roese2016-04-20-3/+3
| |/ | | | | | | | | | | | | | | | | | | Fix a small typo in some of the SoCFPGA dts files that has spread via copy-and-paste. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2016-04-19-2/+3
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| * | MIPS: bootm: Add fixup of '/memory' node.Purna Chandra Mandal2016-04-19-2/+3
| |/ | | | | | | | | | | | | | | | | | | | | | | MIPS arch do not update 'reg' property of /memory node. As a result Linux bootup will not work unless board.dts file contains right /memory offset-size information or board implements required memory fixup. Fixing by renaming (unused) _arch_fixup_memory_node_ to _arch_fixup_fdt_ in arch/mips/lib/bootm.c inline with ARM arch. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | ARM: always perform per-CPU GIC initStephen Warren2016-04-18-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code in ARMv8's lowlevel_init() skips the per-CPU GIC initialization ifndef CONFIG_ARMV8_MULTIENTRY. However, the per-CPU init should always occur; it's just the one-time init that should only happen on the master. Once this consideration is taken into account, the only difference between the paths when CONFIG_ARMV8_MULTIENTRY is undefined/defined is the use of branch_if_slave. Naively, any unified code would need to invoke this conditionally upon ifdef CONFIG_ARMV8_MULTIENTRY. However, branch_if_slave already checks CONFIG_ARMV8_MULTIENTRY and does nothing if it isn't defined, so we don't even need that ifdef at the call site. Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | sandbox: Set CONFIG_SYS_CPUTom Rini2016-04-18-0/+3
| | | | | | | | | | | | | | Give a valid value here as well to allow things which want CONFIG_ENV_VARS_UBOOT_CONFIG to build Signed-off-by: Tom Rini <trini@konsulko.com>
* | ARM: AM43xx: Fix BOOT_DEVICE_USB IDLokesh Vutla2016-04-18-1/+2
| | | | | | | | | | | | | | | | | | commit 62c5674ea136a ("omap: SPL boot devices cleanup and completion") cleans up the boot device ids for amx3xx soc. But mistakenly updates wrong device IDs for AM43xx USB. Fixing the same here. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | m68k: fix broken buildman m68kangelo@sysam.it2016-04-18-8/+24
| | | | | | | | | | | | | | | | | | fix 19/48 broken board compilations, due to a now too smal 16-bit relative jump Signed-off-by: Angelo Dureghello <angelo@sysam.it> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
* | ARM: dts: dra7xx: am57xx: fix cd-gpios definition as per hardware design and ↵Mugunthan V N2016-04-18-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dt binding docs As per mmc device tree binding documentation card detect gpio has to be active low signal. When a hardware is designed with active high card detect, gpio polarity has to be changed with cd-inverted dt property. In DRA72x and AM57xx EVMs the card detect gpio is designed as active low gpio. So correcting the dt card detect gpio definition. Also adding card-detect gpio for DRA74x EVM. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: dts: am43xx: fix cd-gpios definition as per hardware design and dt ↵Mugunthan V N2016-04-18-2/+2
|/ | | | | | | | | | | | | | | binding docs As per mmc device tree binding documentation card detect gpio has to be active low signal. When a hardware is designed with active high card detect, gpio polarity has to be changed with cd-inverted dt property. In AM43xx the card detect gpio is designed as active low gpio. So correcting the dt card detect gpio definition. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
generated by cgit v1.1 at 2024-12-24 10:52:31 +0000