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* ARM: zynq: Move ps7_init() out of spl.hMichal Simek2014-08-19-2/+2
| | | | | | | Prepare for spl.h removal. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* zynq: spl: Add vectors section to linker scriptPeter Crosthwaite2014-08-08-0/+1
| | | | | | | | | | | | | | | | | | The vectors section contains the _start symbol which is used as the program entry point. Add it to the linker script in same fashion as done for regular u-boot. This allows for correct generation of an spl elf with a non-zero entry point. A similar change was applied to sunxi platform in "sunxi: Fix u-boot-spl.lds to refer to .vectors" (sha1: 9e5f80d823e3fd2a685b10ecf02009e34b86cff9) This also allows for placement of the vector table at the hivecs location by setting the TEXT_BASE to 0xffff0000. Tested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-08-06-1/+17
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| * powerpc: mpc85xx watchdog init added to init_funcBoschung, Rainer2014-08-01-0/+3
| | | | | | | | | | | | | | | | | | | | | | When CONFIG_WATCHDOG is defined the board initialization just performs a WATCHDOG_RESET, an initialization of the watchdog is not done. This has been modified fot the MPC85xx, the board initialization calls its watchdog initialitzation allowing for full watchdog configuration very early in the boot phase. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * mpc85xx: watchdog initialisation addedBoschung, Rainer2014-08-01-0/+8
| | | | | | | | | | | | | | | | Function to inititialize the cpu watchdog added. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> [York Sun: Add prototype in watchdog.h] Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc: macros for e500mc timer regs addedBoschung, Rainer2014-08-01-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For e500mc cores the watchdog timer period has to be set by means of a 6bit value, that defines the bit of the timebase counter used to signal a watchdog timer exception on its 0 to 1 transition. The macro used to set the watchdog period TCR_WP, was redefined for e500mc to support 6 WP setting. The parameter (x) given to the macro specifies the prescaling factor of the time base clock (fTB): watchdog_period = 1/fTB * 2^x Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * mpc85xx: fix interrupt init to not affect watchdogBoschung, Rainer2014-08-01-1/+1
| | | | | | | | | | | | | | | | TCR watchdog bit are overwritten when dec interrupt is enabled. This has been fixed with this patch. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | Merge http://git.denx.de/u-boot-dmTom Rini2014-08-04-0/+14
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| * | arm: Support pre-relocation malloc()Simon Glass2014-08-04-1/+4
| | | | | | | | | | | | | | | | | | Add support for re-relocation malloc() in arm's start-up code. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | arm: Set up global data before board_init_f()Simon Glass2014-08-04-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present arm defines CONFIG_SYS_GENERIC_GLOBAL_DATA, meaning that the global_data pointer is set up in board_init_f(). However it is actually set up before this, it just isn't zeroed. If we zero the global data before calling board_init_f() then we don't need to define CONFIG_SYS_GENERIC_GLOBAL_DATA. Make this change (on arm32 only) to simplify the init process. I don't have the ability to test aarch64 yet. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Tom Rini <trini@ti.com>
* | | mmc: s3c: Add SD driverMarek Vasut2014-08-01-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement SD driver for the S3C24xx family. This implementation is currently only capable of using the PIO transfers, DMA is not supported. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* | | arm: s3c: Unify the S3C24xx SDI structureMarek Vasut2014-08-01-11/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unify the register structure so they can be easily used across all of S3C24xx lineup. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* | | ARM: kirkwood: add mvsdio driverDrEagle2014-08-01-0/+10
|/ / | | | | | | | | | | | | | | | | This patch add Marvell kirkwood MVSDIO/MMC driver and enable it for Sheevaplugs and OpenRD boards. Signed-off-by: Gerald Kerma <drEagle@doukki.net> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* | powerpc: remove redundant CPU definitionMasahiro Yamada2014-07-30-12/+11
| | | | | | | | | | | | | | | | CONFIG_${CPU} is defined by Kconfig. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Stefan Roese <sr@denx.de>
* | kconfig: delete redundant CONFIG_${ARCH} definitionMasahiro Yamada2014-07-30-13/+11
| | | | | | | | | | | | | | CONFIG_${ARCH} is defined by Kconfig. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | kconfig: switch to KconfigMasahiro Yamada2014-07-30-15/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit enables Kconfig. Going forward, we use Kconfig for the board configuration. mkconfig will never be used. Nor will include/config.mk be generated. Kconfig must be adjusted for U-Boot because our situation is a little more complicated than Linux Kernel. We have to generate multiple boot images (Normal, SPL, TPL) from one source tree. Each image needs its own configuration input. Usage: Run "make <board>_defconfig" to do the board configuration. It will create the .config file and additionally spl/.config, tpl/.config if SPL, TPL is enabled, respectively. You can use "make config", "make menuconfig" etc. to create a new .config or modify the existing one. Use "make spl/config", "make spl/menuconfig" etc. for spl/.config and do likewise for tpl/.config file. The generic syntax of configuration targets for SPL, TPL is: <target_image>/<config_command> Here, <target_image> is either 'spl' or 'tpl' <config_command> is 'config', 'menuconfig', 'xconfig', etc. When the configuration is done, run "make". (Or "make <board>_defconfig all" will do the configuration and build in one time.) For futher information of how Kconfig works in U-Boot, please read the comment block of scripts/multiconfig.py. By the way, there is another item worth remarking here: coexistence of Kconfig and board herder files. Prior to Kconfig, we used C headers to define a set of configs. We expect a very long term to migrate from C headers to Kconfig. Two different infractructure must coexist in the interim. In our former configuration scheme, include/autoconf.mk was generated for use in makefiles. It is still generated under include/, spl/include/, tpl/include/ directory for the Normal, SPL, TPL image, respectively. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* | kconfig: add basic Kconfig filesMasahiro Yamada2014-07-30-0/+66
| | | | | | | | | | | | | | This commit adds more Kconfig files, which were written by hand. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* | kconfig: add board Kconfig and defconfig filesMasahiro Yamada2014-07-30-0/+2883
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds: - arch/${ARCH}/Kconfig provide a menu to select target boards - board/${VENDOR}/${BOARD}/Kconfig or board/${BOARD}/Kconfig set CONFIG macros to the appropriate values for each board - configs/${TARGET_BOARD}_defconfig default setting of each board (This commit was automatically generated by a conversion script based on boards.cfg) In Linux Kernel, defconfig files are located under arch/${ARCH}/configs/ directory. It works in Linux Kernel since ARCH is always given from the command line for cross compile. But in U-Boot, ARCH is not given from the command line. Which means we cannot know ARCH until the board configuration is done. That is why all the "*_defconfig" files should be gathered into a single directory ./configs/. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-07-29-692/+3167
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| * | ARM: HYP/non-sec: remove MIDR check to validate CBARMarc Zyngier2014-07-28-17/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Having a form of whitelist to check if we know of a CPU core and and obtain CBAR is a bit silly. It doesn't scale (how about A12, A17, as well as other I don't know about?), and is actually a property of the SoC, not the core. So either it works and everybody is happy, or it doesn't and the u-boot port to this SoC is providing the real address via a configuration option. The result of the above is that this code doesn't need to exist, is thus forcefully removed. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | ARM: HYP/non-sec/PSCI: emit DT nodesMarc Zyngier2014-07-28-2/+112
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Generate the PSCI node in the device tree. Also add a reserve section for the "secure" code that lives in in normal RAM, so that the kernel knows it'd better not trip on it. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | ARM: convert arch_fixup_memory_node to a generic FDT fixup functionMa Haijun2014-07-28-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some architecture needs extra device tree setup. Instead of adding yet another hook, convert arch_fixup_memory_node to be a generic FDT fixup function. [maz: collapsed 3 patches into one, rewrote commit message] Signed-off-by: Ma Haijun <mahaijuns@gmail.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | ARM: HYP/non-sec: add the option for a second-stage monitorMarc Zyngier2014-07-28-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow the switch to a second stage secure monitor just before switching to non-secure. This allows a resident piece of firmware to be active once the kernel has been entered (the u-boot monitor is dead anyway, its pages being reused). Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | ARM: HYP/non-sec: add generic ARMv7 PSCI codeMarc Zyngier2014-07-28-0/+141
| | | | | | | | | | | | | | | | | | | | | | | | | | | Implement core support for PSCI. As this is generic code, it doesn't implement anything really useful (all the functions are returning Not Implemented). Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | ARM: HYP/non-sec: allow relocation to secure RAMMarc Zyngier2014-07-28-140/+138
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current non-sec switching code suffers from one major issue: it cannot run in secure RAM, as a large part of u-boot still needs to be run while we're switched to non-secure. This patch reworks the whole HYP/non-secure strategy by: - making sure the secure code is the *last* thing u-boot executes before entering the payload - performing an exception return from secure mode directly into the payload - allowing the code to be dynamically relocated to secure RAM before switching to non-secure. This involves quite a bit of horrible code, specially as u-boot relocation is quite primitive. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | ARM: HYP/non-sec: add separate section for secure codeMarc Zyngier2014-07-28-1/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In anticipation of refactoring the HYP/non-secure code to run from secure RAM, add a new linker section that will contain that code. Nothing is using it just yet. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | ARM: add missing HYP mode constantMarc Zyngier2014-07-28-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to be able to use the various mode constants (far more readable than random hex values), add the missing HYP and A values. Also update arm/lib/interrupts.c to display HYP instead of an unknown value. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | ARM: non-sec: reset CNTVOFF to zeroMarc Zyngier2014-07-28-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before switching to non-secure, make sure that CNTVOFF is set to zero on all CPUs. Otherwise, kernel running in non-secure without HYP enabled (hence using virtual timers) may observe timers that are not synchronized, effectively seeing time going backward... Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | ARM: HYP/non-sec: add a barrier after setting SCR.NS==1Marc Zyngier2014-07-28-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | A CP15 instruction execution can be reordered, requiring an isb to be sure it is executed in program order. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | ARM: HYP/non-sec: move switch to non-sec to the last boot phaseMarc Zyngier2014-07-28-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Having the switch to non-secure in the "prep" phase is causing all kind of troubles, as that stage can be called multiple times. Instead, move the switch to non-secure to the last possible phase, when there is no turning back anymore. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2014-07-28-521/+813
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| | * | ARM: omap: clean redundant PISMO_xx macros used in OMAP3pekon gupta2014-07-25-23/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PISMO_xx macros were used to define 'Platform Independent Storage MOdule' related GPMC configurations. This patch - Replaces these OMAP3 specific macros with generic CONFIG_xx macros as provided by current u-boot infrastructure. - Removes unused redundant macros, which are no longer required after merging of common platform code in following commit commit a0a37183bd75e74608bc78c8d0e2a34454f95a91 ARM: omap: merge GPMC initialization code for all platform +-----------------+-----------------------------------------------------------+ | Macro | Reason for removal | +-----------------+-----------------------------------------------------------+ | PISMO1_NOR_BASE | duplicate of CONFIG_SYS_FLASH_BASE | +-----------------+-----------------------------------------------------------+ | PISMO1_NAND_BASE| duplicate of CONFIG_SYS_NAND_BASE | +-----------------+-----------------------------------------------------------+ | PISMO1_ONEN_BASE| duplicate of CONFIG_SYS_ONENAND_BASE | +-----------------+-----------------------------------------------------------+ | PISMO1_NAND_SIZE| GPMC accesses NAND device via I/O mapped registers so | | | configuring GPMC chip-select for smallest allowable | | | segment (GPMC_SIZE_16M) is enough. | +-----------------+-----------------------------------------------------------+ | PISMO1_ONEN_SIZE| OneNAND uses a fixed GPMC chip-select address-space of | | | 128MB (GPMC_SIZE_128M) | +-----------------+-----------------------------------------------------------+ +-----------------+-----------------------------------------------------------+ | PISMO1_NOR | Unused Macros | | PISMO1_NAND | | | PISMO2_CS0 | | | PISMO2_CS1 | | | PISMO1_ONENAND | | | PISMO2_NAND_CS0 | | | PISMO2_NAND_CS1 | | | PISMO1_NOR_BASE | | | PISMO1_NAND_BASE| | | PISMO2_CS0_BASE | | +-----------------+-----------------------------------------------------------+ Signed-off-by: Pekon Gupta <pekon@ti.com>
| | * | ARM: omap: fix GPMC address-map size for NAND and NOR devicespekon gupta2014-07-25-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes commit a0a37183bd75e74608bc78c8d0e2a34454f95a91 ARM: omap: merge GPMC initialization code for all platform 1) NAND device are not directly memory-mapped to CPU address-space, they are indirectly accessed via following GPMC registers: - GPMC_NAND_COMMAND_x - GPMC_NAND_ADDRESS_x - GPMC_NAND_DATA_x Therefore from CPU's point of view, NAND address-map can be limited to just above register addresses. But GPMC chip-select address-map can be configured in granularity of 16MB only. So this patch uses GPMC_SIZE_16M for all NAND devices. 2) NOR device are directly memory-mapped to CPU address-space, so its address-map size depends on actual addressable region in NOR FLASH device. So this patch uses CONFIG_SYS_FLASH_SIZE to derive GPMC chip-select address-map size configuration. Signed-off-by: Pekon Gupta <pekon@ti.com>
| | * | ARM: OMAP: Fix handling of errata i727Rajendra Nayak2014-07-25-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The errata is applicable on all OMAP4 (4430 and 4460/4470) and OMAP5 ES 1.0 devices. The current revision check erroneously implements this on all DRA7 varients and with DRA722 device (which has only 1 EMIF instance) infact causes an asynchronous abort and ends up masking it in CPSR, only to be uncovered once the kernel switches to userspace. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| | * | board: k2e-evm: add board supportHao Zhang2014-07-25-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds Keystone2 k2e_evm evaluation board support. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * | ARM: keystone2: spl: add K2E SoC supportKhoronzhuk, Ivan2014-07-25-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Keystone2 K2E SoC has slightly different spl pll settings then K2HK, so correct this. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * | ARM: keystone2: add MSMC cache coherency support for K2E SOCHao Zhang2014-07-25-8/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds Keystone2 K2E SOC specific code to support MSMC cache coherency. Also create header file for msmc to hold its API. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * | ARM: keystone2: clock: add K2E clock supportHao Zhang2014-07-25-5/+202
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds clock definitions and commands to support Keystone2 K2E SOC. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * | ARM: keystone2: add K2E SoC hardware definitionsHao Zhang2014-07-25-44/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds hardware definitions specific to Keystone II K2E device. It has a lot common definitions with k2hk SoC, so move them to common hardware.h. This is preparation patch for adding K2E SoC support. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * | ARM: keystone: clock: move K2HK SoC dependent code in separate fileKhoronzhuk, Ivan2014-07-25-145/+166
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch in general spit SoC type clock dependent code and general clock code. Before adding keystone II Edison k2e SoC which has slightly different dpll set, move k2hk dependent clock code to separate clock-k2hk.c file. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * | k2hk: use common KS2_ prefix for all hardware definitionsKhoronzhuk, Ivan2014-07-25-130/+120
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use KS2_ prefix in all definitions, for that replace K2HK_ prefix and add KS2_ prefix where it's needed. It requires to change names also in places where they're used. Align lines and remove redundant definitions in kardware-k2hk.h at the same time. Using common KS2_ prefix helps resolve redundant redefinitions and adds opportunity to use KS2_ definition across a project not thinking about what SoC should be used. It's more convenient and we don't need to worry about the SoC type in common files, hardware.h will think about that. The hardware.h decides definitions of what SoC to use. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * | keystone2: add possibility to turn off all dspsHao Zhang2014-07-25-2/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By default all DSPs are turned off, for another case option to turn off them is added in this commit. Also add command to turn off itself. Acked-by: Murali Karicheri <m-maricheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * | keystone2: move cpu_to_bus() to keystone.cHao Zhang2014-07-25-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SoC related common functions in board.c should be placed to a common keystone.c arch file. Acked-by: Murali Karicheri <m-maricheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * | ARM: keystone2: keystone_nav: make it dependent on keystone driverKhoronzhuk, Ivan2014-07-25-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver is needed in case if keystone driver is used. Currently only keystone_net driver uses it. So to avoid redundant code compilation make the keystone_nav dependent on keystone net driver. It also leads to compilation errors for boards that does't use it. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * | keystone2: ddr: add DDR3 PHY configs updated for PG 2.0Hao Zhang2014-07-25-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add DDR3 PHY configs updated for PG 2.0 Also add DDR3A PHY reset before init for PG2.0 SoCs. Acked-by: Murali Karicheri <m-maricheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * | keystone: ddr3: add ddr3.h to hold ddr3 APIKhoronzhuk, Ivan2014-07-25-42/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's convinient to hold ddr3 function definitions in separate file such as ddr3.h. So move this from hardware.h to ddr3.h. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * | ARM: keystone2: psc: use common PSC baseKhoronzhuk, Ivan2014-07-25-24/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use common keystone2 Power Sleep controller base address instead of directly deciding which keystone2 SoC is used in psc module. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * | ARM: omap: Remove unused arch/arm/cpu/armv7/omap3/mem.cStefan Roese2014-07-25-139/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These functions have been merged into the common GPMC init code with this commit a0a37183 (ARM: omap: merge GPMC initialization code for all platform). The file is not compiled any more. So remove it as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Pekon Gupta <pekon@ti.com> Cc: Tom Rini <trini@ti.com> Acked-by: Pekon Gupta <pekon@ti.com>
| | * | ARM: omap: Fix GPMC init for OMAP3 platformsStefan Roese2014-07-25-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit a0a37183 (ARM: omap: merge GPMC initialization code for all platform) broke NAND on OMAP3 based platforms. I noticed this while testing the latest 2014.07-rc version on the TAO3530 board. NAND detection did not work with this error message: NAND: nand: error: Unable to find NAND settings in GPMC Configuration - quitting As OMAP3 configs don't set CONFIG_NAND but CONFIG_NAND_CMD. the GPMC was not initialized for NAND at all. This patch now fixes this issue. Tested on TAO3530 board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Pekon Gupta <pekon@ti.com> Cc: Tom Rini <trini@ti.com> Acked-by: Pekon Gupta <pekon@ti.com>
| | * | am335x_evm / gumstix pepper: Correct DDR settingsTom Rini2014-07-25-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As noted by clang, we have been shifting certain values out of 32bit range when setting some DDR registers. Upon further inspection these had been touching reserved fields (and having no impact). These came in from historical bring-up code and can be discarded. Similarly, we had been declaring some fields as 0 when they will be initialized that way. Tested on Beaglebone White. Reported-by: Jeroen Hofstee <jeroen@myspectrum.nl> Cc: Ash Charles <ash@gumstix.com> Signed-off-by: Tom Rini <trini@ti.com> Tested-By: Ash Charles <ashcharles@gmail.com>
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