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* MLK-10812-3 imx:mx6ul PAD_CTL_SPEED_LOW for mx6ulPeng Fan2015-05-05-1/+1
| | | | | | PAD_CTL_SPEED_LOW for mx6ul same with mx6sx. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10812-2 imx:mx6ul add clock supportPeng Fan2015-05-05-61/+421
| | | | | | | | | | | | add i.MX6UL clock related settings/macros/apis When using TFT43AB, its pixel size is 480x272 which needs a slow pix clock. Without apply the test_div in PLL video, we can't get the pix clock in the rate. So change the LCDIF clock calculation to use the test_div. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10812-1 imx:mx6 add i2c4 supportPeng Fan2015-05-05-6/+23
| | | | | | I2C4 support for i.MX Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10808-5 imx: mx6ul: Update soc relevant settingsYe.Li2015-05-05-9/+25
| | | | | | | Remove PCIe, xPU power, PL310 L2 Cache for MX6UL. Update FEC MAC address, WDOG settings, USDHC clock rate. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10808-4 imx: Move system counter driver to imx-commonYe.Li2015-05-04-9/+18
| | | | | | | | | | | | | Since the system counter driver will also be used by mx6ul, move this timer driver to imx-common and rename it as syscounter.c For mx6ul and mx7, configurations are used for choose the GPT timer or system counter timer (default). GPT timer: CONFIG_GPT_TIMER System counter timer: CONFIG_SYSCOUNTER_TIMER Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10808-3 imx: mx6ul: Update imx registers head fileYe.Li2015-05-04-33/+114
| | | | | | Update imx registers base address for i.MX6UL Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10808-2 imx: mx6ul: Add pins IOMUX head fileYe.Li2015-05-04-0/+1068
| | | | | | | Add i.MX6UL pins IOMUX file which defines the IOMUX settings for choose. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10808-1 imx: mx6ul: Add i.MX6UL CPU typeYe.Li2015-05-04-2/+5
| | | | | | | | | Add MXC_CPU_MX6UL for i.MX6UL CPU type which is got at runtime. The 0x64 is defined as i.MX6Ul CPU type value in RM, but the value has been occupied by i.MX6D as a dummy CPU type. So we also need change i.MX6D to a invalid value 0x67. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10774-52 nand: mxs correct MXS_DMA_ALIGNMENTPeng Fan2015-04-29-1/+1
| | | | | | | | | | | | We should align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN, otherwise we may encounter errors, " NAND: ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 ERROR: v7_dcache_inval_range - stop address is not aligned - 0xbdf1f4a0 ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 " Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10708 imx:mx6qp Update Saturation THR for PRExPeng Fan2015-04-29-4/+4
| | | | | | | | Update settings for PRE. Value for Saturation THR of PREx, changed from 0x20 to 0x10 to make system more stable. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 02e7090604e55d9690532294b02b499609d46e63)
* MLK-10702 imx: mx7d: clock: correct fec MDC root clockFugang Duan2015-04-29-1/+1
| | | | | | | | In i.MX7d platform, fec MDC root clock is ENET_AXI_ROOT_CLK, not ipg clock, correct it. Signed-off-by: Fugang Duan <B38611@freescale.com> (cherry picked from commit 07105e18dd0899c47ef80d3fddecf3ef250d895a)
* MLK-10774-48 imx: mx7 update hab_caam_clock_enablePeng Fan2015-04-29-11/+8
| | | | | | | Merge hab_caam_clock_enable and hab_caam_clock_disable into one function Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* ENGR00329484-2 ARM:MX6: Clear Align bit in SCTLRPeng Fan2015-04-29-0/+3
| | | | | | | | | | | This problem is found when debugging QuadSPI. When "A" bit is enabled, unaligned access will cause data abort exception. Actually, we do not want this exception. So clear the align bit for MX6 SOCs. Tested this code with android team colleague and did not find problem. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit aa76a7e472e34bc59554f9932d611b1047d24590)
* MLK-10674-2 imx: mx6qp settings for PREPeng Fan2015-04-29-0/+38
| | | | | | | | | | | | | | | | | | | | | | Since the following piece settings can not be in DCD table, we add them in enable_ipu_clock. " setmem /32 0x00bb048c = 0x00000002 ## Bypass IPU1 QoS generator setmem /32 0x00bb050c = 0x00000002 ## Bypass IPU2 QoS generator setmem /32 0x00bb0690 = 0x00000200 ## Bandwidth THR for of PRE0 setmem /32 0x00bb0710 = 0x00000200 ## Bandwidth THR for of PRE1 setmem /32 0x00bb0790 = 0x00000200 ## Bandwidth THR for of PRE2 setmem /32 0x00bb0810 = 0x00000200 ## Bandwidth THR for of PRE3 setmem /32 0x00bb0694 = 0x00000020 ## Saturation THR for of PRE0 setmem /32 0x00bb0714 = 0x00000020 ## Saturation THR for of PRE1 setmem /32 0x00bb0794 = 0x00000020 ## Saturation THR for of PRE2 setmem /32 0x00bb0814 = 0x00000020 ## Saturation THR for of PRE " CONFIG_VIDEO_IPUV3 is always defined in mx6sabre_common.h, the settings sure will effect. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 61cec88a59ebf450dd1352d81e03b5aa842e1d71)
* MLK-10647 armv7: Fix Dcache disable issue on i.MX7Ye.Li2015-04-29-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The issue on the i.MX7D is that, there is one cache-able memory access between the L1 and L2 cache flush by calling the flush_dache_all-> v7_maint_dcache_all() [Flush L1 and L2 cache) which written in the C code. L1-cache-flush -> This will flush L1 cache to L2 cache in the end. Cache-able memory access -> This will have the chance cause the L1 line-fill with dirty data from L2 cache(L1 cache-line dirty, L2 clean) L2-cache-flush -> This will only flush L2 cache to L3, but still some dirty data on the L1 cacheline. After C & M bit clean, -> The dirty data on the L1 cache line lost, which will cause memory coherent issue if that dirty cache line has some useful data The only problem here is: there is one cache-cable memory access between L1 and L2 cache flush. This patch should works fine on the i.MX6 and i.MX7. The second cache flush have zero impact on the i.MX6, but this is really need for the i.MX7D platform due to the L1 line-fill during the first dcache_flush. And the second flush will not bring in the L1 dirty cache line due to the C bit is clear now, which means the dcache is disabled. Acked-by: Jason Liu<r64343@freescale.com> Reviewed-by: Jason Liu<r64343@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit f5d5f07fba936c4bb05c887de9d72fb75b3dc0f2) (cherry picked from commit 86c784cf4c4b633d37a76de7d47155c08f75dc82)
* MLK-10774-46 imx:mx6sx use correct GPR addressPeng Fan2015-04-29-1/+1
| | | | | | Use correct GPR address. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10774-45 imx:mx6sx add SION for i2c pin muxPeng Fan2015-04-29-20/+20
| | | | | | | | Add SION for i2c pin mux, otherwise will cause error. Found this problem on mx6sxsabreauto board. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10774-44 imx:mx6 fix is_soc_revPeng Fan2015-04-29-1/+1
| | | | | | | is_soc_rev should be casted to signed int, otherwise may incur errors when detecting cpu types. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10597: arm: imx7d: extend iomuxc-lpsr IO pads config optionsAdrian Alonso2015-04-29-4/+39
| | | | | | | | | * Extend IOMUXC-LPSR IO pads configuration options * Add alternative configuration modes for IO pads from IOMUXC-LPSR Signed-off-by: Adrian Alonso <aalonso@freescale.com> (cherry picked from commit ca20aa7ca0c21b9766e0c34cfec275aaab0f11e7)
* MLK-10569 imx7d: call set_epdc_qos unconditionallyRobby Cai2015-04-29-4/+1
| | | | | | | | | This EPDC/EPXP QoS setting is needed for EPDC stress test to pass. This patch remove the #ifdef to make sure set_epdc_qos be called always. Signed-off-by: Robby Cai <r63905@freescale.com> (cherry picked from commit d2fb113740b2c67958862503dda2a40191ab0899) (cherry picked from commit 581aa86581bb1178c5df4ad5298e5b85c53f1186)
* MLK-10590: arm :imx7d: correct iomuxc-lpsr daisy chainAdrian Alonso2015-04-29-3/+3
| | | | | | | | | | * Correct daisy chain settings for LPSR iomux controller * Add IOMUX_LPSR_SEL_INPUT_OFS only when pad is identified to be part of lpsr-iomuxc domain Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> (cherry picked from commit e4fd6550b3e5458aaf5049a7e6a12d6e4443c53a)
* MLK-10522-2: arm: imx7d: add iomuxc-lpsr i2c pad settingsAdrian Alonso2015-04-29-1/+4
| | | | | | | | | | | * Add IMX7D iomuxc-lpsr I2C1 and I2C2 pad configuration settings * Input select offset input_sel_ofs = 0x05xx + IOMUX_LPSR_SEL_INPUT_OFS allows to access register in iomuxc controller for imx_iomux_v3_setup_pad I2C daisy chaing configuration. Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit bca65c5ee1099f99b880be325c9fa0a568ab88de)
* MLK-10566: arm :imx7d: fix iomuxc-lpsr daisy chain settingsAdrian Alonso2015-04-29-0/+4
| | | | | | | | | | | | | | | * For IOMUXC LPSR pads when daisy chain register needs to be set the result offsets for sel_input register is incorrect as base address is 0x302C0000 and the passed offset does not resolve to the intended input sel pad register; input sel base offset should start in 0x30330000. * Add an addiotional fixed offset of 0x70000 to address the input sel offset: INPUT_SEL = 0x302C0000 + 0x70000 + sel_input_ofs. Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 5d4612613eb2e85f1929d8cf5cb6aac6ba9e5fd7)
* MLK-10524: iMX6x: Implement workaround for Cortex-A9 errata 845369Nitin Garg2015-04-29-0/+5
| | | | | | | | | | Under very rare timing circumstances, transitioning into streaming mode might create a data corruption. Present on Two or more processors or 1 core with ACP, all revisions. This erratum can be worked round by setting bit[22] of the undocumented Diagnostic Control Register to 1. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> (cherry picked from commit 70ad44e523680de67dd8b7a7505d7f27799980ee)
* MLK-10513 mx7: HAB: Fix HAB RVT addresses to unified sectionYe.Li2015-04-29-11/+5
| | | | | | | | Incorrect hab_rvt addresses were used for getting HAB functions. Need to change to addresses in unified section. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 5ae1cb9d8e7cd7babd1d7ef7f2303664a4e15c26)
* MLK-10503 imx:mx6qp add missed macroPeng Fan2015-04-29-1/+4
| | | | | | | is_mx6dqp should be only applied for MX6 Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit d860559f7913f16f7cb248f7b44140e8c1aa3ee9)
* MLK-10499 imx:mx6qp update printed cpu infoPeng Fan2015-04-29-5/+14
| | | | | | | We should print "MX6QP Rev1.0", but not "MX6Q Rev2.0". Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 64b2be69835af80e0dbc151175617942683a3167)
* MLK-10496: Check the PL310 version for applying errataNitin Garg2015-04-29-11/+15
| | | | | | | | | | | | Apply errata based on PL310 version instead of compile time. Also set Prefetch offset to 15, since it improves memcpy performance by 35%. Don't enable Incr double Linefill enable since it adversely affects memcpy performance by about 32MB/s and reads by 90MB/s. Tested with 4K to 16MB sized src and dst aligned buffer. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> (cherry picked from commit 31751fa9cf29ef4056f49fe06a54700a89c9bdc5)
* MLK-10492-1 imx: mx7d: Update LCDIF clock settingsYe.Li2015-04-29-7/+54
| | | | | | | | | To support lower clock frequency, needs to set post divider and test divider in PLL_VIDEO. So update LCDIF clock settings function to support this feature. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit b4d3b2a8eaf1ad1dc529ae2348d1646a2833b701)
* MLK-10477-2 imx: mx7d: Add EPDC clock init and base addressYe.Li2015-04-29-0/+34
| | | | | | | Ungate the EPDC clock at system up if the EPDC is enabled Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit f215632cb25d1076ab5c5465efdfad2212010d8d)
* MLK-10477-1 imx: mx7d: Add QoS settings for EPDCYe.Li2015-04-29-0/+34
| | | | | | | Add the QoS settings function which is used for EPDC Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 725a3bbbe0a172a0f4619d99bc198b9367b9fc5d)
* MLK-10448-5 imx: mx6qp: Enable PRG clock for IPUYe.Li2015-04-29-0/+6
| | | | | | | | | | The i.MX6QP has a PRG module, need to enable its clock for using IPU. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Brown Oliver <B37094@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 089f399ea07db79d6bca8fdc08b442b59eb55feb)
* MLK-10448-4 mx6: hab : Remove the cache issue workaroud in hab for i.MX6QPYe.Li2015-04-29-1/+2
| | | | | | | | | | | Since the i.MX6QP has fixed the issue in boot ROM, so remove the workaround for i.MX6QP. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 96e13b57ead3ed00c3a32c5373c7a2a876947f99) Conflicts: arch/arm/cpu/armv7/mx6/hab.c
* MLK-10448-3 mx6: ccm: Change the clock settings for i.MX6QPYe.Li2015-04-29-20/+54
| | | | | | | | | | | | | | | | Since i.MX6QP changes some CCM registers, so modify the clocks settings to follow the hardware changes. A new CONFIG_MX6QP is introduced here and is used for the CCM difference. At default CONFIG_MX6Q is enabled along with the CONFIG_MX6QP. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 5e4d1537ce9a476c8404126350f05d8976c5aa35) Conflicts: arch/arm/cpu/armv7/mx6/clock.c arch/arm/include/asm/arch-mx6/crm_regs.h include/configs/mx6_common.h
* MLK-10448-2 mx6: L2cache: Enable the double line fill for i.MX6DQPYe.Li2015-04-29-0/+3
| | | | | | | | Since i.MX6DQP has fixed the L2 cache issue, enable the double line fill feature to provide better performance. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit aa8a38edb67d4d1375d10bee9bf46557369fb5c4)
* MLK-10448-1 mx6: Add MX6DQP CPU rev typeYe.Li2015-04-29-2/+10
| | | | | | | | | Add new cpu type for i.MX6DQP and providing a dynamical detecting function. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit ccf3b130d71cf3dd9a97d3bb424931bf6bd7e8c0)
* MLK-10385-3 imx: mx7: Enable rawnand clock at init for APBH-DMAYe.Li2015-04-29-0/+4
| | | | | | | | For APBH-DMA enabled case, we have to enable rawnand clock for mxs_dma_init. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 42f42939bbd8161ce283a6af326d0f313cc4c36c) Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10385-2 imx: nand: Update GPMI NAND driver to support MX7DYe.Li2015-04-29-3/+3
| | | | | | | | Update GPMI NAND driver and BCH head file with definitions for CONFIG_MX7 Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 9c50677dac30085742ef216b9f2e19308e123d2b) Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10385-1 imx: apbh_dma: Update APBH-DMA for MX7DYe.Li2015-04-29-6/+6
| | | | | | | | Update APBH-DMA driver and head files with definitions for CONFIG_MX7 Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 07299056426f1f25aab51ab5531c4846d4c7560f) Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10363-1 udc: Update i.MX udc driver to support MX7Ye.Li2015-04-29-24/+2
| | | | | | | | | Update driver codes and registers define for MX7. Implement udc callback function in MX7 arch. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit e55c4f7bf5a66b34c2d01c42bac667cb3789b0c1) Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10774-33 imx:mx6 add udc and fastboot supportPeng Fan2015-04-29-1/+618
| | | | | | | | | | | | Add udc and fastboot support We did not use the upstream way. Currently use CI_UDC and USB_GAGDET of upstream can make fastboot work, but lack of flash operation, so we still use our way. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10774-30 imx:mx7 dm thermal driver supportPeng Fan2015-04-29-112/+22
| | | | | | Add thermal driver for mx7 Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10774-29 imx:thermal change from CONFIG_IMX6_THERMAL to CONFIG_IMX_THERMALPeng Fan2015-04-29-1/+1
| | | | | | Change macro name to make driver support more platforms. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10774-26 arm:armv7 add imx7Peng Fan2015-04-29-0/+1
| | | | | | Modify Makefile to support MX7 Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10215 Add elan init in i.MX6SL-EVK boardHaibo Chen2015-04-29-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | EPDC board contain a elan touch screen, this screen is a i2c slave. If this EPDC board connect to i.MX6SL-EVK board, after uboot boot up, if we do i2c operation, like i2c probe, then the i2c bus block. This is due to the elan touch screen i2c slave. This device needs to do some initialization opearation before its i2c operation, otherwise this i2c device pull down the i2c clk line, and make the i2c bus hang. This means elan needs a special flow on i2c before its address is acked, otherwise the i2c bus will be hang. This patch is a workaround, it add a void function which is defined as a weak symbol in i2c driver, and it is called before every i2c operation. In mx6slevk, this function was overwrite to execute elan initialization. So that, for mx6slevk board, it will initialize elan before every i2c operation, but for other boards, it just work as before. Signed-off-by: Haibo Chen <haibo.chen@freescale.com> (cherry picked from commit 4c587b29c423ce61b2471ed20f31ff533d9d8a39) Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Conflicts: arch/arm/include/asm/arch-mx6/mx6sl_pins.h board/freescale/mx6slevk/mx6slevk.c
* MLK-10363-2 imx: mx7: Enable SNVS clockYe.Li2015-04-29-0/+2
| | | | | | | | Enable SNVS clock in clock_init function as default enabled clock. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit df1e45b3098f737d68517c51032472d12fd87666) Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10362 imx: mx7dsabresd: Add support for MX7D SABRESD boardPeng Fan2015-04-29-0/+5
| | | | | | | | | | | | | | | Add i.MX7D SABRESD board BSP codes, with enabled modules: UART, PMIC, USB/OTG, SD, eMMC, ENET, I2C, 74LV IOX. Build target: mx7dsabresd_config Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 3bf52a153e2964d4fdc17f0e8cb816686cbb6c2b) Conflicts: boards.cfg
* MLK-10361 imx: mx7d arm2: Change to use WDOG_B resetYe.Li2015-04-29-3/+22
| | | | | | | | | | | | | | | | | | | | | The default u-boot reset is a internal WDOG reset (warm reset on i.MX6) which does not have power and DDR reset. So the peripherals and DDR may meet problem. When using the internal WDOG reset on i.MX7D ARM2 boards, we meets two DDR issues: 1. On 12x12 ARM2, sometimes the system may hang in DCD because the DDRC Operating Mode does not become to normal. 2. On 19x19 ARM2, the reset always brings system to USB download because the DDR3 turns to unstable. On the i.MX7D ARM2 board, the WDOG_B signal connects to POR_B or PMIC_PWRON. This gives a chance to use a stronger reset. So in this patch, we set the IOMUX for WDOG_B pin and enable WDOG_B signal output in WDOG WCR register. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 1192501c1fcf3b266eb22639a6bc93ac7c03b367) Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10351 imx: mx7d: Add 19x19 DDR3L ARM2 board supportYe.Li2015-04-29-0/+5
| | | | | | | | | | | | | | | Add BSP codes, configuration head file and build target for 19x19 DDR3L ARM2 board with basic functions: ENET2, I2C, SD/eMMC/MMC, USB, QSPI, ECSPI, pfuze3000 PMIC. Build target: mx7d_19x19_ddr3_arm2_config Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 58fd869e3097b7461fbfae3d94e3ebbd30ae2474) Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Conflicts: boards.cfg
* MLK-10200 imx: mx7: Add M4 booting supportYe.Li2015-04-29-2/+18
| | | | | | | | Implement the auxiliary core booting for Cortex M4 on i.MX7 Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit c1c8ba37d87493c16ec1a12bc36d47f909e0e733) Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
generated by cgit v1.1 at 2024-12-22 04:53:43 +0000