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* driver/ddr: Restruct driver to allow standalone memory spaceYork Sun2014-09-25-2/+2
| | | | | | | | | | U-boot has been initializing DDR for the main memory. The presumption is the memory stays as a big continuous block, either linear or interleaved. This change is to support putting some DDR controllers to separated space without counting into main memory. The standalone memory controller could use different number of DIMM slots. Signed-off-by: York Sun <yorksun@freescale.com>
* Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2014-09-21-0/+78
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| * ARM: keystone: ddr3: workaround for ddr3a/3b memory issueMurali Karicheri2014-09-17-0/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements a workaround to fix DDR3 memory issue. The code for workaround detects PGSR0 errors and then preps for and executes a software-controlled hard reset.In board_early_init, where logic has been added to identify whether or not the previous reset was a PORz. PLL initialization is skipped in the case of a software-controlled hard reset. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Keegan Garcia <kgarcia@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* | ARM: atmel: add pcr related definitionBo Shen2014-09-19-1/+2
| | | | | | | | | | | | | | | | Using CPU_HAS_PCR micro to present the SoC has pcr (peripheral control register). Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | ARM: atmel: use pcr to enable or disable peripheral clockBo Shen2014-09-19-4/+25
| | | | | | | | | | | | | | | | When use pcr (peripheral control register), then we won't need to care about the peripheral ID. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | ARM: atmel: sama5d3: add timings registerBo Shen2014-09-19-1/+2
| | | | | | | | | | | | Signed-off-by: Bo Shen <voice.shen@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-09-17-165/+313
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| * Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-09-17-165/+313
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| | * imx: Fix build of mx6sxsabresdStefano Babic2014-09-11-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 224beb833e544b802f08765271cec07667d39669 add clock enabling function for FEC, but the masks are not available for SX processor and the mx6sxsabresd cannot be built clean. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Nikita Kiryanov <nikita@compulab.co.il>
| | * pcie_imx: Add mx6solox supportFabio Estevam2014-09-09-4/+22
| | | | | | | | | | | | | | | | | | | | | Let PCI on mx6solox also be supported. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
| | * mx6: imx-regs: Provide a structure for GPC registersFabio Estevam2014-09-09-0/+13
| | | | | | | | | | | | | | | | | | | | | Introduce a structure for accessing the General Power Controller block (GPC) registers. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * mx6qsabreauto: Remove imx6q-sabreauto.dtsFabio Estevam2014-09-09-14/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit fa9c021632473 ("mx6: add example DTB for mx6qsabreauto") introduced 'imx6q-sabreauto.dts' but it adds no real value as the dts file only contains the 'model' and 'compatible' strings. After this commit the final binary is also changed from 'u-boot.imx' to 'u-boot-dtb.imx', which may confuse users. So revert it until a more complete and useful device tree could be provided. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
| | * mx6: Fix ECSPI typo in soc_boot_modesNikolay Dimitrov2014-09-09-4/+4
| | | | | | | | | | | | | | | | | | Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
| | * iMX6: Disable the L2 before chaning the PL310 latencyYe.Li2014-09-09-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Latency parameters of PL310 Tag RAM latency control register and Data RAM Latency control register are set in L2 cache enable. And setting these registers must have PL310 NOT enabled. But when using Plugin mode boot, the PL310 is enabled by bootrom. The patch disables the PL310 before applying this setting. Signed-off-by: Ye.Li <Ye.Li@freescale.com>
| | * arm: mx6: add support for Compulab cm-fx6 CoMNikita Kiryanov2014-09-09-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial support for Compulab CM-FX6 CoM. Support includes MMC, SPI flash, and SPL with dynamic DRAM detection. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| | * arm: mx6: add get_cpu_type()Nikita Kiryanov2014-09-09-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | Define get_cpu_type(). Reuse it in is_cpu_type(). Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| | * arm: mx6: ddr: fix cs0_end calculationNikita Kiryanov2014-09-09-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current way of calculation CS0_END field for MMDCx_MDASP register is problematic because in most cases the user is forced to define cs_density in an unnatural way: as value - 2, instead of value. This breaks the abstraction provided by struct mx6_ddr_sysinfo because the user is forced to be aware of the way the calculation is performed. Refactor the calculation. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| | * arm: mx6: ddr: configure MMDC for slow_pdNikita Kiryanov2014-09-09-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to MX6 TRM, both MMDC and DRAM should be configured to the same powerdown precharge. Currently, mx6_dram_cfg() configures MMDC for fast pd (MDPDC[7] = 0), and the DRAM for 'slow exit (DLL off)' (MR0[12] = 0). Configure MMDC for slow pd. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Tim Harvey <tharvey@gateworks.com>
| | * arm: mx6: ddr: do not write into reserved bitNikita Kiryanov2014-09-09-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Bit 16 in mapsr register is in a reserved field. Don't write to it. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Acked-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| | * arm: mx6: ddr: cleanupNikita Kiryanov2014-09-09-141/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | | No functional changes. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Acked-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| | * i2c: imx: add macros to setup pads for multiple SoC typesNikita Kiryanov2014-09-09-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add macro which defines i2c_pads_info structs for multiple SoC types, and a macro which selects the appropriate struct based on CPU type, thus eliminating the need to manage multiple i2c pad configurations manually when supporting multiple SoC types. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Acked-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| | * mx6: add clock enabling functionsNikita Kiryanov2014-09-09-0/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add functions to enable/disable clocks for UART, SPI, ENET, and MMC. Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* | | Revert "ARM: SPL: do not set gd again"Tom Rini2014-09-16-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the high level, the problem is that we set gd multiple times (and still do, even after the commit we're reverting). We set important parts of gd to the copy which is not above stack but rather in the data section. For the release, we're going to revert this change and for the next release we shall correct things to only, really, set gd once to an appropriate location and ensure that comments about it are correct too. This reverts commit f0c3a6c4ad09210d5d4aeafe87685ee75e5683d6. Acked-by: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Tom Rini <trini@ti.com>
* | | kconfig: armv8: move CONFIG_ARM64 to KconfigMasahiro Yamada2014-09-16-0/+14
| | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | vexpress64: kconfig: consolidate CONFIG_TARGET_VEXPRESS_AEMV8A_SEMIMasahiro Yamada2014-09-16-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | We do not have to distinguish CONFIG_TARGET_VEXPRESS_AEMV8A_SEMI from CONFIG_TARGET_VEXPRESS_AEMV8A. Rename the former to the latter. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Steve Rae <srae@broadcom.com> Cc: David Feng <fenghua@phytium.com.cn>
* | | kconfig: remove redundant "string" type in arch and board KconfigsMasahiro Yamada2014-09-13-67/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now the types of CONFIG_SYS_{ARCH, CPU, SOC, VENDOR, BOARD, CONFIG_NAME} are specified in arch/Kconfig. We can delete the ones in arch and board Kconfig files. This commit can be easily reproduced by the following command: find . -name Kconfig -a ! -path ./arch/Kconfig | xargs sed -i -e ' /config[[:space:]]SYS_\(ARCH\|CPU\|SOC\|\VENDOR\|BOARD\|CONFIG_NAME\)/ { N s/\n[[:space:]]*string// } ' Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | kconfig: add CONFIG_SYS_{ARCH, CPU, ...} type def to arch/KconfigMasahiro Yamada2014-09-13-0/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds the type definitions (+ help messages) of CONFIG_SYS_{ARCH, CPU, SOC, VENDOR, BOARD, CONFIG_NAME} to arch/Kconfig, which would save lots of type defs for taget boards. (See also the next commit.) Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-dmTom Rini2014-09-13-16/+309
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| * | | tegra: dts: Add serial port detailsSimon Glass2014-09-10-10/+290
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some Tegra device tree files do not include information about the serial ports. Add this and also add information about the input clock speed. The console alias needs to be set up to indicate which port is used for the console. Also add a binding file since this is missing. Series-changes; 5 - Add full serial port nodes from Linux tree (commit fc9d4dbe) - Use /chosen/stdout-path instead of /aliases/console to specify the console Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | sandbox: dts: Add a serial console nodeSimon Glass2014-09-10-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the sandbox device tree is provided to U-Boot (with the -d flag) then it will use the device tree version in preference to the built-in device. The only difference is the colour. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | tegra: Convert tegra GPIO driver to use driver modelSimon Glass2014-09-10-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is an implementation of GPIOs for Tegra that uses driver model. It has been tested on trimslice and also using the new iotrace feature. The implementation uses a top-level GPIO device (which has no actual GPIOS). Under this all the banks are created as separate GPIO devices. The GPIOs are named as per the Tegra datasheet/header files: A0..A7, B0..B7, ..., Z0..Z7, AA0..AA7, etc. Since driver model is not yet available before relocation, or in SPL, a special function is provided for seaboard's SPL code. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-09-12-70/+417
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| * | arm: Fix _start for CONFIG_SYS_DV_NOR_BOOT_CFGBenoît Thébaudeau2014-09-11-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The boards using CONFIG_SYS_DV_NOR_BOOT_CFG (i.e. calimain, da850evm_direct_nor and enbw_cmc) had the _start symbol defined after the CONFIG_SYS_DV_NOR_BOOT_CFG word rather than before it in arch/arm/lib/vectors.S. Because of that, if by lack of luck 'gd->mon_len = (ulong)&__bss_end - (ulong)_start' (see setup_mon_len()) was a multiple of 4 kiB (see reserve_uboot()), then the last BSS word overlapped the first word of the following reserved RAM area (or went beyond the top of RAM without such an area) after relocation because __image_copy_start did not match _start (see relocate_code()). This was broken by commit 41623c9 'arm: move exception handling out of start.S files', which defined _start twice (before and after the CONFIG_SYS_DV_NOR_BOOT_CFG word), then by commit 0a26e1d 'arm: fix a double-definition error of _start symbol', which kept the definition of the _start symbol after the CONFIG_SYS_DV_NOR_BOOT_CFG word. This new commit fixes this issue by restoring the original behavior, i.e. by defining the _start symbol before the CONFIG_SYS_DV_NOR_BOOT_CFG word. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Manfred Rudigier <manfred.rudigier@omicron.at> Cc: Christian Riesch <christian.riesch@omicron.at> Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Cc: Heiko Schocher <hs@denx.de>
| * | arm: Make reset position-independentBenoît Thébaudeau2014-09-11-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some boards, like mx31pdk and tx25, require the beginning of the SPL code to be position-independent. For these two boards, this is because they use the i.MX external NAND boot, which starts by executing the first NAND Flash page from the NFC page buffer. The SPL then needs to copy itself to its actual link address in order to free the NFC page buffer and use it to load the non-SPL image from Flash before running it. This means that the SPL runtime address differs from its link address between the reset and the initial copy performed by board_init_f(), so this part of the SPL binary must be position-independent. This requirement was broken by commit 41623c9 'arm: move exception handling out of start.S files', which used an absolute address to branch to the reset routine. This new commit restores the original behavior, which just performed a relative branch. This fixes the boot of mx31pdk and tx25. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com> Reported-by: Helmut Raiger <helmut.raiger@hale.at> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Magnus Lilja <lilja.magnus@gmail.com> Cc: John Rigby <jcrigby@gmail.com> Tested-by: Magnus Lilja <lilja.magnus@gmail.com>
| * | eabi_compat: add __aeabi_memcpy __aeabi_memsetJeroen Hofstee2014-09-09-2/+13
| | | | | | | | | | | | | | | cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
| * | ARM: make gd a function for clangJeroen Hofstee2014-09-09-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "clang does not support global register variables; this is unlikely to be implemented soon because it requires additional LLVM backend support" [1] Workaround it by obtaining the value of gd/r9 by an inline asm routine. Note there is no set routine added for ARM at the moment, since most if not all updates of gd from c are actually not needed for ARM. [1] http://clang.llvm.org/docs/UsersManual.html cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
| * | ARM: SPL: do not set gd againJeroen Hofstee2014-09-09-3/+0
| |/ | | | | | | | | | | | | | | | | Just before calling board_init_f, crt0.S has already reserved space for the initial gd on the stack. There should be no need to allocate it again. cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
| * Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2014-09-09-28/+258
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| | * ARM: exynos: peach_pit: Add DT nodes for fimd and parade bridge chipAjay Kumar2014-09-05-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds DT properties for fimd and the parade bridge chip present on peach_pit. The panel supports 1366x768 resolution. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * exynos5420: add callbacks needed for exynos_fb driverAjay Kumar2014-09-05-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initialization code for peach_pit panel, parade bridge chip, and backlight. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * ARM: exynos: Add missing declaration for gpio_direction_inputAjay Kumar2014-09-05-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds missing declaration for gpio_direction_input function, thereby helps in resolving compilation warnings. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * video: exynos_fimd: Add framework to disable FIMD sysmmuAjay Kumar2014-09-05-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Exynos5420 and newer versions, the FIMD sysmmus are in "on state" by default. We have to disable them in order to make FIMD DMA work. This patch adds the required framework to exynos_fimd driver, and disables FIMD sysmmu on Exynos5420. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420Ajay Kumar2014-09-05-6/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by exynos video driver. Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * arm: exynos: Add RPLL for Exynos5420Ajay Kumar2014-09-05-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | RPLL is needed to drive the LCD panel on Exynos5420 based boards. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * exynos_fb: Remove usage of static definesAjay Kumar2014-09-05-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, we used to statically assign values for vl_col, vl_row and vl_bpix using #defines like LCD_XRES, LCD_YRES and LCD_COLOR16. Introducing the function exynos_lcd_early_init() would take care of this assignment on the fly by parsing FIMD DT properties, thereby allowing us to remove LCD_XRES and LCD_YRES from the main config file. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * odroid: kconfig: add odroid_defconfigPrzemyslaw Marczak2014-09-05-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This config is valid for two devices: - Odroid X2, - Odroid U3. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Tom Rini <trini@ti.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * odroid: add odroid U3/X2 device tree descriptionPrzemyslaw Marczak2014-09-05-1/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is a standard description for Odroid boards. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Tom Rini <trini@ti.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * arm:reset: call the reset_misc() before the cpu resetPrzemyslaw Marczak2014-09-05-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On an Odroid U3 board, the SOC is unable to reset the eMMC card in the DWMMC mode by the cpu software reset. Manual reset of the card by switching proper gpio pin - fixes this issue. Such solution needs to add a call to pre reset function. This is done by the reset_misc() function, which is called before reset_cpu(). The function reset_misc() is a weak function. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Changes v4: - arch/arm/reset: fix weak function attribute to proper style Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * arch:exynos: boot mode: add get_boot_mode(), code cleanupPrzemyslaw Marczak2014-09-05-19/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces code clean-up for exynos boot mode check. It includes: - removal of typedef: boot_mode - move the boot mode enum to arch-exynos/power.h - add bootmode for sequence: eMMC 4.4 ch4 / SD ch2 - add new function: get_boot_mode() for OM[5:1] pin check - update spl boot code Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Changes v5: - exynos: boot mode: add missing bootmode (1st:EMMC 4.4 / 2nd:SD ch2) Changes v6: - none changes v7: - change boot mode name: BOOT_MODE_MMC to BOOT_MODE_SD Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * exynos: pinmux: fix the gpio names for exynos4x12 mmcPrzemyslaw Marczak2014-09-05-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change fixes the bad gpio configuration for the exynos dwmmc. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Beomho Seo <beomho.seo@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
generated by cgit v1.1 at 2024-11-28 17:37:11 +0000