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* sh: Do not include start.o in lib$(CPU).oMasahiro Yamada2013-10-31-3/+9
| | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* sparc: fix a link errorMasahiro Yamada2013-10-31-0/+2
| | | | | | | | | | | Before this commit, arch/sparc/lib/Makefile used both COBJS and COBJS-y. And it missed to add COBJS-y into OBJS. This means bootm.o was never compiled even if CONFIG_CMD_BOOTM=y Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Daniel Hellstrom <daniel@gaisler.com>
* ARM: s5pc, exynos: move Samsung ARM SoC specific code under arch/arm/Masahiro Yamada2013-10-31-0/+4
| | | | | | | | | This patch moves S5PC, EXYNOS specific directory entries from the toplevel Makefile to arch/arm/cpu/armv7/Makefile using Kbuild descending feature. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Minkyu Kang <mk7.kang@samsung.com>
* ARM: omap: move OMAP specific code under arch/arm/Masahiro Yamada2013-10-31-0/+3
| | | | | | | | | This patch moves OMAP specific directory entries from the toplevel Makefile and spl/Makefile to arch/arm/cpu/armv7/Makefile using Kbuild descending feature. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com>
* ARM: tegra: move Tegra specific code under arch/arm/Masahiro Yamada2013-10-31-0/+6
| | | | | | | | | This patch moves Tegra specific directory entries from the toplevel Makefile and spl/Makefile to arch/arm/cpu/*/Makefile using Kbuild descending feature. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Warren <TWarren@nvidia.com>
* powerpc: convert makefiles to Kbuild styleMasahiro Yamada2013-10-31-580/+267
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Note: arch/powerpc/cpu/mpc8260/Makefile is originally like follows: ---<snip>--- START = start.o kgdb.o COBJS = traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \ ---<snip>--- COBJS-$(CONFIG_ETHER_ON_SCC) = ether_scc.o ---<snip>--- $(LIB): $(OBJS) $(call cmd_link_o_target, $(OBJS) $(obj)kgdb.o) The link rule `$(call cmd_link_o_target, $(OBJS) $(obj)kgdb.o)' is weird. kbdg.o is not included in $(OBJS) but linked into $(LIB) and $(LIB) is not dependent on kgdb.o. (Broken dependency tracking) So, START = start.o kgdb.o shoud have been START = start.o SOBJS = kgdb.o That is why this commit adds kgdb.o to obj-y, not to extra-y. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de>
* sandbox: convert makefiles to Kbuild styleMasahiro Yamada2013-10-31-46/+2
| | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* ARM: imx-common: convert makefiles to Kbuild styleMasahiro Yamada2013-10-31-29/+6
| | | | | | | | Multiple targets are included in arch/arm/imx-common/Makefile In order to refactor it, we need to tweak Makefile and spl/Makefile. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: convert makefiles to Kbuild styleMasahiro Yamada2013-10-31-429/+65
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* arm720t: convert makefiles to Kbuild styleMasahiro Yamada2013-10-31-114/+8
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* arm920t: convert makefiles to Kbuild styleMasahiro Yamada2013-10-31-170/+22
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* arm926ejs: convert makefiles to Kbuild styleMasahiro Yamada2013-10-31-407/+67
| | | | | | | | | | | | | | | | | Note1: In arch/arm/cpu/arm926ejs/spear/Makefile START := start.o was changed extra-$(CONFIG_SPL_BUILD) := start.o because spear/start.o is only used for SPL. Note2: START := start.o was missing from arch/arm/cpu/arm926ejs/mxs/Makefile. This commit simply adds extra-$(CONFIG_SPL_BUILD) := start.o Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* armv7: convert makefiles to Kbuild styleMasahiro Yamada2013-10-31-581/+103
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* DWMMC: SMDK5420: Disable SMU for eMMCRajeshwari Shinde2013-10-31-0/+13
| | | | | | | | | | | | SMDK5420 has a new Security Management Unit added for dwmmc driver, hence, configuring the control registers to support booting via eMMC. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* fsl/mpc85xx: define common serdes_clock_to_string functionValentin Longchamp2013-10-24-0/+39
| | | | | | | | | | | | This allows to share some common code for the boards that use a corenet base SoC. Two different versions of the function are available in fsl_corenet_serdes.c and fsl_corenet2_serdes.c files. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> [York Sun: fix t1040qds.c] Acked-by: York Sun <yorksun@freescale.com>
* mpc8xxx: set x2 DDR3 refresh rate if SPD config requires itValentin Longchamp2013-10-24-1/+17
| | | | | | | | | | | | | | | If the DDR3 module supports industrial temperature range and requires the x2 refresh rate for that temp range, the refresh period must be 3.9us instead of 7.8 us. This was successfuly tested on kmp204x board with some MT41K128M16 DDR3 RAM chips (no module used, chips directly soldered on board with an SPD EEPROM). Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> [York Sun: fix minor conflicts in fsl_ddr_dimm_params.h, lc_common_dimm_params.c, common_timing_params.h] Acked-by: York Sun <yorksun@freescale.com>
* mpc8xxx: call i2c_set_bus_num in __get_spdValentin Longchamp2013-10-24-1/+5
| | | | | | This is necessary with the new I2C subystem that was introduced lately. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
* powerpc: cast bi_memsize to ulong for %ld usageValentin Longchamp2013-10-24-1/+1
| | | | | | | | | | When exporting the new memsize without reserved PRAM area, the -Wformat option produces a warning since %ld is used for snprintf and bi_memsize is phys_size_t. This patch removes this warning for all PRAM PowerPC boards. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
* powerpc/usb:Differentiate USB controller base addressramneek mehresh2013-10-24-14/+21
| | | | | | | | Introduce different macros for storing addresses of multiple USB controllers. This is required for successful initialization and usage of multiple USB controllers inside u-boot Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
* powerpc/usb:Define CONFIG_USB_MAX_CONTROLLER_COUNT for all 85xx socsramneek mehresh2013-10-24-3/+29
| | | | | | | | CONFIG_USB_MAX_CONTROLLER_COUNT macro recently defined for initializing all USB controllers on a given platform. This macro is defined for all 85xx socs Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2013-10-22-10/+9
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| * sh: cache: Change cache API to defines as U-BootNobuhiro Iwamatsu2013-10-17-6/+3
| | | | | | | | | | | | | | | | | | A chache API of SH is developped by reference in linux kernel. And API was the same as the linux kernel. This patch change cache API to defines as U-Boot. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: timer: Remove static global variableNobuhiro Iwamatsu2013-10-17-4/+4
| | | | | | | | | | | | | | | | "static u16 bit" is not necessary to use this as static global variable. This patch fixes this. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: timer: Mask bit of timer prescalerNobuhiro Iwamatsu2013-10-17-1/+3
| | | | | | | | | | | | | | | | | | timer_init function sets timer prescaler bit. The previous code so did not mask this bit, this function was to overwrite the bit. This will fix this problem. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2013-10-21-10/+184
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| * | usb: add enum usb_init_type parameter to usb_lowlevel_initTroy Kisky2013-10-20-4/+4
| | | | | | | | | | | | | | | | | | This parameter will later be used to verify OTG ports. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * | usb: am437x: Add support for am437x xhci USB hostDan Murphy2013-10-20-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add the support for the am437x xhci usb host. The xHCI host on AM437 is connected to a usb2 phy so need to add support to enable those clocks. Signed-off-by: Dan Murphy <dmurphy@ti.com>
| * | usb: dra7xx: Add support for dra7xx xhci USB hostDan Murphy2013-10-20-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the support for the dra7xx xhci usb host. dra7xx does not contain an EHCI controller so the headers can be removed from the board file. The xHCI host on dra7xx is connected to a usb2 phy so need to add support to enable those clocks. Signed-off-by: Dan Murphy <dmurphy@ti.com>
| * | usb: omap: Move the xhci-omap header file to common locationDan Murphy2013-10-20-124/+0
| | | | | | | | | | | | | | | | | | | | | Moving the xhci-omap header to a more global location so that other code can reference this code. Signed-off-by: Dan Murphy <dmurphy@ti.com>
| * | usb: new board-specific USB init interfaceMateusz Zalega2013-10-20-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit unifies board-specific USB initialization implementations under one symbol (usb_board_init), declaration of which is available in usb.h. New API allows selective initialization of USB controllers whenever needed. Signed-off-by: Mateusz Zalega <m.zalega@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Lukasz Majewski <l.majewski@samsung.com>
| * | mx6: iomux: add GPR1 defines for use with nitrogen6xTroy Kisky2013-10-20-0/+6
| | | | | | | | | | | | | | | | | | Select GPIO1 as the USB OTG ID pin for Nitrogen6x Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * | OMAP5: USB: Add OMAP xHCI file and headerDan Murphy2013-10-20-0/+124
| | | | | | | | | | | | | | | | | | | | | | | | Add the OMAP file for the xHCI Host controller This code will initilialize the proper components within the OMAP5 to enable the xHCI host controller. Signed-off-by: Dan Murphy <dmurphy@ti.com>
| * | ARM: OMAP5: Add registers and defines for USBOTG SSDan Murphy2013-10-20-2/+20
| | | | | | | | | | | | | | | | | | | | | Add the prcm registers and the bit definitions to enable the USB SS port of the OMAP5 device. Signed-off-by: Dan Murphy <dmurphy@ti.com>
| * | exynos5: dts: Add device node for XHCIVivek Gautam2013-10-20-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding device node for xhci host controller to enable usb 3.0 on exynos5250. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Cc: Julius Werner <jwerner@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Dan Murphy <dmurphy@ti.com> Cc: Marek Vasut <marex@denx.de>
| * | arm: exynos: Add methods to control power to USB 3.0 PHYVivek Gautam2013-10-20-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding methods to turn on/off power to USB3.0 type PHY as and when required by the controller. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Cc: Julius Werner <jwerner@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Dan Murphy <dmurphy@ti.com> Cc: Marek Vasut <marex@denx.de>
| * | USB: XHCI: Add xHCI host controller support for Exynos5Vivek Gautam2013-10-20-0/+96
| |/ | | | | | | | | | | | | | | | | | | | | | | | | This adds driver layer for xHCI controller in Samsung's exynos5 soc. This interacts with xHCI host controller stack. Signed-off-by: Vikas C Sajjan <vikas.sajjan@samsung.com> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Cc: Julius Werner <jwerner@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Dan Murphy <dmurphy@ti.com> Cc: Marek Vasut <marex@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2013-10-17-3/+3
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| * | i2c: mxc: move to new subsystemtrem2013-10-17-3/+3
| |/ | | | | | | Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
* | PCIe:change the method to get the address of a requested capability in ↵Zhao Qiang2013-10-16-18/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com>
* | powerpc/mpc85xx: Add workaround for erratum A006379York Sun2013-10-16-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default value after POR. The workaround is to set this field before enabling CPC to 0x1e. Erratum A006379 applies to T4240 rev 1.0 B4860 rev 1.0, 2.0 Signed-off-by: York Sun <yorksun@freescale.com>
* | powerpc: Fix CamelCase warnings in DDR related codePriyanka Jain2013-10-16-464/+464
| | | | | | | | | | | | | | | | | | | | | | Some DDR related structures present in fsl_ddr_dimm_params.h, fsl_ddr_sdram.h, ddr_spd.h has various parameters with embedded acronyms capitalized that trigger the CamelCase warning in checkpatch.pl Convert those variable names to smallcase naming convention and modify all files which are using these structures with modified structures. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
* | powerpc/mpc85xx:Avoid fix clk groups for Cluster & HW acceleratorPrabhakar Kushwaha2013-10-16-60/+89
| | | | | | | | | | | | | | | | | | | | | | CHASSIS2 architecture never fix clock groups for Cluster and hardware accelerator like PME, FMA. These are SoC defined. SoC defines :- - NUM of PLLs present in the system - Clusters and their Clock group - hardware accelerator and their clock group if no clock group, then platform clock divider for FMAN, PME Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* | powerpc/mpc85xx:Update processor defines for T1040Prabhakar Kushwaha2013-10-16-8/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1040 SoC has - DDR controller ver 5.0 - 2 PLLs - 8 IFC Chip select - FMAN Muram 192K - No Srio - Sec controller ver 5.0 - Max CPU update for its personalities So, update the defines accordingly. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* | powerpc/mpc85xx:Make L2 cache type independent of CHASSIS2Prabhakar Kushwaha2013-10-16-5/+5
| | | | | | | | | | | | | | | | | | | | CHASSIS2 architecture never defines type of L2 cache present in SoC. it is dependent upon the core present in the SoC. for example, - e6500 core has L2 cluster (Kibo) - e5500 core has Backside L2 Cache Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* | powerpc: add CONFIG_SECURE_BOOT condition into fsl_secure_boot.hPo Liu2013-10-16-0/+2
|/ | | | | | | This patch is for board config file not to add CONFIG_SECURE_BOOT condition for include the asm/fsl_secure_boot.h. Signed-off-by: Po Liu <Po.Liu@freescale.com>
* microblaze: Fix watchdog initializationMichal Simek2013-10-16-4/+3
| | | | | | | | | | | The patch: "blackfin: Move blackfin watchdog driver out of the blackfin arch folder." (sha1: e9a389a18477c1c57a0b30e9ea8f4d38c6e26e63) changed hw_watchdog_init() prototype which didn't match with Microblaze one. This patch fixes the driver and Microblaze initialization. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Coding Style cleanup: drop some excessive empty linesWolfgang Denk2013-10-14-2/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Coding Style cleanup: remove trailing empty linesWolfgang Denk2013-10-14-5/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Coding Style cleanup: replace leading SPACEs by TABsWolfgang Denk2013-10-14-42/+42
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Drop changes for PEP 4 following python tools] Signed-off-by: Tom Rini <trini@ti.com>
* Coding Style cleanup: remove trailing white spaceWolfgang Denk2013-10-14-88/+88
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
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