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* MPC512x: workaround data corruption for unaligned local bus accessesWolfgang Denk2010-06-29-9/+12
| | | | | | | | | | | Commit 460c2ce3 "MPC5200: workaround data corruption for unaligned local bus accesses" fixed the problem for MPC5200 only, but MPC512x is affected as well, so apply the same fix here, too. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Acked-by: Detlev Zundel <dzu@denx.de>
* Prepare v2010.06-rc3v2010.06-rc3Wolfgang Denk2010-06-23-70/+70
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* MPC5200: workaround data corruption for unaligned local bus accessesWolfgang Denk2010-06-23-0/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MPC5200 has a nasty problem that will cause silent data corruption when performing unaligned 16 or 32 byte accesses when reading from the local bus - typically this affects reading from flash. The problem can be easily shown: => md fc0c0000 10 fc0c0000: 323e4337 01626f6f 74636d64 3d72756e 2>C7.bootcmd=run fc0c0010: 206e6574 5f6e6673 00626f6f 7464656c net_nfs.bootdel fc0c0020: 61793d35 00626175 64726174 653d3131 ay=5.baudrate=11 fc0c0030: 35323030 00707265 626f6f74 3d656368 5200.preboot=ech => md fc0c0001 10 fc0c0001: 65636801 00000074 0000003d 00000020 ech....t...=... fc0c0011: 0000005f 00000000 00000074 00000061 ..._.......t...a fc0c0021: 00000000 00000064 00000065 00000035 .......d...e...5 fc0c0031: 00000000 00000062 0000003d 0000006f .......b...=...o => md.w fc0c0001 10 fc0c0001: 0000 3701 0000 6f74 0000 643d 0000 6e20 ..7...ot..d=..n fc0c0011: 0000 745f 0000 7300 0000 6f74 0000 6c61 ..t_..s...ot..la This commit implements a workaround at least for the most blatant problem: using memcpy() from NOR flash. We rename the assembler routine into __memcpy() and provide a wrapper, which will use a byte-wise copy loop for unaligned source or target addresses when reading from NOR flash, and branch to the optimized __memcpy() in all other cases, thus minimizing the performance impact. Tested on lite5200b and TQM5200S. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
* ARM: remove unused VIDEOLFB ATAGMinkyu Kang2010-06-23-40/+3
| | | | | | | | | | | | | ATAG_VIDEOLFB is not used anywhere. The belowing warning is occurred due to this ATAG. [ 0.000000] Ignoring unrecognised tag 0x54410008 This patch fixed it. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Martin Krause <Martin.Krause@tqs.de>
* Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2010-06-22-4/+4
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| * Fix wrong orion5x MPP and GIPO writel argumentsAlbert Aribaud2010-06-22-4/+4
| | | | | | | | | | | | | | Orion5x MPP and GPIO setting code had writel arguments the wrong way around. Fixed and tested. Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
* | ARM: fix bug in macro __arch_ioremap.Terry Lv2010-06-22-7/+7
| | | | | | | | | | | | | | | | Signed-off-by: Terry Lv <r65388@freescale.com> Fix commit message and code formatting. Signed-off-by: Wolfgang Denk <wd@denx.de>
* | ARM: Align stack to 8 bytesVitaly Kuzmichev2010-06-22-6/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM ABI requires that the stack be aligned to 8 bytes as it is noted in Procedure Call Standard for the ARM Architecture: http://infocenter.arm.com/help/topic/com.arm.doc.ihi0042d/index.html Unaligned SP also causes the problem with variable-length arrays allocation when VLA address becomes less than stack pointer during aligning of this address, so the next 'push' in the stack overwrites first 4 bytes of VLA. Signed-off-by: Vitaly Kuzmichev <vkuzmichev@mvista.com> Tested on tx25(mx25), imx27lite(mx27), qong(mx31) and trab(s3c2400) Tested-by: Wolfgang Denk <wd@denx.de>
* | arch/arm/cpu/arm_cortexa8/omap3/cache.S: make build with older toolsWolfgang Denk2010-06-18-4/+4
|/ | | | | | | | | | | | | | | | | | | | | The push / pop instructions used in this file are available only with more recent tool chains: cache.S: Assembler messages: cache.S:133: Error: bad instruction `push {r0,r1,r2,lr}' cache.S:160: Error: bad instruction `pop {r1,r2,r3,pc}' cache.S:164: Error: bad instruction `push {r0,r1,r2,lr}' cache.S:191: Error: bad instruction `pop {r1,r2,r3,pc}' Change push/pop into stmfd/ldmfd instructions to support older versions of binutils as well. I verified that the modified source code generates exactly the same binary code. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Sandeep Paulraj <s-paulraj@ti.com> Cc: Tom Rix <tom@bumblecow.com>
* Merge branch 'fix' of git://git.denx.de/u-boot-pxaWolfgang Denk2010-06-17-1/+4
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| * PXA: Align stack to 8 bytesMarek Vasut2010-06-13-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Part of this patch is by: Mikhail Kshevetskiy. Stack must be aligned to 8 bytes on PXA (possibly all armv5te) for LDRD/STRD instructions. In case LDRD/STRD is issued on an unaligned address, the behaviour is undefined. The issue was observed when working with the NAND code, which was rendered disfunctional. Also, the vsprintf() function had serious problems with printing 64bit wide long longs. After aligning the stack, this wrong behaviour is no longer present. Tested on: Marvell Littleton PXA310 board Toradex Colibri PXA320 board Aeronix Zipit Z2 PXA270 handheld Voipac PXA270 board Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-marvellWolfgang Denk2010-06-17-0/+1175
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| * | Initial support for Marvell Orion5x SoCAlbert Aribaud2010-06-17-0/+1175
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the Marvell Orion5x SoC. It has no use alone, and must be followed by a patch to add Orion5x support for serial, then support for the ED Mini V2, an Orion5x-based product from LaCie. Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
* | | Merge branch 'master' of git://git.denx.de/u-boot-tiWolfgang Denk2010-06-17-0/+1
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: CONFLICT (rename/add): Rename board/davinci/da830evm/Makefile->board/ti/tnetv107xevm/Makefile in 89b765c7f6ddfde07ba673dd4adbeb5da391a81b. board/ti/tnetv107xevm/Makefile added in HEAD But files were identical, so no problem. Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | | TI: DaVinci: Add board specific code for da850 EVMSudhakar Rajashekhara2010-06-10-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provides initial support for TI OMAP-L138/DA850 SoC devices on a Logic PD EVM board. Provides: Initial boot and configuration. Support for i2c. UART support (console). Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Acked-by: Ben Gardiner <bengardiner@nanometrics.ca> Reviewed-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * | | AM35x: Add support for EMIF4Vaibhav Hiremath2010-06-07-0/+273
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the EMIF4 interface available in the AM35x processors. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Sanjeev Premi <premi@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * | | omap3: Consolidate SDRC related operationsVaibhav Hiremath2010-06-07-168/+220
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Consolidated SDRC related functions into one file - sdrc.c And also replaced sdrc_init with generic memory init function (mem_init), this generalization of omap memory setup is necessary to support the new emif4 interface introduced in AM3517. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * | | omap3: Calculate CS1 size only when SDRC isVaibhav Hiremath2010-06-07-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | initialized for CS1 From: Vaibhav Hiremath <hvaibhav@ti.com> The patch makes sure that size for SDRC CS1 gets calculated only when the CS1 SDRC is initialized. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * | | ARM1176: TI: TNETV107X soc initial supportCyril Chemparathy2010-06-07-0/+1872
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TNETV107X is a Texas Instruments SoC based on an ARM1176 core, and with a bunch on on-chip integrated peripherals. This is an initial commit with basic functionality, more commits with drivers, etc. to follow. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * | | ARM1176: Coexist with other ARM1176 platformsCyril Chemparathy2010-06-07-21/+47
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current ARM1176 CPU specific code is too specific to the SMDK6400 architecture. The following changes were necessary prerequisites for the addition of other SoCs based on ARM1176. Existing board's (SMDK6400) configuration has been modified to keep behavior unchanged despite these changes. 1. Peripheral port remap configurability The earlier code had hardcoded remap values specific to s3c64xx in start.S. This change makes the peripheral port remap addresses and sizes configurable. 2. U-Boot code relocation support Most architectures allow u-boot code to run initially at a different address (possibly in NOR) and then get relocated to its final resting place in RAM. Added support for this capability in ARM1176 architecture. 3. Disable TCM if necessary If a ROM based bootloader happened to have initialized TCM, we disable it here to keep things sane. 4. Remove unnecessary SoC specific includes ARM1176 code does not really need this SoC specific include. The presence of this include prevents builds on other ARM1176 archs. 5. Modified virt-to-phys conversion during MMU disable The original MMU disable code masks out too many bits from the load address when it tries to figure out the physical address of the jump target label. Consequently, it ends up branching to the wrong address after disabling the MMU. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2010-06-17-190/+2415
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| * AM35x: Add support for EMIF4Vaibhav Hiremath2010-06-08-0/+273
| | | | | | | | | | | | | | | | | | This patch adds support for the EMIF4 interface available in the AM35x processors. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Sanjeev Premi <premi@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * omap3: Consolidate SDRC related operationsVaibhav Hiremath2010-06-08-168/+220
| | | | | | | | | | | | | | | | | | | | | | Consolidated SDRC related functions into one file - sdrc.c And also replaced sdrc_init with generic memory init function (mem_init), this generalization of omap memory setup is necessary to support the new emif4 interface introduced in AM3517. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * omap3: Calculate CS1 size only when SDRC isVaibhav Hiremath2010-06-08-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | initialized for CS1 From: Vaibhav Hiremath <hvaibhav@ti.com> The patch makes sure that size for SDRC CS1 gets calculated only when the CS1 SDRC is initialized. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * ARM1176: TI: TNETV107X soc initial supportCyril Chemparathy2010-06-08-0/+1872
| | | | | | | | | | | | | | | | | | TNETV107X is a Texas Instruments SoC based on an ARM1176 core, and with a bunch on on-chip integrated peripherals. This is an initial commit with basic functionality, more commits with drivers, etc. to follow. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * ARM1176: Coexist with other ARM1176 platformsCyril Chemparathy2010-06-08-21/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current ARM1176 CPU specific code is too specific to the SMDK6400 architecture. The following changes were necessary prerequisites for the addition of other SoCs based on ARM1176. Existing board's (SMDK6400) configuration has been modified to keep behavior unchanged despite these changes. 1. Peripheral port remap configurability The earlier code had hardcoded remap values specific to s3c64xx in start.S. This change makes the peripheral port remap addresses and sizes configurable. 2. U-Boot code relocation support Most architectures allow u-boot code to run initially at a different address (possibly in NOR) and then get relocated to its final resting place in RAM. Added support for this capability in ARM1176 architecture. 3. Disable TCM if necessary If a ROM based bootloader happened to have initialized TCM, we disable it here to keep things sane. 4. Remove unnecessary SoC specific includes ARM1176 code does not really need this SoC specific include. The presence of this include prevents builds on other ARM1176 archs. 5. Modified virt-to-phys conversion during MMU disable The original MMU disable code masks out too many bits from the load address when it tries to figure out the physical address of the jump target label. Consequently, it ends up branching to the wrong address after disabling the MMU. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * ARM1136: Fix cache_flush() error and correct cpu_init_crit() commentsGeorge G. Davis2010-06-01-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM1136 cache_flush() function uses the "mcr p15, 0, rn, c7, c7, 0" instruction which means "Invalidate Both Caches" when in fact the intent is to clean and invalidate all caches. So add an "mcr p15, 0, %0, c7, c10, 0" instruction to "Clean Entire Data Cache" prior to the "Invalidate Both Caches" instruction to insure that memory is consistent with any dirty cache lines. Also fix a couple of "flush v*" comments in ARM1136 cpu_init_crit() so that they correctly describe the actual ARM1136 CP15 C7 Cache Operations used. Signed-off-by: George G. Davis <gdavis@mvista.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2010-05-30-3/+6
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| * | fsl/85xx: add clkdvdr and pmuxcr2 to global utilities structure definitionTimur Tabi2010-05-30-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | Add the 'clkdvdr' and 'pmuxcr2' registers to the 85xx definition of struct ccsr_gur. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2010-05-30-8/+1165
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| * ARM Update mach-typesTom2010-05-28-6/+500
| | | | | | | | | | | | | | | | | | | | Fetched from http://www.arm.linux.org.uk/developer/machines/download.php And built with repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm commit 3defb2476166445982a90c12d33f8947e75476c4 Signed-off-by: Tom <Tom@bumblecow.com>
| * ARM Update mach-typesTom2010-05-28-2/+665
| | | | | | | | | | | | | | | | | | | | Fetched from http://www.arm.linux.org.uk/developer/machines/download.php And built with repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm commit 257dab81413b31b8648becfe11586b3a41e5c29a Signed-off-by: Tom <Tom@bumblecow.com>
* | Merge branch 'next' of git://git.denx.de/u-boot-niosWolfgang Denk2010-05-28-3588/+911
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| * | nios: remove nios-32 archThomas Chou2010-05-28-3403/+0
| | | | | | | | | | | | | | | | | | The nios-32 arch is obsolete and broken. So it is removed. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
| * | nios2: allow STANDALONE_LOAD_ADDR overridingThomas Chou2010-05-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows users to override default STANDALONE_LOAD_ADDR. The gcclibdir path was duplicated in the standalone Makefile and can be removed. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
| * | nios2: fix div64 issue for gcc4Thomas Chou2010-05-28-175/+856
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the run-time error on div64 when built with gcc4, which was reported by jhwu0625 on nios forum. It merges math support from libgcc of gcc4. This patch is copied from nios2-linux. It works with both gcc3 and gcc4. The old mult.c, divmod.c and math.h are removed. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
| * | nios2: fix r15 issue for gcc4Thomas Chou2010-05-28-9/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "-ffixed-r15" option doesn't work well for gcc4. Since we don't use gp for small data with option "-G0", we can use gp as global data pointer. This allows compiler to use r15. It is necessary for gcc4 to work properly. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
| * | nios2: add gpio supportThomas Chou2010-05-28-0/+52
| |/ | | | | | | | | | | | | | | | | | | | | | | | | This patch adds driver for a trivial gpio core, which is described in http://nioswiki.com/GPIO. It is used for gpio led and nand flash interface in u-boot. When CONFIG_SYS_GPIO_BASE is not defined, board may provide its own driver. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Tested-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
* | add CONFIG_SYS_FEC_FULL_MII for MCF5445xWolfgang Wegner2010-05-28-2/+11
| | | | | | | | | | | | | | This patch adds support for full MII interface on MCF5445x (in contrast to RMII as used on the evaluation boards). Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de>
* | add CONFIG_SYS_FEC_NO_SHARED_PHY for MCF5445xWolfgang Wegner2010-05-28-0/+11
| | | | | | | | | | | | | | | | This patch adds the possibility to handle seperate PHYs to MCF5445x. Naming is chosen to resemble the contrary CONFIG_FEC_SHARED_PHY in the linux kernel. Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de>
* | add missing PCS3 for MCF5445xWolfgang Wegner2010-05-28-0/+8
|/ | | | | | | This patch adds the code for handling PCS3 (DSPI chip select 3) in cpu_init.c and m5445x.h Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de>
* Coding style cleanup, update CHANGELOG.Wolfgang Denk2010-05-26-3/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2010-05-26-20/+20
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| * mpc83xx: don't shift pre-shifted ACR, SPCR, SCCR bitfield masks in cpu_init.cKim Phillips2010-05-21-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit c7190f028fa950d4d36b6d0b4bb3fc72602ec54c "mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields" incorrectly shifted <register>_<bitfield> (e.g. ACR_PIPE_DEP) values that were preshifted by their definition in mpc83xx.h. this patch removes the unnecessary shifting for the newly utilized mask values in cpu_init.c, and prevents seemingly unrelated symptoms such as an mpc8379erdb board from locking up whilst performing a networking operation, e.g. a tftp. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * Fixed two typos in arch/powerpc/cpu/mpc83xx/start.S.Horst Kronstorfer2010-05-21-2/+2
| | | | | | | | | | Signed-off-by: Horst Kronstorfer <hkronsto@frequentis.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | Convert Makefiles from COBJS-${} to COBJS-$()Kumar Gala2010-05-26-5/+5
| | | | | | | | | | | | Match style we use almost everywhere else Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/bootcount: Fix endianness problemMichael Weiss2010-05-26-2/+4
| | | | | | | | | | | | | | For CONFIG_SYS_BOOTCOUNT_SINGLEWORD the code had an endianness problem. Signed-off-by: Michael Weiss <michael.weiss@ifm.com> Signed-off-by: Detlev Zundel <dzu@denx.de>
* | a320evb: fix udelay / __udelay confusionWolfgang Denk2010-05-21-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Fix the following compiler problems: arch/arm/cpu/arm920t/a320/liba320.a(timer.o): In function `udelay': /home/wd/git/u-boot/work/arch/arm/cpu/arm920t/a320/timer.c:160: multiple definition of `udelay' lib/libgeneric.a(time.o):/home/wd/git/u-boot/work/lib/time.c:34: first defined here lib/libgeneric.a(time.o): In function `udelay': time.c:(.text+0x1c): undefined reference to `__udelay' Signed-off-by: Wolfgang Denk <wd@denx.de>
* | ARM: */timer.c: fix spelling and vertical alignmentWolfgang Denk2010-05-21-18/+18
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-imxWolfgang Denk2010-05-21-1/+1
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