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* OMAP5: add ABB setup for MPU voltage domainAndrii Tseglytskyi2013-06-10-0/+16
| | | | | | | | Patch adds a call of abb_setup() function, and proper registers definitions needed for ABB setup sequence. ABB is initialized for MPU voltage domain. Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
* OMAP3+: introduce generic ABB supportAndrii Tseglytskyi2013-06-10-0/+256
| | | | | | | | | | | | | | | | | Adaptive Body Biasing (ABB) modulates transistor bias voltages dynamically in order to optimize switching speed versus leakage. Adaptive Body-Bias ldos are present for some voltage domains starting with OMAP3630. There are three modes of operation: * Bypass - the default, it just follows the vdd voltage * Foward Body-Bias - applies voltage bias to increase transistor performance at the cost of power. Used to operate safely at high OPPs. * Reverse Body-Bias - applies voltage bias to decrease leakage and save power. Used to save power at lower OPPs. Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com> Acked-by: Nishanth Menon <nm@ti.com>
* Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-06-08-4/+1300
|\ | | | | | | | | Conflicts: drivers/serial/Makefile
| * arm: mxs: Fix vectoring table craftingMarek Vasut2013-06-03-3/+22
| | | | | | | | | | | | | | | | | | | | | | | | The vectoring table has to be placed at 0x0, but U-Boot on MX23/MX28 starts from RAM, so the vectoring table at 0x0 is not present. Craft code that will be placed at 0x0 and will redirect interrupt vectoring to proper location of the U-Boot in RAM. Signed-off-by: Marek Vasut <marex@denx.de> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
| * arm: vf610: Add Vybrid VF610 CPU supportAlison Wang2013-06-03-0/+1253
| | | | | | | | | | | | | | | | | | | | | | This patch adds generic codes to support Freescale's Vybrid VF610 CPU. It aligns Vybrid VF610 platform with i.MX platform. As there are some differences between VF610 and i.MX platforms, the specific codes are in the arch/arm/cpu/armv7/vf610 directory. Signed-off-by: Alison Wang <b18965@freescale.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * arm: vf610: Add IOMUX support for Vybrid VF610Alison Wang2013-06-03-1/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the IOMUX support for Vybrid VF610 platform. There is a little difference for IOMUXC module between VF610 and i.MX platform, the muxmode and pad configuration share one 32bit register on VF610, but they are two independent registers on I.MX platform. A CONFIG_IOMUX_SHARE_CONFIG_REG was introduced to fit this difference. Signed-off-by: Alison Wang <b18965@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* | ARM: tegra: only enable SCU on Tegra20Tom Warren2013-06-06-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The non-SPL build of U-Boot on Tegra only runs on a single CPU, and hence there is no need to enable the SCU when running U-Boot. If an SMP OS is booted, and it needs the SCU enabled, it will enable the SCU itself. U-Boot doing so is redundant. The one exception is Tegra20, where an enabled SCU is required for some aspects of PCIe to work correctly. Some Tegra SoCs contain CPUs without a software-controlled SCU. In this case, attempting to turn it on actively causes problems. This is the case for Tegra114. For example, when running Linux, the first (or at least some very early) user-space process will trigger the following kernel message: Unhandled fault: imprecise external abort (0x406) at 0x00000000 This is typically accompanied by that process receving a fatal signal, and exiting. Since this process is usually pid 1, this causes total system boot failure. Signed-off-by: Tom Warren <twarren@nvidia.com> [swarren, fleshed out description, ported to upstream chipid APIs] Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | am33xx/omap: Move save_omap_boot_params to omap-common/boot-common.cTom Rini2013-06-05-36/+42
| | | | | | | | | | | | | | | | | | | | | | We need to call the save_omap_boot_params function on am33xx/ti81xx and other newer TI SoCs, so move the function to boot-common. Only OMAP4+ has the omap_hw_init_context function so add ifdefs to not call it on am33xx/ti81xx. Call save_omap_boot_params from s_init on am33xx/ti81xx boards. Reviewed-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* | am33xx: Correct NON_SECURE_SRAM_START/ENDTom Rini2013-06-04-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prior to Sricharan's cleanup of the boot parameter saving code, we did not make use of NON_SECURE_SRAM_START on am33xx, so it wasn't a problem that the address was pointing to the middle of our running SPL. Correct to point to the base location of the download image area. Increase CONFIG_SPL_TEXT_BASE to account for this scratch area being used. As part of correcting these tests, make use of the fact that we've always been placing our stack outside of the download image area (which is fine, once the downloaded image is run, ROM is gone) so correct the max size test to be the ROM defined top of the download area to where we link/load at. Signed-off-by: Tom Rini <trini@ti.com> --- Changes in v2: - Fix typo noted by Peter Korsgaard
* | omap-common/hwinit-common.c: Mark omap_rev_string as staticTom Rini2013-06-04-1/+1
| | | | | | | | | | | | Only called in this file, mark as static. Signed-off-by: Tom Rini <trini@ti.com>
* | arm: factorize relocate_code routineAlbert ARIBAUD2013-05-30-992/+124
| | | | | | | | | | | | | | | | | | | | | | Replace all relocate_code routines from ARM start.S files with a single instance in file arch/arm/lib/relocate.S. For PXA, this requires moving the dcache unlocking code from within relocate_code into c_runtime_cpu_setup. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Tested-by: Simon Glass <sjg@chromium.org>
* | arm: do not compile relocate_code() for SPL buildsAlbert ARIBAUD2013-05-30-81/+55
| | | | | | | | | | | | Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Tested-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-05-30-8455/+1488
|\ \ | | | | | | | | | | | | | | | Conflicts: common/cmd_fpga.c drivers/usb/host/ohci-at91.c
| * | powerpc/mpc85xx: Clear L1 D-cache lockYork Sun2013-05-24-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | dcbi instruction has been used to clear D-cache lock. However, the cache lock is persistent for e6500 core. Use dcblc to clear the lock explicitly. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | SECURE BOOT - Removed deletion of TLB entries codeRuchika Gupta2013-05-24-17/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boot ROM code creates TLB entries for 3.5G space before entering the u-boot. Earlier we were deleting these entries after early initialization of CPU. In recent past, code has been added to invalidate all these entries before relocation of u-boot code. So this code to delete TLB entries after CPU initialization is no longer required. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Acked-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/b4860qds: Add LAW Target ID and Create LAW entry for MapleShaveta Leekha2013-05-24-0/+2
| | | | | | | | | | | | | | | Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/B4: Merge B4420 and B4860 in config_mpc85xx.hPoonam Aggrwal2013-05-24-23/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | B4420 is a subset of B4860. Merge them in config_mpc85xx.h to simplify the defines. - Removed #define CONFIG_SYS_FSL_NUM_CLUSTERS as this is used nowhere. - defined CONFIG_SYS_NUM_FM1_10GEC to 0 for B4420 as it does not have 10G. Also move CONFIG_E6500 out of B4860QDSds.h into config_mpc85xx.h. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/mpc8xxx: Allow DDR overclockYork Sun2013-05-24-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow DDR clock runs faster than SPD specifes. This may cause memory failure, but the user should know what is going to happen when using higher than expected DDR clock. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/chassis2: Change core numbering schemeYork Sun2013-05-24-58/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To align with chassis generation 2 spec, all cores are numbered in sequence. The cores may reside across multiple clusters. Each cluster has zero to four cores. The first available core is numbered as core 0. The second available core is numbered as core 1 and so on. Core clocks are generated by each clusters. To identify the cluster of each core, topology registers are examined. Cluster clock registers are reorganized to be easily indexed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/mpc8xxx: Add T1040 and variant SoCsYork Sun2013-05-24-0/+282
| | | | | | | | | | | | | | | | | | | | | | | | | | | T1040 and variants have e5500 cores and are compliant to QorIQ Chassis Generation 2. The major difference between T1040 and its variants is the number of cores and the number of L2 switch ports. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/T4160: Merge T4160 and T4240 in config_mpc85xx.hYork Sun2013-05-24-32/+10
| | | | | | | | | | | | | | | | | | | | | | | | T4160 is a subset of T4240. Merge them in config_mpc85xx.h to simplify the defines. Also move CONFIG_E6500 out of t4qds.h into config_mpc85xx.h. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | Add e6500 L2 replacement policy selectionJames Yang2013-05-24-1/+11
| | | | | | | | | | | | | | | | | | | | | This is compile-time config. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/mpc85xx: check if core is disabled for showing statusYork Sun2013-05-24-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | "cpu <num> status" should check if core is disabled before printing the spin table location. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | Enable L2 cache parity/ECC error checkingJames Yang2013-05-24-2/+2
| | | | | | | | | | | | | | | Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xxTom Rini2013-05-15-107/+376
| |\ \
| | * | powerpc/mpc8xxx: Allow board file to override DDR address assignmentYork Sun2013-05-14-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This gives boards flexibility to assign other than default addresses to each DDR controller. For example, DDR controler 2 can have 0 as the base and DDR controller 1 has higher memory. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | powerpc/mpc85xx: Update workaround for DDR erratum A-004934York Sun2013-05-14-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The workaround has been updated to use a slightly different magic number. Change from 0x00003000 to 0x30003000. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | T4/usb: move usb 2.0 utmi dual phy init code to cpu_init.cRoy Zang2013-05-14-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is what we have done for the UTMI PHY on P3041/P5020. Then the PHY initialization can be reused in kernel without “usb start” command. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | powerpc/85xx: fix build error introduced by serdes_get_prtclShengzhou Liu2013-05-14-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Removed unused declare serdes_get_prtcl() which was no longer needed. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | t4240qds/eth: fixup ethernet for t4240qdsShengzhou Liu2013-05-14-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1, Implemented board_ft_fman_fixup_port() to fix port for kernel. 2, Implemented fdt_fixup_board_enet() to fix node status of different slots and interfaces. 3, Adding detection of slot present for XGMII interface. 4, There is no PHY for XFI, so removed related phy address settings. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | powerpc/85xx: add missing QMAN frequency calculationShaohui Xie2013-05-14-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_SYS_FSL_QORIQ_CHASSIS2 is not defined, QMAN frequency will not be initialized, and QMAN will have a wrong frequency display. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | powerpc/mpc85xx: Add T4160 SoCYork Sun2013-05-14-2/+172
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T4160 SoC is low power version of T4240. The T4160 combines eight dual threaded Power Architecture e6500 cores and two memory complexes (CoreNet platform cache and DDR3 memory controller) with the same high-performance datapath acceleration, networking, and peripheral bus interfaces. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | powerpc/t4240: Fix SerDes protocol arrays with const prefixYork Sun2013-05-14-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Protocols are constants. Fix arrays with const prefix. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | powerpc/mpc85xx: Fix PIR parsing for chassis2York Sun2013-05-14-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PIR parsing algorithm we used is not only for E6500. It applies to all SoCs with chassis 2. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | powerpc/corenet2: Print SerDes protocol in decimalYork Sun2013-05-14-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use decimal and hexadecimal for protocol numbers. It helps to match with SoC user manual. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | T4/USB: Add USB 2.0 UTMI dual phy supportRoy Zang2013-05-14-2/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T4240 internal UTMI phy is different comparing to previous UTMI PHY in P3041. This patch adds USB 2.0 UTMI Dual PHY new memory map and enable it for T4240. The phy timing is very sensitive and moving the phy enable code to cpu_init.c will not work. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | powerpc/mpc85xx: Fix portal setupYork Sun2013-05-14-14/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Missing nodes of crypto, pme, etc in device tree is not a fatal error. Setting up the qman portal should skip the missing node and continue to finish the rest. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | powerpc/mpc8xxx: Fix DDR 3-way interleavingYork Sun2013-05-14-8/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Should check if interleaving is enabled before using interleaving mode. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | T4/SerDes: correct the SATA indexRoy Zang2013-05-14-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Lane H on SerDes4 should be SATA2 instead of SATA1 Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | e6500: Move L1 enablement after L2 enablementAndy Fleming2013-05-14-47/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The L1 D-cache on e6500 is write-through. This means that it's not considered a good idea to have the L1 up and running if the L2 is disabled. We don't actually *use* the L1 until after the L2 is brought up on e6500, so go ahead and move the L1 enablement after that code is done. Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | powerpc/mpc85xx: Update corenet global utility block registersYork Sun2013-05-14-11/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix ccsr_gur for corenet platform. Remove non-exist registers. Add fuse status register. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | powerpc/mpc85xx: Add definitions for HDBCR registersAndy Fleming2013-05-14-8/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Makes it a bit easier to see if we've properly set them. While we're in there, modify the accesses to HDBCR0 and HDBCR1 to actually use those definitions. Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | powerpc/B4860: Corrected FMAN1 operating frequency print at u-bootSandeep Singh2013-05-14-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The bit positions for FMAN1 freq in RCW is different for B4860. Also addded a case when FMAN1 frewuency is equal to systembus. Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | | Power: remove support for Freescale MPC8220Wolfgang Denk2013-05-15-6061/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Freescale MPC8220 Power Architecture processors have long reached EOL; Freescale does not even list these any more on their web site. Remove the code to avoid wasting maitaining efforts on dead stuff. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Andy Fleming <afleming@gmail.com>
| * | | sparc: Use image_setup_linux() instead of local codeSimon Glass2013-05-14-10/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sparc only really sets up the ramdisk, but we should still use image_setup_linux() so that setup is common across all architectures that use the FDT. Cover-letter Introduce a common image_setup_linux() function This series continues the work to tidy up the image code. Each architecture has its own code for setting up ready for booting linux. An attempt is made here to unify these in a single image_setup_linux() function. The part of the image code that deals with FDT is split into image-fdt.c and a few tweaks are added to make FIT images more viable in SPL. END Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | m68k: Use image_setup_linux() instead of local codeSimon Glass2013-05-14-12/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than having similar code in m68k, use image_setup_linux() which should be common across all architectures that use the FDT. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | powerpc: Use image_setup_linux() instead of local codeSimon Glass2013-05-14-83/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than having similar code in powerpc, use image_setup_linux() which should be common across all architectures that use the FDT. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | arm: Use image_setup_linux() instead of local codeSimon Glass2013-05-14-56/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the common FDT setup function that is now available in image. Move the FDT-specific code to a new bootm-fdt.c and remove unused headers from bootm.c. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | arm: Refactor bootm to reduce #ifdefsSimon Glass2013-05-14-68/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With fewer #ifdefs the code is more readable and more of the code is compiled for all boards. Add defines in the header file to control what features are enabled, and then use if() instead of #ifdef. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | Merge branch 'master' of git://git.denx.de/u-boot-blackfin into ↵Tom Rini2013-05-14-702/+290
| |\ \ \ | | |/ / | |/| | | | | | powerpc-eldk53-warning-fixes
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