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* arm: Move timer_rate_hz into arch_global_dataSimon Glass2013-02-01-15/+17
| | | | | | Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* at91: Move at91 global data into arch_global_dataSimon Glass2013-02-01-41/+45
| | | | | | Move these fields into arch_global_data. Signed-off-by: Simon Glass <sjg@chromium.org>
* Add architecture-specific global dataSimon Glass2013-02-01-2/+79
| | | | | | | | | | | | | We plan to move architecture-specific data into a separate structure so that we can make the rest of it common. As a first step, create struct arch_global_data to hold these fields. Initially it is empty. This patch applies to all archs at once. I can split it if this is really a pain. Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: fix CONFIG_DELAY_ENVIRONMENT to act like it claims in the READMELucas Stach2013-01-30-1/+1
| | | | | | | | | No one expects to end up in a delayed environment if CONFIG_DELAY_ENVIRONMENT isn't defined. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Allen Martin <amartin@nvidia.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2013-01-30-74/+130
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| * MIPS: add unified u-boot.lds fileGabor Juhos2013-01-31-0/+84
| | | | | | | | | | | | | | | | | | | | | | | | The patch adds an unified linker script file which can be used for all currently supported MIPS targets. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Stefan Roese <sr@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Xiangfu Liu <xiangfu@openmobilefree.net> Acked-by: Stefan Roese <sr@denx.de>
| * MIPS: remove OUTPUT_FORMAT from linker scriptsGabor Juhos2013-01-30-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The OUTPUT_FORMAT command in linker scripts was always misused due to some endianess and toolchain problems. Use GCC flags to ensure proper output format, and get rid of the OUTPUT_FORMAT commands in the board specific u-boot.lds files. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Stefan Roese <sr@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
| * MIPS: xburst: simplify relocation offset calculationGabor Juhos2013-01-30-9/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code uses four instructions and a temporary register to calculate the relocation offset and to adjust the gp register. The relocation offset can be calculated directly from the CONFIG_SYS_MONITOR_BASE constant and from the destination address. The resulting offset can be used to adjust the gp pointer. This approach makes the code a bit simpler because it needs two instructions only. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
| * MIPS: simplify relocated _G_O_T_ address calculationGabor Juhos2013-01-30-12/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The difference between the address of the original and the relocated _GLOBAL_OFFSET_TABLE_ is always the same as the relocation offset. The relocation offset is already computed and it is available in the 's1/t6' register. Use that to adjust the relocated _G_O_T_ address, instead of calculating the offset again from the _gp value. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
| * MIPS: start.S: don't save flush_cache parameters in advanceGabor Juhos2013-01-27-20/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Saving the parameters in advance unnecessarily complicates the code. The destination address is already saved in the 's2' register, and that register is not clobbered by the copy loop. The size of the copied data can be computed after the copy loop is done. Change the code to compute the size parameter right before calling flush_cache, and set the destination address parameter in the delay slot of the actuall call. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * MIPS: start.S: simplify relocation offset calculationGabor Juhos2013-01-27-18/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code uses four instructions and a temporary register to calculate the relocation offset and to adjust the gp register. The relocation offset can be calculated directly from the CONFIG_SYS_MONITOR_BASE constant and from the destination address. The resulting offset can be used to adjust the gp pointer. This approach makes the code a bit simpler because it needs two instructions only. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * MIPS: start.S: save reused arguments earlier in relocate_codeGabor Juhos2013-01-27-4/+6
| | | | | | | | | | | | | | | | | | Save the reused parameters at the beginning of the 'relocate_code' function. This makes the function a bit more readable. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * MIPS: start.S: set sp register directlyGabor Juhos2013-01-27-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code uses two instructions to load the stack pointer into the 'sp' register. This results in the following assembly code: 468: 3c088040 lui t0,0x8040 46c: 251d0000 addiu sp,t0,0 The first instuction loads the stack pointer into the 't0' register then the value of the 'sp' register is computed by adding zero to the value of the 't0' register. The same issue present on the 64-bit version as well: 56c: 3c0c8040 lui t0,0x8040 570: 659d0000 daddiu sp,t0,0 Change the code to load the stack pointer directly into the 'sp' register. The generated code is functionally equivalent to the previous version but it is simpler. 32-bit: 468: 3c1d8040 lui sp,0x8040 64-bit: 56c: 3c1d8040 lui sp,0x8040 Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * MIPS: start.S: fix boundary check in relocate_codeGabor Juhos2013-01-27-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | The loop code copies more data with one than necessary due to the 'ble' instuction. Use the 'blt' instruction instead to fix that. Due to the lack of suitable hardware the Xburst specific code is compile tested only. However the change is quite obvious. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * MIPS: start{, 64}.S: fill branch delay slots with NOP instructionsGabor Juhos2013-01-22-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The romReserved and romExcHandle handlers are accessed by a branch instruction however the delay slots of those instructions are not filled. Because the start.S uses the 'noreorder' directive, the assembler will not fill the delay slots either, and leads to the following assembly code: 0000056c <romReserved>: 56c: 1000ffff b 56c <romReserved> 00000570 <romExcHandle>: 570: 1000ffff b 570 <romExcHandle> In the resulting code, the second branch instruction is placed into the delay slot of the first branch instruction, which is not allowed on the MIPS architecture. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * MIPS: convert IO port accessor functions to 'static inline'Gabor Juhos2013-01-22-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The currently used 'extern inline' directive causes the following compiler warnings if CONFIG_SWAP_IO_SPACE is defined: <...>/include/asm/io.h:345:1: warning: '__fswab32' is static but used in inline function '__outlc_p' which is not static [enabled by default] <...>/include/asm/io.h:345:1: warning: '__fswab32' is static but used in inline function '__outl_p' which is not static [enabled by default] <...>/include/asm/io.h:345:1: warning: '__fswab32' is static but used in inline function '__outlc' which is not static [enabled by default] <...>/include/asm/io.h:345:1: warning: '__fswab32' is static but used in inline function '__outl' which is not static [enabled by default] <...>/include/asm/io.h:344:1: warning: '__fswab16' is static but used in inline function '__outwc_p' which is not static [enabled by default] <...>/include/asm/io.h:344:1: warning: '__fswab16' is static but used in inline function '__outw_p' which is not static [enabled by default] <...>/include/asm/io.h:344:1: warning: '__fswab16' is static but used in inline function '__outwc' which is not static [enabled by default] <...>/include/asm/io.h:344:1: warning: '__fswab16' is static but used in inline function '__outw' which is not static [enabled by default] <...>/include/asm/io.h:341:1: warning: '__fswab32' is static but used in inline function '__inlc_p' which is not static [enabled by default] <...>/include/asm/io.h:341:1: warning: '__fswab32' is static but used in inline function '__inl_p' which is not static [enabled by default] <...>/include/asm/io.h:341:1: warning: '__fswab32' is static but used in inline function '__inlc' which is not static [enabled by default] <...>/include/asm/io.h:341:1: warning: '__fswab32' is static but used in inline function '__inl' which is not static [enabled by default] <...>/include/asm/io.h:340:1: warning: '__fswab16' is static but used in inline function '__inwc_p' which is not static [enabled by default] <...>/include/asm/io.h:340:1: warning: '__fswab16' is static but used in inline function '__inw_p' which is not static [enabled by default] <...>/include/asm/io.h:340:1: warning: '__fswab16' is static but used in inline function '__inwc' which is not static [enabled by default] <...>/include/asm/io.h:340:1: warning: '__fswab16' is static but used in inline function '__inw' which is not static [enabled by default] Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * MIPS: use inline directive for __in*s functionsGabor Juhos2013-01-22-1/+1
| | | | | | | | | | | | | | | | | | All other IO accessor functions are using the 'inline' directive. Use that also for the __in*s to make it consistent with the other variants. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
* | powerpc/t4240: Adding workaround errata A-005871Shengzhou Liu2013-01-30-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When CoreNet Fabric (CCF) internal resources are consumed by the cores, inbound SRIO messaging traffic through RMan can put the device into a deadlock condition. This errata workaround forces internal resources to be reserved for upstream transactions. This ensures resources exist on the device for upstream transactions and removes the deadlock condition. The Workaround is for the T4240 silicon rev 1.0. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/mpc85xx: Add property 'fsl, sec-era' in device tree node 'crypto'Vakul Garg2013-01-30-1/+92
| | | | | | | | | | | | | | | | | | | | If property 'fsl,sec-era' is already present, it is updated. This property is required so that applications can ascertain which descriptor commands are supported on a particular CAAM version. Signed-off-by: Vakul Garg <vakul@freescale.com> Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | mpc8xxx: fix DDR init value to use CONFIG_MEM_INIT_VALUEAnatolij Gustschin2013-01-30-0/+4
| | | | | | | | | | | | | | | | | | | | | | Configuring custom memory init value using CONFIG_MEM_INIT_VALUE in the board config file doesn't work and memory is always initialized to the value 0xdeadbeef. Only use this default value if a board doesn't define CONFIG_MEM_INIT_VALUE. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Andy Fleming <afleming@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/mpc85xx: add support for MMUv2 page sizesScott Wood2013-01-30-24/+49
| | | | | | | | | | | | | | | | e6500 implements MMUv2 and supports power-of-2 page sizes rather than power-of-4. Add support for such pages. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/mpc85xx: Add BSC9132/BSC9232 processor supportPrabhakar Kushwaha2013-01-30-2/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The BSC9132 is a highly integrated device that targets the evolving Microcell, Picocell, and Enterprise-Femto base station market subsegments. The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850 core technologies with MAPLE-B2P baseband acceleration processing elements to address the need for a high performance, low cost, integrated solution that handles all required processing layers without the need for an external device except for an RF transceiver or, in a Micro base station configuration, a host device that handles the L3/L4 and handover between sectors. The BSC9132 SoC includes the following function and features: - Power Architecture subsystem including two e500 processors with 512-Kbyte shared L2 cache - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2 cache - 32 Kbyte of shared M3 memory - The Multi Accelerator Platform Engine for Pico BaseStation Baseband Processing (MAPLE-B2P) - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including ECC), up to 1333 MHz data rate - Dedicated security engine featuring trusted boot - Two DMA controllers - OCNDMA with four bidirectional channels - SysDMA with sixteen bidirectional channels - Interfaces - Four-lane SerDes PHY - PCI Express controller complies with the PEX Specification-Rev 2.0 - Two Common Public Radio Interface (CPRI) controller lanes - High-speed USB 2.0 host and device controller with ULPI interface - Enhanced secure digital (SD/MMC) host controller (eSDHC) - Antenna interface controller (AIC), supporting four industry standard JESD207/four custom ADI RF interfaces - ADI lanes support both full duplex FDD support & half duplex TDD - Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards - Two DUART, two eSPI, and two I2C controllers - Integrated Flash memory controller (IFC) - GPIO - Sixteen 32-bit timers Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/mpc8xxxx: FSL DDR debugger auto run of stored commandsJames Yang2013-01-30-11/+47
| | | | | | | | | | | | | | | | | | | | | | This patch adds the ability for the FSL DDR interactive debugger to automatically run the sequence of commands stored in the ddr_interactive environment variable. Commands are separated using ';'. ddr_interactive=compute; edit c0 d0 dimmparms caslat_X 0x3FC0; go Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | Add copy command to FSL DDR interactiveJames Yang2013-01-30-0/+127
| | | | | | | | | | | | | | | | | | Add copy command which allows copying of DIMM/controller settings. This saves tedious retyping of parameters for each identical DIMM or controller. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | Fix data stage name matching issueJames Yang2013-01-30-1/+2
| | | | | | | | | | | | | | | | | | | | This fix allows the name of the stage to be specifed after the controler and DIMM is specified. Prior to this fix, if the data stage name is not the first entry on the command line, the operation is applied to all controller and DIMMs. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | Move DDR command parsing to separate functionJames Yang2013-01-30-79/+74
| | | | | | | | | | | | | | | | Move the FSL DDR prompt command parsing to a separate function so that it can be reused. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/mpc8xxx: Enable entering DDR debugging by key pressYork Sun2013-01-30-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using environmental variable "ddr_interactive" to activate interactive DDR debugging seomtiems is not enough. For example, after updating SPD with a valid but wrong image, u-boot won't come up due to wrong DDR configuration. By enabling key press method, we can enter debug mode to have a chance to boot without using other tools to recover the board. CONFIG_FSL_DDR_INTERACTIVE needs to be defined in header file. To enter the debug mode by key press, press key 'd' shortly after reset, like one would do to abort auto booting. It is fixed to lower case 'd' at this moment. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/mpc85xx:Fix Core cluster configuration loopPrabhakar Kushwaha2013-01-30-8/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Different personalities/derivatives of SoC may have reduced cluster. But it is not necessary for last valid DCFG_CCSR_TP_CLUSTER register to have DCFG_CCSR_TP_CLUSTER[EOC] bit set to represent "End of Clusters". EOC bit can still be set in last DCFG_CCSR_TP_CLUSTER register of orignal SoC which may not be valid for the personality. So add initiator type check to find valid cluster. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/mpc85xx:Add support of B4420 SoCPoonam Aggrwal2013-01-30-1/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900 and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and reduced target frequencies. Key differences between B4860 and B4420 ---------------------------------------- B4420 has: 1. Fewer e6500 cores: 1 cluster with 2 e6500 cores 2. Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster. 3. Single DDRC 4. 2X 4 lane serdes 5. 3 SGMII interfaces 6. no sRIO 7. no 10G Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/mpc85xx: Few updates for B4860 cpu changesPoonam Aggrwal2013-01-30-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Added some more serdes1 and serdes2 combinations serdes1= 0x2c, 0x2d, 0x2e serdes2= 0x7a, 0x8d, 0x98 - Updated Number of DDR controllers to 2. - Added FMAN file for B4860, drivers/net/fm/b4860.c Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/mpc85xx: Reserve default boot pageYork Sun2013-01-30-0/+16
| | | | | | | | | | | | | | | | | | The boot page in memory is already reserved so OS won't overwrite. As long as the boot page translation is active, the default boot page also needs to be reserved in case the memory is 4GB or more. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxTom Rini2013-01-29-13/+92
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| * Merge remote-tracking branch 'mpc83xx/next'Kim Phillips2013-01-16-13/+92
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| | * powerpc/mpc83xx: add support for new SPLScott Wood2012-12-19-13/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds arch support for PPC mpc83xx to boot "minimal" (4K) SPLs using the new infrastructure. Existing nand_spl targets are updated to deal with the name change from nand_init.c to spl_minimal.c (as in theory this isn't limited to NAND anymore). Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | | MIPS: bootm.c: add support for 'prep' and 'go' subcommandsGabor Juhos2013-01-16-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The bootm command supports subcommands since long time however those subcommands are not yet usable on MIPS. The patch is based on the ARM implementation, and it adds support for the 'prep' and 'go' subcommands only. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
* | | MIPS: bootm.c: separate environment initializationGabor Juhos2013-01-16-23/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move the environment initialization code into a separate function. This make the code reusable for bootm subcommands. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
* | | MIPS: bootm.c: separate linux jump codeGabor Juhos2013-01-16-13/+19
| | | | | | | | | | | | | | | | | | | | | | | | Move the actual jump code into a separate function. This make the code reusable for bootm subcommands. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
* | | MIPS: bootm.c: use debug macro to print debug messageGabor Juhos2013-01-16-3/+1
|/ / | | | | | | | | | | | | | | The '## Transferring control ...' message is printed only if DEBUG is enabled. Get rid of the 'ifdef DEBUG' statement and use the debug macro instead. Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
* | pxa: Save lr register in relocate_code functionŁukasz Dałek2013-01-14-0/+2
| | | | | | | | | | | | | | | | | | | | | | When u-boot is compiled for PXA25x processor, pxa/start.S is calling cpu_init_crit by BL instruction. BL is overwriting lr register so relocate_code is going into infinite loop. This patch preservs lr register in r12 before calling cpu_init_crit and after function returns restores it. Signed-off-by: Lukasz Dalek <luk0104@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
* | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-01-14-84/+12
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| * | mx31/mx35/mx51/mx53/mx6: add watchdogTroy Kisky2013-01-13-84/+2
| | | | | | | | | | | | | | | | | | | | | Use a common watchdog driver for all these cpus. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * | mx6: Add workaround for ARM errataFabio Estevam2013-01-09-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add workaround for the following ARM errata: 743622 and 751472. The motivation for this change is the following kernel commit 62e4d357a (ARM: 7609/1: disable errata work-arounds which access secure registers), which removes the errata from multiplatform kernel. Since imx has been converted to multiplatform in the kernel, we need to apply such workarounds into the bootloader. Workaround code has been taken from arch/arm/mm/proc-v7.S from 3.7.1 kernel. Explanation of each erratum is provided at "Chip Errata for the i.MX 6Dual/6Quad" document available at: cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | | Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2013-01-14-25/+953
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| * | | Exynos: clock: add CLK_DIV_FSYS3 at set_mmc_clkJaehoon Chung2013-01-11-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mobile storage is used the CLK_DIV_FSYS3 value. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | Exynos: clock: support get_mmc_clk for exynosJaehoon Chung2013-01-11-0/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To get exactly clock value for mmc, support the get_mmc_clk() like set_mmc_clk(). Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | EXYNOS: Add dummy definition to fix compilation dependency on ↵Ajay Kumar2013-01-10-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_EXYNOS_MIPI_DSIM When only DP is used, we need not enable CONFIG_EXYNOS_MIPI_DSIM. But if we do not select CONFIG_EXYNOS_MIPI_DSIM, exynos_fb.c throws error saying exynos_mipi_dsi_init() not defined. So, we add dummy definition for exynos_mipi_dsi_init when CONFIG_EXYNOS_MIPI_DSIM is not defined. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | EXYNOS5: Change parent clock of FIMD to MPLLAjay Kumar2013-01-10-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With VPLL as source clock to FIMD, Exynos DP Initializaton was failing sometimes with unstable clock. Changing FIMD source to MPLL resolves this issue. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | EXYNOS5: Add support for FIMD and DPAjay Kumar2013-01-10-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add panel_info structure required by LCD driver and DP panel platdata for SMDK5250. Add GPIO configuration for LCD. Enable FIMD and DP support on SMDK5250. DP Panel size: 2560x1600. We use 16BPP resolution to get LCD console. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chomium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | EXYNOS5: Add device node for USB.Rajeshwari Shinde2013-01-08-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the device node required for USB Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | EXYNOS5: FDT: Add SPI device node dataRajeshwari Shinde2013-01-08-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SPI device node data for exynos. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
generated by cgit v1.1 at 2024-12-22 12:32:46 +0000