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* powerpc/mpc8xxx: fix workaround for errata DDR111 and DDR134York Sun2011-03-24-0/+41
| | | | | | | | The fix for errata workaround is to avoid covering physical address 0xff000000 to 0xffffffff during the implementation. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: disable rcw_en bit for non-DDR3York Sun2011-03-24-0/+2
| | | | | | | | rcw_en bit is only available for DDR3 controllers. It is a reserved bit on DDR1 and DDR2 controllers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: fix recognition of DIMMs with ECC and Address ParityYork Sun2011-03-24-1/+6
| | | | | | | | To recognize DIMMs with ECC capability by testing ECC bit only. Not to be confused by Address Parity bit. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Introduce a new linker flag LDFLAGS_FINALHaiying Wang2011-03-22-5/+5
| | | | | | | | | | | | | | | commit 8aba9dceebb14144e07d19593111ee3a999c37fc Divides variable of linker flags to LDFLAGS-u-boot and LDFLAGS breaks the usage of --gc-section to build nand_spl. We still need linker option --gc-section for every uboot image, not only the main one. LDFLAGS_FINAL passes the --gc-sections to each uboot image. To get the proper linker flags, we use LDFLAGS and LDFLAGS_FINAL to replace PLATFORM_LDFLAGS in the Makefile of each nand_spl board. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-shWolfgang Denk2011-03-21-4/+10
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| * sh: Add KEEP order to start.o sectionNobuhiro Iwamatsu2011-03-16-3/+3
| | | | | | | | | | | | | | | | The start.o section is changed by --gc-section option of ld. Of this using KEEP order, therefore, evade this problem. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: Add handling of CONFIG_SYS_NO_FLASH for board.cNobuhiro Iwamatsu2011-03-16-1/+7
| | | | | | | | | | | | | | | | | | Some board of SH does not have flash memoy. This revises it to initialize Flash when CONFIG_SYS_NO_FLASH is not defined. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | powerpc/85xx: Fix synchronization of timebase on MP bootKumar Gala2011-03-15-0/+9
|/ | | | | | | | | | | There is a small ordering issue in the master core in that we need to make sure the disabling of the timebase in the SoC is visible before we set the value to 0. We can simply just read back the value to synchronizatize the write, before we set TB to 0. Reported-by: Dan Hettena Tested-by: Dan Hettena Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc8[5/6]xx: Ensure POST word does not get resetJohn Schmoller2011-03-13-0/+32
| | | | | | | | | | | | The POST word is stored in a spare register in the PIC on MPC8[5/6]xx processors. When interrupt_init() is called, this register gets reset which resulted in all POST_RAM POSTs not being ran due to the corrupted POST word. To resolve this, store off POST word before the PIC is reset, and restore it after the PIC has been initialized. Signed-off-by: John Schmoller <jschmoller@xes-inc.com> Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Fix plat_mp_up() disabling of BPTR for CoreNet PlatformsEd Swarthout2011-03-05-2/+2
| | | | | | | | Copying directly from ECM/PQ3 is not correct for how CoreNet based platforms handle boot page translation. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registersYork Sun2011-03-05-6/+14
| | | | | | | | | The write recovery time of both registers should match. Since mode register doesn't support cycles of 9,11,13,15, we should use next higher number for both registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ARM: Update mach-typesSandeep Paulraj2011-02-21-15/+1276
| | | | | | | This commit updates the mach-types based on the latest in linus's head Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* arm1136 relocation: Fix calculation of board_init_rFabio Estevam2011-02-21-1/+1
| | | | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* arm1136: Fix NAND bootFabio Estevam2011-02-21-12/+4
| | | | | | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com> Tested-by: Magnus Lilja <lilja.magnus@gmail.com>
* arm: get_sp() should always be compiledPo-Yu Chuang2011-02-21-3/+1
| | | | | | | | | | | | get_sp() was incorrectly excluded if none of CONFIG_SETUP_MEMORY_TAGS CONFIG_CMDLINE_TAG CONFIG_INITRD_TAG CONFIG_SERIAL_TAG CONFIG_REVISION_TAG were defined. Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
* mvmfp: add MFP configuration support for PANTHEONLei Wen2011-02-21-0/+41
| | | | | | | This patch adds the Multiple Function Pin configuration support for Marvell PANTHEON SoCs Signed-off-by: Lei Wen <leiwen@marvell.com>
* ARM: Add Support for Marvell Pantheon Familiy SoCsLei Wen2011-02-21-0/+641
| | | | | | | | | | | | | Pantheon Family processors are highly integrated SoCs based on Sheeva_88SV331x-v5 PJ1 cpu core. Ref: http://www.marvell.com/products/processors/communications/marvell_pantheon_910_920_pb.pdf SoC versions Supported: 1) PANTHEON920 (TD) 2) PANTHEON910 (TTC) Signed-off-by: Lei Wen <leiwen@marvell.com>
* mv: seperate kirkwood and armada from common settingLei Wen2011-02-21-0/+189
| | | | | | | | | | | | | Since there are lots of difference between kirkwood and armada series, it is better to seperate them but still keep the most common file shared by all marvell platform in the mv-common configure file. This patch move the kirkwood only driver definitoin in mv-common to the <soc_name>/config.h. This patch is tested with compilation for armada100 and guruplug. Signed-off-by: Lei Wen <leiwen@marvell.com>
* ARM: fix write*() I/O accessorsWolfgang Denk2011-02-21-3/+3
| | | | | | | | | | | | | | | | | | | Commit 3c0659b "ARM: Avoid compiler optimization for readb, writeb and friends." introduced I/O accessors with memory barriers. Unfortunately the new write*() accessors introduced a bug: The problem is that the argument "v" gets evaluated twice. This breaks code like used here (from "drivers/net/dnet.c"): for (i = 0; i < wrsz; i++) writel(*bufp++, &dnet->regs->TX_DATA_FIFO); Use auxiliary variables to avoid such problems. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Albert Aribaud <albert.aribaud@free.fr> Cc: Alexander Holler <holler@ahsoftware.de> Cc: Dirk Behme <dirk.behme@googlemail.com>
* arm relocation: Fix calculation of board_init_rAlexander Stein2011-02-21-1/+1
| | | | Signed-off-by: Alexander Stein <alexander.stein@informatik.tu-chemnitz.de>
* arm: Tegra2: Add basic NVIDIA Tegra2 SoC supportTom Warren2011-02-21-0/+861
| | | | Signed-off-by: Tom Warren <twarren@nvidia.com>
* microblaze: Fix msr handling in interrupt_handlerMichal Simek2011-02-15-18/+1
| | | | | | | Fix ancient code which worked with MSR in a bad way. Use rtid instruction which enable IRQs and jump. Signed-off-by: Michal Simek <monstr@monstr.eu>
* microblaze: Fix systems with MSR=0Michal Simek2011-02-15-1/+1
| | | | | | | | u-boot BSP generates XILINX_USE_MSR_INSTR macro even for system with MSR=0. That's why explicitly check that MSR=1. Signed-off-by: Michal Simek <monstr@monstr.eu>
* sc520: Release CAR and enable cachingGraeme Russ2011-02-12-5/+11
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* x86: Convert board_init_f to use an init_sequenceGraeme Russ2011-02-12-41/+29
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* x86: Rearrange function calls in board_init_fGraeme Russ2011-02-12-8/+8
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* x86: Split board_init_f() into init_fnc_t compatible functionsGraeme Russ2011-02-12-49/+74
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* x86: Fix incorrect usage of relocation offsetGraeme Russ2011-02-12-6/+6
| | | | | x86 has always used relocation offset in the opposite sense to the ELF standard - Fix this
* x86: Move console initialisation into board_init_fGraeme Russ2011-02-12-3/+12
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* x86: Move test for cold boot into init functionsGraeme Russ2011-02-12-13/+11
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* x86: Move call to dram_init_f into board_init_fGraeme Russ2011-02-12-3/+4
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* x86: Defer setup of final stackGraeme Russ2011-02-12-17/+33
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* sc520: Move RAM sizing code from asm to CGraeme Russ2011-02-12-755/+610
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* x86: Use Cache-As-RAM for initial stackGraeme Russ2011-02-12-21/+115
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* x86: Move initial gd to fixed locationGraeme Russ2011-02-12-19/+36
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* sc520: Remove printf calls from cpu_init_fGraeme Russ2011-02-12-2/+0
| | | | | In later patches, cpu_init_f will be called before console has been initialised and printf will not be legitimately available
* sc520: Move board specific settings to board init functionGraeme Russ2011-02-12-19/+0
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* sc520: Define MMCR address in include fileGraeme Russ2011-02-12-36/+51
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* x86: Make cpu init functions weakGraeme Russ2011-02-12-10/+17
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* x86: Call early_board_init when warm bootingGraeme Russ2011-02-12-5/+5
| | | | | | | | | | early_board_init has been skipped to avoid SDRAM corruption in the case that a fully relocatable image has been loaded into SDRAM and is being executed from SDRAM. x86 is being aligned with other architectures (ARM and PPC in particlar) and will be using Cache-As-RAM to run a C environment from Flash (or SRAM if you have some). early_board_init may be needed to assist in the setup of Cache-As-RAM and the early C environment
* x86: Add processor flags header from linuxGraeme Russ2011-02-12-10/+121
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* x86: Move Global Descriptor Table defines to processor.hGraeme Russ2011-02-12-10/+7
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* x86: Add stack dump to register dumpGraeme Russ2011-02-12-0/+16
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* x86: Fix mangled umlautsGraeme Russ2011-02-12-2/+2
| | | | | git mergetool has a nasty habit of mangling umlats - fix ones that have been missed in previous submissions
* sc520: Sort MakefileGraeme Russ2011-02-12-1/+1
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* x86: Parametize values used in linker scriptGraeme Russ2011-02-12-20/+19
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* x86: Align config.mk and linker scripts with other archesGraeme Russ2011-02-12-8/+114
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* x86: Fix definition of global_data struct for asm-offsets.cGraeme Russ2011-02-12-1/+1
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* powerpc/8xxx: Add additional cycle to write-to-read turnaound for DDR3York Sun2011-02-10-1/+4
| | | | | | | | | When DDR data rate is higher than 1200MT/s or controller interleaving is enabled, additional cycle for write-to-read turnaround is needed to satisfy dynamic ODT timing. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'next' of git://git.denx.de/u-boot-niosWolfgang Denk2011-02-09-1/+13
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