summaryrefslogtreecommitdiff
path: root/arch
Commit message (Collapse)AuthorAgeLines
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2010-06-17-190/+2415
|\
| * AM35x: Add support for EMIF4Vaibhav Hiremath2010-06-08-0/+273
| | | | | | | | | | | | | | | | | | This patch adds support for the EMIF4 interface available in the AM35x processors. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Sanjeev Premi <premi@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * omap3: Consolidate SDRC related operationsVaibhav Hiremath2010-06-08-168/+220
| | | | | | | | | | | | | | | | | | | | | | Consolidated SDRC related functions into one file - sdrc.c And also replaced sdrc_init with generic memory init function (mem_init), this generalization of omap memory setup is necessary to support the new emif4 interface introduced in AM3517. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * omap3: Calculate CS1 size only when SDRC isVaibhav Hiremath2010-06-08-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | initialized for CS1 From: Vaibhav Hiremath <hvaibhav@ti.com> The patch makes sure that size for SDRC CS1 gets calculated only when the CS1 SDRC is initialized. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * ARM1176: TI: TNETV107X soc initial supportCyril Chemparathy2010-06-08-0/+1872
| | | | | | | | | | | | | | | | | | TNETV107X is a Texas Instruments SoC based on an ARM1176 core, and with a bunch on on-chip integrated peripherals. This is an initial commit with basic functionality, more commits with drivers, etc. to follow. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * ARM1176: Coexist with other ARM1176 platformsCyril Chemparathy2010-06-08-21/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current ARM1176 CPU specific code is too specific to the SMDK6400 architecture. The following changes were necessary prerequisites for the addition of other SoCs based on ARM1176. Existing board's (SMDK6400) configuration has been modified to keep behavior unchanged despite these changes. 1. Peripheral port remap configurability The earlier code had hardcoded remap values specific to s3c64xx in start.S. This change makes the peripheral port remap addresses and sizes configurable. 2. U-Boot code relocation support Most architectures allow u-boot code to run initially at a different address (possibly in NOR) and then get relocated to its final resting place in RAM. Added support for this capability in ARM1176 architecture. 3. Disable TCM if necessary If a ROM based bootloader happened to have initialized TCM, we disable it here to keep things sane. 4. Remove unnecessary SoC specific includes ARM1176 code does not really need this SoC specific include. The presence of this include prevents builds on other ARM1176 archs. 5. Modified virt-to-phys conversion during MMU disable The original MMU disable code masks out too many bits from the load address when it tries to figure out the physical address of the jump target label. Consequently, it ends up branching to the wrong address after disabling the MMU. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * ARM1136: Fix cache_flush() error and correct cpu_init_crit() commentsGeorge G. Davis2010-06-01-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM1136 cache_flush() function uses the "mcr p15, 0, rn, c7, c7, 0" instruction which means "Invalidate Both Caches" when in fact the intent is to clean and invalidate all caches. So add an "mcr p15, 0, %0, c7, c10, 0" instruction to "Clean Entire Data Cache" prior to the "Invalidate Both Caches" instruction to insure that memory is consistent with any dirty cache lines. Also fix a couple of "flush v*" comments in ARM1136 cpu_init_crit() so that they correctly describe the actual ARM1136 CP15 C7 Cache Operations used. Signed-off-by: George G. Davis <gdavis@mvista.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2010-05-30-3/+6
|\ \
| * | fsl/85xx: add clkdvdr and pmuxcr2 to global utilities structure definitionTimur Tabi2010-05-30-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | Add the 'clkdvdr' and 'pmuxcr2' registers to the 85xx definition of struct ccsr_gur. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2010-05-30-8/+1165
|\ \ \ | |/ / |/| / | |/
| * ARM Update mach-typesTom2010-05-28-6/+500
| | | | | | | | | | | | | | | | | | | | Fetched from http://www.arm.linux.org.uk/developer/machines/download.php And built with repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm commit 3defb2476166445982a90c12d33f8947e75476c4 Signed-off-by: Tom <Tom@bumblecow.com>
| * ARM Update mach-typesTom2010-05-28-2/+665
| | | | | | | | | | | | | | | | | | | | Fetched from http://www.arm.linux.org.uk/developer/machines/download.php And built with repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm commit 257dab81413b31b8648becfe11586b3a41e5c29a Signed-off-by: Tom <Tom@bumblecow.com>
* | Merge branch 'next' of git://git.denx.de/u-boot-niosWolfgang Denk2010-05-28-3588/+911
|\ \
| * | nios: remove nios-32 archThomas Chou2010-05-28-3403/+0
| | | | | | | | | | | | | | | | | | The nios-32 arch is obsolete and broken. So it is removed. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
| * | nios2: allow STANDALONE_LOAD_ADDR overridingThomas Chou2010-05-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows users to override default STANDALONE_LOAD_ADDR. The gcclibdir path was duplicated in the standalone Makefile and can be removed. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
| * | nios2: fix div64 issue for gcc4Thomas Chou2010-05-28-175/+856
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the run-time error on div64 when built with gcc4, which was reported by jhwu0625 on nios forum. It merges math support from libgcc of gcc4. This patch is copied from nios2-linux. It works with both gcc3 and gcc4. The old mult.c, divmod.c and math.h are removed. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
| * | nios2: fix r15 issue for gcc4Thomas Chou2010-05-28-9/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "-ffixed-r15" option doesn't work well for gcc4. Since we don't use gp for small data with option "-G0", we can use gp as global data pointer. This allows compiler to use r15. It is necessary for gcc4 to work properly. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
| * | nios2: add gpio supportThomas Chou2010-05-28-0/+52
| |/ | | | | | | | | | | | | | | | | | | | | | | | | This patch adds driver for a trivial gpio core, which is described in http://nioswiki.com/GPIO. It is used for gpio led and nand flash interface in u-boot. When CONFIG_SYS_GPIO_BASE is not defined, board may provide its own driver. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Tested-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
* | add CONFIG_SYS_FEC_FULL_MII for MCF5445xWolfgang Wegner2010-05-28-2/+11
| | | | | | | | | | | | | | This patch adds support for full MII interface on MCF5445x (in contrast to RMII as used on the evaluation boards). Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de>
* | add CONFIG_SYS_FEC_NO_SHARED_PHY for MCF5445xWolfgang Wegner2010-05-28-0/+11
| | | | | | | | | | | | | | | | This patch adds the possibility to handle seperate PHYs to MCF5445x. Naming is chosen to resemble the contrary CONFIG_FEC_SHARED_PHY in the linux kernel. Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de>
* | add missing PCS3 for MCF5445xWolfgang Wegner2010-05-28-0/+8
|/ | | | | | | This patch adds the code for handling PCS3 (DSPI chip select 3) in cpu_init.c and m5445x.h Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de>
* Coding style cleanup, update CHANGELOG.Wolfgang Denk2010-05-26-3/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2010-05-26-20/+20
|\
| * mpc83xx: don't shift pre-shifted ACR, SPCR, SCCR bitfield masks in cpu_init.cKim Phillips2010-05-21-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit c7190f028fa950d4d36b6d0b4bb3fc72602ec54c "mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields" incorrectly shifted <register>_<bitfield> (e.g. ACR_PIPE_DEP) values that were preshifted by their definition in mpc83xx.h. this patch removes the unnecessary shifting for the newly utilized mask values in cpu_init.c, and prevents seemingly unrelated symptoms such as an mpc8379erdb board from locking up whilst performing a networking operation, e.g. a tftp. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * Fixed two typos in arch/powerpc/cpu/mpc83xx/start.S.Horst Kronstorfer2010-05-21-2/+2
| | | | | | | | | | Signed-off-by: Horst Kronstorfer <hkronsto@frequentis.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | Convert Makefiles from COBJS-${} to COBJS-$()Kumar Gala2010-05-26-5/+5
| | | | | | | | | | | | Match style we use almost everywhere else Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/bootcount: Fix endianness problemMichael Weiss2010-05-26-2/+4
| | | | | | | | | | | | | | For CONFIG_SYS_BOOTCOUNT_SINGLEWORD the code had an endianness problem. Signed-off-by: Michael Weiss <michael.weiss@ifm.com> Signed-off-by: Detlev Zundel <dzu@denx.de>
* | a320evb: fix udelay / __udelay confusionWolfgang Denk2010-05-21-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Fix the following compiler problems: arch/arm/cpu/arm920t/a320/liba320.a(timer.o): In function `udelay': /home/wd/git/u-boot/work/arch/arm/cpu/arm920t/a320/timer.c:160: multiple definition of `udelay' lib/libgeneric.a(time.o):/home/wd/git/u-boot/work/lib/time.c:34: first defined here lib/libgeneric.a(time.o): In function `udelay': time.c:(.text+0x1c): undefined reference to `__udelay' Signed-off-by: Wolfgang Denk <wd@denx.de>
* | ARM: */timer.c: fix spelling and vertical alignmentWolfgang Denk2010-05-21-18/+18
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-imxWolfgang Denk2010-05-21-1/+1
|\ \ | |/ |/|
| * MX51: Fix MX51 CPU detect messageFabio Estevam2010-05-05-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix MX51 CPU detect message. Original string was: CPU: Freescale i.MX51 family 3.0V at 800 MHz which can be misinterpreted as 3.0 Volts instead of the silicon revision. ,change it to: CPU: Freescale i.MX51 family rev3.0 at 800 MHz Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2010-05-17-0/+2
|\ \
| * | mpc83xx: fix NAND bootstrap too big errorKim Phillips2010-05-17-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 167cdad1372917bc11c636c359aad02625291fa9 "SERIAL: Enable port-mapped access" inadvertently broke 83xx nand boards by converting NS16550_init to use io accessors, which expanded the size of the generated code. this patch fixes the problem by removing icache functions from the nand builds, which somewhat follows commit 1a2e203b31d33fb720f2cf1033b241ad36ab405a "mpc83xx: turn on icache in core initialization to improve u-boot boot time" Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2010-05-17-33/+129
|\ \ \ | |/ / |/| |
| * | Enabled support for Rev 1.3 SPD for DDR2 DIMMsYork Sun2010-05-12-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPD has minor change from Rev 1.2 to 1.3. This patch enables Rev 1.3. The difference has ben examined and the code is compatible. Speed bins is not verified on hardware for CL7 at this moment. This patch also enables SPD Rev 1.x where x is up to "F". According to SPD spec, the lower nibble is optionally used to determine which additinal bytes or attribute bits have been defined. Software can safely use defaults. However, the upper nibble should always be checked. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | 85xx/fsl-sata: Use is_serdes_configured() to determine if SATA is enabledKumar Gala2010-05-12-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the MPC85xx platform if we have SATA its connected on SERDES. Determing if SATA is enabled via sata_initialize should not be board specific and thus we move it out of the MPC8536DS board code. Additionally, now that we have is_serdes_configured() we can determine if the given SATA port is enabled and error out if its not in the driver. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | 85xx/mpc8536ds: Use is_serdes_configured() to determine of PCIe enabledKumar Gala2010-05-12-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new is_serdes_configured covers a broader range of devices than the PCI specific code. Use it instead as we convert away from the is_fsl_pci_cfg() code. Additionally move to setting LAWs for PCI based on if its configured. Also updated PCI FDT fixup code to remove PCI controllers from dtb if they are configured. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | 85xx: Add is_serdes_configured() support to MPC8536 SERDESKumar Gala2010-05-12-18/+114
| | | | | | | | | | | | | | | | | | | | | | | | Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | ARM: add __aeabi_unwind_cpp_pr0() function to avoid linker complaintsWolfgang Denk2010-05-15-0/+5
|/ / | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> Tested-by: Thomas Weber <weber@corscience.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2010-05-09-0/+1
|\ \
| * | mpc83xx: Add UPMA configuration to SIMPC8313Ron Madrid2010-05-07-0/+1
| | | | | | | | | | | | | | | | | | | | | Added UPM array table, upmconfig, and Local Bus configuration support for SIMPC8313 Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | | update include/asm/ gitignore after moveMike Frysinger2010-05-07-0/+2
| | | | | | | | | | | | | | | | | | | | | With the cpu include paths moved, the gitignore paths need updating. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Tested-by: Tom Rix <tom@bumblecow.com>
* | | powerpc: Consolidate bootcount_{store|load} for PowerPCStefan Roese2010-05-06-124/+91
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch consolidates bootcount_{store|load} for PowerPC by implementing a common version in arch/powerpc/lib/bootcount.c. This code is now used by all PowerPC variants that currently have these functions implemented. The functions now use the proper IO-accessor functions to read/write the values. This code also supports two different bootcount versions: a) Use 2 separate words (2 * 32bit) to store the bootcounter b) Use only 1 word (2 * 16bit) to store the bootcounter Version b) was already used by MPC5xxx. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> for 83xx parts Cc: Michael Zaidman <michael.zaidman@gmail.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Kim Phillips <kim.phillips@freescale.com> Cc: Anatolij Gustschin <agust@denx.de>
* | sc520: Fix minor DRAM Controller Setup bugGraeme Russ2010-05-06-1/+1
| | | | | | | | Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | sc520: Update to new AMD CopyrightGraeme Russ2010-05-06-40/+77
| | | | | | | | | | | | | | AMD recently changed the licensing of the RAM sizing code to the GPLv2 (or at your option any later version) Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | sc520: Board Specific PCI InitGraeme Russ2010-05-06-37/+3
| | | | | | | | Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | sc520: Move PCI defines to PCI include fileGraeme Russ2010-05-06-29/+29
| | | | | | | | Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | sc520: Allow boards to override udelayGraeme Russ2010-05-06-0/+5
| | | | | | | | | | | | | | If the board has a high precision mico-second timer, it maked sense to use it instead of the on-chip one Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | x86: Fix support for booting bzImageGraeme Russ2010-05-06-32/+424
| | | | | | | | | | | | | | | | | | | | | | Add support for newer (up to 2.6.33) kernels Add zboot command which takes the address of a bzImage as its first argument and (optionally) the size of the bzImage as the second argument (the second argument is needed for older kernels which do not include the bzImage size in the header) Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | x86: Provide weak PC/AT compatibility setup functionGraeme Russ2010-05-06-0/+9
| | | | | | | | | | | | | | | | | | | | It is possibly to setup x86 boards to use non-PC/AT configurations. For example, the sc520 is an x86 CPU with PC/AT and non-PC/AT peripherals. This function allows the board to set itself up for maximum PC/AT compatibility just before booting the Linux kernel (the Linux kernel 'just works' if everything is PC/AT compliant) Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
generated by cgit v1.1 at 2024-12-23 04:59:39 +0000