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* ENGR00315894-59 iMX6SX: Add RDC mappings of masters and peripheralsYe.Li2014-06-17-0/+159
| | | | | | | Add the definitions for the RDC mappings on iMX6SX and include this file to "imx-rdc.h" Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-58 RDC: Add an iMX platform driver for RDC-SEMAYe.Li2014-06-17-0/+319
| | | | | | | | | | | | | | The RDC driver provides interfaces for setting peripherals and masters at BSP initialization, before using the peripherals driver. Another interfaces for lock/unlock RDC semaphore and permission check. The driver assumes boot CPU which runs u-boot is in Domain 0 (default setting on boot). Users should not set it to other domains. The peripherals ID and masters ID may change on different chip, each should provide definitions of the IDs and be included in "imx-rdc.h". Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-57 iMX6SX: Add M4 boot support at soc levelYe.Li2014-06-17-0/+30
| | | | | | | | | Implement the override function "arch_auxiliary_core_up" to boot Cortex-M4 by executing command "bootaux". The parameter "boot_private_data" points to fields where stores the stack address and PC address for M4 to run. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-55 iMX6SX: add debug monitor supportYe.Li2014-06-17-0/+29
| | | | | | | | | | | Debug monitor will print out last failed AXI access info when system reboot is caused by AXI access failure, only works when debug monitor is enabled. Enable this module on i.MX6SX. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-54 iMX6SX/SL: Modify SOC to support two ENETYe.Li2014-06-17-5/+96
| | | | | | | | | | | | | | | | | | | | | iMX6SX has different enet system clocks with iMX6SL, and has two ENET controllers. So update clocks and soc APIs accordingly to support this features. 1. Modify the clock API "enable_enet_clock" to enable enet system clock for enet controllers. 2. Enet RGMII TX clock source may come from external or internal PLL. By default, use the external phy CLK_25M output as TX clock source. When using internal PLL as source, the function enable_fec_anatop_clock must be called to enable clock for each enet controller. 3. Modify the MAC address function "imx_get_mac_from_fuse" to get either ENET MAC address. 4. Add configuration "CONFIG_FEC_MXC_25M_REF_CLK" to enable ENET 25Mhz reference clock. 5. Modify imx6slevk BSP to fit the new APIs. Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-51 iMX6SX: Add QuadSPI clock enable functionYe.Li2014-06-17-0/+45
| | | | | | | Enable the clock for QuadSPI controllers. Must be called at initialization. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-48 iMX6SX: Add iMX6SX SoC supportYe.Li2014-06-17-17/+2149
| | | | | | | | | | | Adding clks, pinmux, memory map, etc for iMX6SoloX. Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-44 imx6:USB: Update EHCI driver for OTG lines compatibilityYe.Li2014-06-17-12/+3
| | | | | | | | | | | To be compatible with more USB otg lines which has micro port B to connect imx6 OTG port when imx6 working at host mode, remove the checking for the OTG ID with the init type. Only use the init type for the power and controller initialization. Use same EHCI register base address for various imx6 platform. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-35 i.mx6: Fix issue in HAB clock settingYe.Li2014-06-17-9/+9
| | | | | | Should use the address of one register when calling "readl"/"writel". Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-19 iMX6 Disable the L2 before chaning the PL310 latencyYe.Li2014-06-17-0/+3
| | | | | | | | | | | The Latency parameters of PL310 Tag RAM latency control register and Data RAM Latency control register are set in L2 cache enable. Setting these registers must have PL310 not enabled. But when using Plugin mode boot, the PL310 is enabled by bootrom. Thus, disable the PL310 before this setting. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-11 i.mx6:shutdown vddpu and pcie phy to save powerYe.Li2014-06-17-0/+31
| | | | | | | | shutdown vddpu and pcie phy to save power Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315499-21 HDMI: splash screen function enhancementNitin Garg2014-06-13-1/+11
| | | | | | | | | | | | -Change HDMI video mode to VGA. -Add pixel clock fraction part setting in IPU driver, fix video mode timing issue. -Add overflow state clear workaround, fix kernel hang in HDMI driver issue. -Correct IPU clock to 264MHz. Signed-off-by: Sandor Yu <R01008@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR00315499-17 ARM:imx6sl:evk Add SPI NOR flash boot and access supportNitin Garg2014-06-13-0/+5
| | | | | | | | | | | Add BSP codes to support SPI NOR flash read, write and erase by using "sf" command. In addition, add a new configuration "mx6slevk_spinor" for building the uboot that can be booted from SPI NOR flash and stored the environments variables in it. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR00315499-15 ARM:imx6sl:evk Add USB HOST supportNitin Garg2014-06-13-1/+4
| | | | | | | | Enable the USB EHCI for the imx6slevk board. Add VBUS control pin settings and related BSP codes. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR00315499-12: ARM: MSL: add i2c0 support for imx6sl evkNitin Garg2014-06-13-0/+5
| | | | | | | | - Add i2c0 support for imx6sl evk platform. - Read pmic device ID and revsion ID. Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR00315499-11 ARM:imx6 Change static environment SD/MMC storage to dynamicNitin Garg2014-06-13-0/+22
| | | | | | | | | | | | | | | | | | | imx6 boards (sabresd, sabreauto, arm2 and slevk) have multiple SD/MMC ports to boot. But current uboot hard code the SD/MMC port for environment variables storage. So if customer changes a port without modifying the configuration "CONFIG_SYS_MMC_ENV_DEV", error will issue at saving and loading environment. Implement a mechanism to detect SD/MMC port from SRC SMBR register, and override the default "mmc_get_env_devno". The "board_late_mmc_env_init" is used to set "mmcdev" when booting from SD/MMC port. Finally after booting from SD/MMC, the environment storage device and "mmcdev" are both set to current SD/MMC port. Customers don't need to re-build the image if booting from different SD/MMC port. This patch also adds SD1 and SD3 support to imx6slevk BSP, and adds support for sabreauto SD1 slot on base board. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR00315499-10 ARM:imx6:sabresd/sabreauto Add android fastboot supportingNitin Garg2014-06-13-0/+128
| | | | | | | | | | | | | | | | | | Support android features: fastboot, booti command and recovery for sabresd SD, sabresd eMMC, sabreauto SD, sabreauto NAND. For all booting media (SD, eMMC, NAND), inherits the partitions layout from v2009.08. Fastboot will detect the booting media to replace hardcoding fastboot device. SATA is not supported. FDT is supported to use the "unused" fields in bootimg header which requires the FDT to be combined into the boot.img. For non-FDT boot.img, the "unused" fields should left to NULL and is compatible to boot. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR00315499-9: ARM:iMX6SL EVK: Add keyboard supportNitin Garg2014-05-27-0/+49
| | | | | | | i.MX6sl evk has keyboards on the board, so add mxc_keyb driver to support key press checking. Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR00315499-8 Auto check if boot from usbNitin Garg2014-05-27-0/+5
| | | | | | | | If boot from usb, reset environment to default value. Auto apply mfgtools setting and boot mfgtools kernel. Signed-off-by: Frank Li <Frank.li@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR00315499-7 Add EPDC splash screen for MX 6DL SabreSD and 6SL EVKNitin Garg2014-05-27-0/+48
| | | | | | | | | | | | | | | | | Add EPDC splash screen feature for MX6SL EVK, and MX6DL SABRESD board. - Currently, splash screen consists of a simple black border around a white screen. Done this way to save in memory footprint. - EPDC splash screen is disabled by default in the config file for MX6DL_SABRESD and MX6SL_EVK. If left enabled, the U-Boot image will not boot correctly (hang), since some additional content on the boot device (waveform file) is required for EPDC splash to work correctly. Please refer to Linux Reference Manual for how to flash WAVEFORM file. Signed-off-by: Robby Cai <R63905@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR00315499-6 ARM:imx6: Add USB gadget driver imx_udc to support Android ↵Nitin Garg2014-05-27-0/+562
| | | | | | | | | | | | | | fastboot Android fastboot leans on the USB gadget driver to communicate with host. Porting the imx_udc driver from v2009.08 with two changes: adding resource/memory release APIs and replacing the uncached memory with cache flush&invalidate operations. Pins and Clocks initialization are added to support boards: mx6qdlsabresd, mx6qdlsabreauto, mx6slevk Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR00315499-5: Support i.MX6 1.2GHz via LDO bypassNitin Garg2014-05-27-6/+90
| | | | | | | | Add check for 1.2GHz core speed. If Speed grading fuse is for 1.2GHz, enable LDO bypass and setup PMIC voltages. LDO bypass is dependent on the flatten device tree file. Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR00315499-4: Add support for i.MX6 Plugin imagesNitin Garg2014-05-27-0/+127
| | | | | | | Support generating plugin images. Make sure not to effect the size of DCD images. Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR00315499-3: Support i.MX6 HAB authentication of kernel imageNitin Garg2014-05-27-13/+309
| | | | | | | Support HAB authentication of kernel or secondary images via bootm or hab_auth_img u-boot command. Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR00315499-1: Add i.MX6 CPU temperature sensor supportNitin Garg2014-05-27-4/+693
| | | | | | Support CPU temperature sensors on i.MX6 SoC. Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2014-04-08-367/+299
|\ | | | | | | | | | | | | | | Conflicts: arch/arm/cpu/arm926ejs/mxs/Makefile include/configs/trats.h include/configs/trats2.h include/mmc.h
| * mmc:eSDHC: Workaround for data timeout issue on Txxx SoCHaijun.Zhang2014-04-02-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. The Data timeout counter value in eSDHC_SYSCTL register is not working as it should be, so add quirks to enable this workaround to fix it to the max value 0xE. 2. Add CONFIG_SYS_FSL_ERRATUM_ESDHC111 to enable its workaround. * Update of patch for change mmc interface by Pantelis Antoniou <panto@antoniou-consulting.com> Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
| * tegra: fix Makefile to pass per-file CFLAGSMasahiro Yamada2014-03-31-1/+1
| | | | | | | | | | | | | | | | | | | | | | Since Kbuild was introduced, warmboot_avp.o has been compiled without -march=armv4t. Makefile should be adjusted to pass a per-file option. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Tom Warren <twarren@nvidia.com>
| * cpu: exynos4: add ace sha base addressPrzemyslaw Marczak2014-03-28-4/+4
| | | | | | | | | | Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com>
| * spl: Fix guardian macros in spl.hMarek Vasut2014-03-28-6/+6
| | | | | | | | | | | | | | | | | | Fix the macros guarding the spl.h header for various platforms. Due to a typo and a propagation of it, the macros went out-of-sync with their ifdef check, so fix this. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com>
| * kbuild: move asm-offsets.c from SoC directory to arch/$(ARCH)/libMasahiro Yamada2014-03-28-354/+276
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot has supported two kinds of asm-offsets.h. One is generic for all architectures and its source is located at ./lib/asm-offsets.c. The other is SoC specific and its source is under SoC directory. The problem here is that only boards with SoC directory can use the asm-offsets infrastructure. Putting asm-offsets.c right under CPU directory does not work. Now a new demand is coming. PowerPC folks want to use asm-offsets. But no PowerPC boards have SoC directory. It seems inconsistent that some boards add asm-offsets.c to SoC directoreis and some to CPU directories. It looks more reasonable to put asm-offsets.c under arch/$(ARCH)/lib. This commit merges asm-offsets.c under SoC directories into arch/$(ARCH)/lib/asm-offsets.c. By the way, I doubt the necessity of some entries in asm-offsets.c. I am leaving refactoring to the board maintainers. Please check "TODO" in the comment blocks in arch/{arm,nds32}/lib/asm-offsets.c. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Yuantian Tang <Yuantian.Tang@freescale.com>
| * kbuild: Rename UIMAGE to MKIMAGEMarek Vasut2014-03-28-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot uses the 'mkimage' tool to produce various image types, not only uImage image type. Rename the invocation name from UIMAGE to MKIMAGE. The following command was used to do the replacement: git grep 'quiet_cmd_mkimage.* = UIMAGE' | cut -d : -f 1 | \ xargs -i sed -i "s@\(quiet_cmd_mkimage\)\(.*\) = UIMAGE @\1\2 = MKIMAGE@" {} Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * mmc: Split mmc struct, rework mmc initialization (v2)Pantelis Antoniou2014-03-24-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The way that struct mmc was implemented was a bit of a mess; configuration and internal state all jumbled up in a single structure. On top of that the way initialization is done with mmc_register leads to a lot of duplicated code in drivers. Typically the initialization got something like this in every driver. struct mmc *mmc = malloc(sizeof(struct mmc)); memset(mmc, 0, sizeof(struct mmc); /* fill in fields of mmc struct */ /* store private data pointer */ mmc_register(mmc); By using the new mmc_create call one just passes an mmc config struct and an optional private data pointer like this: struct mmc = mmc_create(&cfg, priv); All in tree drivers have been updated to the new form, and expect mmc_register to go away before long. Changes since v1: * Use calloc instead of manually calling memset. * Mark mmc_register as deprecated. Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* | arm64 patch: gicv3 supportDavid Feng2014-04-08-114/+290
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add gicv3 support to uboot armv8 platform. Changes for v2: - rename arm/cpu/armv8/gic.S with arm/lib/gic_64.S - move smp_kick_all_cpus() from gic.S to start.S, it would be implementation dependent. - Each core initialize it's own ReDistributor instead of master initializeing all ReDistributors. This is advised by arnab.basu <arnab.basu@freescale.com>. Signed-off-by: David Feng <fenghua@phytium.com.cn>
* | bootstage: arm: fix fdt stashing codeMela Custodio2014-04-07-2/+1
| | | | | | | | | | | | The conditional is using a variable that is not defined. Signed-off-by: Rommel G Custodio <sessyargc+u-boot@gmail.com>
* | ARMv8: fix bug for flush data cache by set/wayLeo Yan2014-04-07-3/+1
| | | | | | | | | | | | | | | | | | When flush the d$ with set/way instruction, it need calculate the way's offset = log2(Associativity); but in current uboot's code, it use below formula to calculate the offset: log2(Associativity * 2 - 1), so finally it cannot flush data cache properly. Signed-off-by: Leo Yan <leoy@marvell.com>
* | armv8: Flush dcache before switching to EL2York Sun2014-04-07-0/+1
| | | | | | | | | | | | | | | | | | | | For ARMv8, U-boot has been running at EL3 with cache and MMU enabled. Without proper setup for EL2, cache and MMU are both disabled (out of reset). Before switching, we need to flush the dcache to make sure the data is in the main memory. Signed-off-by: York Sun <yorksun@freescale.com> Acked-by: David.Feng <fenghua@phytium.com.cn>
* | arm: vf610: add enet1 supportMarcel Ziswiler2014-04-07-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch contains several changes required for second Ethernet (enet1/RMII1) port on vf610 - ANADIG PLL5 control definitions required for Ethernet RMII1 clock - Secondary Ethernet (enet1) MAC RMII1 base address definition - RMII1 iomux definitions - VF610_PAD_PTA6__RMII0_CLKOUT iomux definition required for internal (e.g. crystal-less) Ethernet clocking. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> [stefan@agner.ch: regrouped patch] Signed-off-by: Stefan Agner <stefan@agner.ch>
* | arm: vf610: add uart0 clock/iomux definitionsMarcel Ziswiler2014-04-07-0/+3
| | | | | | | | | | | | | | | | | | Add CCM_CCGR0_UART0_CTRL_MASK clock definition and add TX/RX iomux definitions for UART0 (aka. SCI0). Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> [stefan@agner.ch: regrouped patch] Signed-off-by: Stefan Agner <stefan@agner.ch>
* | arm: vf610: fix anadig register structMarcel Ziswiler2014-04-07-25/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The anadig_reg structure started at the wrong offset (fixed by adding reserved_0x000[4]), was missing some reserved field required for alignment purpose (reserved_0x094[3] between pll4_denom and pll6_ctrl) and further contained a too short reserved field causing further miss- alignment (reserved_0x0C4[7]). Also, rename all the reserved fields and using a memory offset based scheme for. Discovered and tested by temporarily putting the following debug instrumentation into board_init(): struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR; printf("&anadig->pll3_ctrl=0x%p\n", &anadig->pll3_ctrl); printf("&anadig->pll5_ctrl=0x%p\n", &anadig->pll5_ctrl); Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> [stefan@agner.ch: regrouped patch] Signed-off-by: Stefan Agner <stefan@agner.ch>
* | build:arm: Remove setting of CROSS_COMPILE environment variableŁukasz Majewski2014-04-07-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After Kbuild introduction, the CROSS_COMPILE environment variable has been set to some default value (prefix arm-linux-). This shall be removed since it breaks building u-boot for native arm target (like qemu ARM). Moreover not all compilers have arm-linux- prefix. Additionally the u-boot cross compiles with CROSS_COMPILE= set explicitly- e.g.: CROSS_COMPILE=/ .... /arm-v7a-linux-gnueabi- make Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-04-07-1/+6
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| * | ARM: Add workaround for Cortex-A9 errata 761320Nitin Garg2014-04-07-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Full cache line writes to the same memory region from at least two processors might deadlock the processor. Exists on r1, r2, r3 revisions. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | ARM: Add workaround for Cortex-A9 errata 794072Nitin Garg2014-04-07-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | A short loop including a DMB instruction might cause a denial of service on another processor which executes a CP15 broadcast operation. Exists on r1, r2, r3, r4 revisions. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
* | | armv8/cache: Change cache invalidate and flush functionYork Sun2014-04-07-20/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When SoC first boots up, we should invalidate the cache but not flush it. We can use the same function for invalid and flush mostly, with a wrapper. Invalidating large cache can ben slow on emulator, so we postpone doing so until I-cache is enabled, and before enabling D-cache. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn>
* | | armv8/cache: Flush D-cache, invalidate I-cache for relocationYork Sun2014-04-07-6/+19
| | | | | | | | | | | | | | | | | | | | | | | | If D-cache is enabled, we need to flush it, and invalidate i-cache before jumping to the new location. This should be done right after relocation. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn>
* | | armv8/cache: Consolidate setting for MAIR and TCRYork Sun2014-04-07-25/+19
| | | | | | | | | | | | | | | | | | | | | | | | Move setting for MAIR and TCR to cache_v8.c, to avoid conflict with sub-architecture. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn>
* | | arm: Handle .gnu.hash section in ldscriptsAndreas Färber2014-04-07-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Avoids "could not find output section .gnu.hash" ld.bfd errors on openSUSE. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | | socfpga: Adding Clock Manager driverChin Liang See2014-04-07-1/+657
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | Clock Manager driver will be called to reconfigure all the clocks setting based on user input. The input are passed to Preloader through handoff files Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Acked-by: Pavel Machek <pavel@denx.de>
* | arm: mxs: Add support for generating signed BootStreamMarek Vasut2014-04-04-0/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the groundwork for generating signed BootStream, which can be used by the HAB library in i.MX28. We are adding a new target, u-boot-signed.sb , since the process for generating regular non-signed BootStream is much easier. Moreover, the signed bootstream depends on external _proprietary_ _binary-only_ tool from Freescale called 'cst', which is available only under NDA. To make things even uglier, the CST or HAB mandates a kind-of circular dependency. The problem is, unlike the regular IVT, which is generated by mxsimage, the IVT for signed boot must be generated by hand here due to special demands of the CST. The U-Boot binary (or SPL binary) and IVT are then signed by the CST as a one block. But here is the problem. The size of the entire image (U-Boot, IVT, CST blocks) must be appended at the end of IVT. But the size of the entire image is not known until the CST has finished signing the U-Boot and IVT. We solve this by expecting the CST block to be always 3904B (which it is in case two files, U-Boot and the hand-made IVT, are signed in the CST block). Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
generated by cgit v1.1 at 2024-11-25 09:23:04 +0000