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* ARM: Add support for MB86R0x SoCsMatthias Weisser2010-08-10-0/+950
| | | | Signed-off-by: Matthias Weisser <weisserm@arcor.de>
* Merge branch 'master' of git://git.denx.de/u-boot-imxWolfgang Denk2010-08-10-1/+1
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| * MX51EVK: fix return value of get_timer_maskedLi Haibo2010-08-10-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | get_timer_masked() should return current timestamp, not current ticks from hardware register. Tested on one custom board with NAND flash. Without this patch, NAND write always TIMEOUT because get_timer(0) return a big value. This patch applies for u-boot-2010.06 Signed-off-by: Li Haibo <hbli@sinocastel.com>
* | orion5x: allow overriding default mappings windowsAlbert Aribaud2010-08-10-41/+97
| | | | | | | | | | | | | | | | | | | | Turn all ORION5X_DEF{ADR,SZ}_xxx macros into ORION5X_{ADR,SZ}_xxx and allow defining them from board code to override defaults. This is particularly useful for defining board-specific FLASH address and size in board header file rather than having to tweak orion5x code. Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
* | Merge branch 'master' of git://git.denx.de/u-boot-marvellWolfgang Denk2010-08-10-0/+11
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| * | cmd_ide: add support for KirkwoodPrafulla Wadaskar2010-08-08-0/+5
| | | | | | | | | | | | | | | | | | | | | Added MVSATAC definitions to Kirkwood. Added support for Kirkwood in cmd_ide. Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
| * | cmd_ide: add support for orion5xAlbert Aribaud2010-08-08-0/+3
| | | | | | | | | | | | | | | | | | | | | Add MVSATAHC definitions to orion5x. Add support for orion5x in cmd_ide. Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
| * | ide: add configurationAlbert Aribaud2010-08-08-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_IDE_SWAP_IO This configuration option replaces a complex conditional in cmd_ide.c with an explicit define to be added to SoC or board configs. Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
* | | Merge branch 'master' of git://git.denx.de/u-boot-tiWolfgang Denk2010-08-10-10/+367
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| * | | ARMV7: Restructure omap3 musb driver to allow code sharing between OMAP3 and ↵Steve Sakoman2010-08-05-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | OMAP4 Signed-off-by: Steve Sakoman <steve@sakoman.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * | | ARMV7: Modify i2c driver for more reliable operation on OMAP4Steve Sakoman2010-08-05-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch modifies the init routine to follow the TRM recommendations. It also modifies the i2c_read_byte function to reflect subtle differences between the i2c controller in OMAP3 and OMAP4. Signed-off-by: Steve Sakoman <steve@sakoman.com> Acked-by: Nishanth Menon <menon.nishanth@gmail.com> Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * | | ARMV7: Fix udelay for OMAP4Steve Sakoman2010-08-05-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The OMAP4 x-load code sets gptimer1 clock source to 32Khz. This isn't acceptable for udelay. This patch changes from gptimer1 to gptimer2, which uses sys_clk at 38.4 Mhz. Signed-off-by: Steve Sakoman <steve@sakoman.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * | | ARMV7: Add pad mux support for OMAP4Steve Sakoman2010-08-05-0/+358
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | Add functional multiplexing support for OMAP4 pads. Configure all the pads for the OMAP4430 SDP and OMAP4 Panda boards Signed-off-by: Steve Sakoman <steve@sakoman.com> Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | | Merge branch 'master' of ../masterWolfgang Denk2010-08-10-2/+2
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| * | fdt relocate: have more attention to use a bootmap or notStephan Linz2010-08-08-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Platforms with flat device tree support can use a bootmap to relocate the fdt_blob. This is not a must. That's why the relocation function boot_relocate_fdt() should be use only if CONFIG_OF_LIBFDT was defined together with CONFIG_SYS_BOOTMAPSZ (see common/cmd_bootm.c). On MicroBlaze platforms there is no need to use a bootmap to relocate a fdt blob. So we need a more precise focus on the compilation and usage of boot_relocate_fdt(). In general it is valid to exclude the function boot_relocate_fdt() if the bootmap size CONFIG_SYS_BOOTMAPSZ is not defined. Signed-off-by: Stephan Linz <linz@li-pro.net>
* | | ARM: Define __raw_readX and __raw_writeXMarek Vasut2010-08-07-6/+40
| | | | | | | | | | | | | | | | | | | | | These functions are undefined on ARM when using __io. These are the commonly used versions and can be redefined. Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
* | | Merge branch 'master' of /home/wd/git/u-boot/masterWolfgang Denk2010-08-07-219/+2375
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| * Rename getenv_r() into getenv_f()Wolfgang Denk2010-08-04-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While running from flash, i. e. before relocation, we have only a limited C runtime environment without writable data segment. In this phase, some configurations (for example with environment in EEPROM) must not use the normal getenv(), but a special function. This function had been called getenv_r(), with the idea that the "_r" suffix would mean the same as in the _r_eentrant versions of some of the C library functions (for example getdate vs. getdate_r, getgrent vs. getgrent_r, etc.). Unfortunately this was a misleading name, as in U-Boot the "_r" generally means "running from RAM", i. e. _after_ relocation. To avoid confusion, rename into getenv_f() [as "running from flash"] Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de>
| * Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2010-08-04-188/+2273
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| | * powerpc/8xxx: query feature reporting register for num cores on unknown cpusKim Phillips2010-08-01-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | doing so helps avant garde users, such as those using simulators that allow users to configure the number of cores, so as to not have to manually adjust u-boot sources. h/w should also be reliably setting FRR NCPU in the future. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * powerpc/8xxx: Improvement to DDR parametersyork2010-07-26-7/+8
| | | | | | | | | | | | | | | | | | Changes for P2020DS DDR applies to other 8xxx platform Signed-off-by: York Sun <yorksun@freescale.com>
| | * powerpc/8xxx: Enable DDR3 RDIMM supportyork2010-07-26-53/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enabled registered DIMMs using data from SPD. RDIMMs have registers which need to be configured before using. The register configuration words are stored in SPD byte 60~116 (JEDEC standard No.21-C). Software should read those RCWs and put into DDR controller before initialization. Signed-off-by: York Sun <yorksun@freescale.com>
| | * powerpc/8xxx: Enabled address hashing for 85xxyork2010-07-26-0/+21
| | | | | | | | | | | | | | | | | | | | | For 85xx silicon which supports address hashing, it can be activated by hwconfig. Signed-off-by: York Sun <yorksun@freescale.com>
| | * powerpc/8xxx: Enable quad-rank DIMMs.york2010-07-26-21/+61
| | | | | | | | | | | | | | | | | | | | | Previous code presumes each DIMM has up to two rank (chip select). Newer DDR controller supports up to four chip select on one DIMM. Signed-off-by: York Sun <yorksun@freescale.com>
| | * powerpc/8xxx: Fix bug in memctrl interleaving & bank interleaving on cs0~cs4york2010-07-26-77/+184
| | | | | | | | | | | | | | | | | | | | | | | | | | | Verified on MPC8641HPCN with four DDR2 dimms. Each dimm has dual rank with 512MB each rank. Also check dimm size and rank size for memory controller interleaving Signed-off-by: York Sun <yorksun@freescale.com>
| | * powerpc/8xxx: Enabled hwconfig for memory interleavingKumar Gala2010-07-26-15/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace environmental variables memctl_intlv_ctl and ba_intlv_ctl with hwconfig parameters. The syntax is setenv hwconfig "fsl_ddr:ctlr_intlv=<mode>,bank_intlv=<mode>" The mode values for memory controller interleaving are cacheline page bank superbank The mode values for bank interleaving are cs0_cs1 cs2_cs3 cs0_cs1_and_cs2_cs3 cs0_cs1_cs2_cs3 Signed-off-by: York Sun <yorksun@freescale.com>
| | * powerpc/p4080: Add workaround for erratum CPU22Kumar Gala2010-07-26-1/+17
| | | | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * powerpc/p4080: Add workaround for errata SERDES8Kumar Gala2010-07-26-0/+295
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * powerpc/p4080: Add support for initializing SERDESKumar Gala2010-07-26-2/+357
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for initializing the SERDES blocks on CoreNet style QoriQ devices and the p4080 specific SERDES tables to know which actual componetns are enabled. Additionally, split out the Frame Manger (FMAN) into its specific ethernet ports instead of gross level of the full FMAN. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * powerpc/85xx: Add support to initialize LIODN registers and portalsKumar Gala2010-07-26-0/+762
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the new QorIQ/CoreNet based platforms we need to initialize the "portals" as access into the Data Path subystem as well as Logical IO Device Numbers (LIODN) that are used for the IOMMU (PAMU). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * powerpc/p4080: Add support for CPC(Corenet platform cache) on CoreNet platformsKumar Gala2010-07-26-1/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CoreNet style platforms can have a L3 cache that fronts the memory controllers. Enable that cache as well as add information into the device tree about it. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * powerpc/85xx: Move INIT_RAM_ADDR physical address to 36-bit spaceyork2010-07-26-0/+10
| | | | | | | | | | | | | | | | | | | | | If 36-bit physical address is used, move the INIT_RAM_ADDR to higher address. This frees the low 4GB address space for better use. Signed-off-by: York Sun <yorksun@freescale.com>
| | * powerpc/fsl_fman: Add initial fman immap structuresKumar Gala2010-07-26-0/+213
| | | | | | | | | | | | | | | | | | Add basic structures for Frame Manager on P4080/P3041/P5020 devices Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * powerpc/85xx: Add additional p4080 platform related defines/structsKumar Gala2010-07-26-22/+197
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Added PCIE4 address, offset, DEVDISR & LAW target ID * Added new p4080 DDR registers and defines to immap * Add missing corenet platform DEVDISR related defines * Updated ccsr_gur to include LIODN registers * Add RCWSR defines * Added Basic qman, pme, bman immap structs * Added SATA related offsets & addresses * Added Frame Manager 1/2 offsets & addresses * Renamed CONFIG_SYS_TSEC1_OFFSET to CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET * Added various offsets and addresses that where missing Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | Blackfin: gpio: use common usage funcMike Frysinger2010-07-29-4/+2
| | | | | | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: jtag-console: handle newline stuffingMike Frysinger2010-07-25-9/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Serial devices currently have to manually stuff \r after every \n found, but this is a bit more difficult with the jtag console since we process everything in chunks of 4 bit. So we have to scan & stuff the whole string rather than what most serial drivers do which is output on a byte per byte basis. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: jtag-console: add debug markersMike Frysinger2010-07-25-1/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While we're in here, add some useful debug points. We need custom debug statements because we need the output to only go to the serial port. If we used the standard debug helpers, the output would also go to the stdout (which would be the jtag console) and make it hard to figure out what is going where exactly. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: jtag-console: robustify against missing peerMike Frysinger2010-07-25-8/+32
| |/ | | | | | | | | | | | | | | | | If the other side isn't listening, we should reset the state to ignore the whole message and not just the part we missed. This makes it easier to connect at any time to the jtag console without worrying about the two sides getting out of sync and thus sending garbage back and forth. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-samsungWolfgang Denk2010-08-04-0/+73
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| * | S5P: support mmc driverMinkyu Kang2010-08-03-0/+73
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds support mmc driver for s5p SoC Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
* | | Merge branch 'master' of /home/wd/git/u-boot/masterWolfgang Denk2010-08-03-96/+570
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| * | cmd_usage(): simplify return code handlingWolfgang Denk2010-07-24-26/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Lots of code use this construct: cmd_usage(cmdtp); return 1; Change cmd_usage() let it return 1 - then we can replace all these ocurrances by return cmd_usage(cmdtp); This fixes a few places with incorrect return code handling, too. Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2010-07-24-5/+341
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| | * | ppc4xx: Add ECC status info to machine-check exception for IBM DDR2 coreStefan Roese2010-07-23-0/+16
| | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| | * | ppc4xx: Add "ecctest" command to test/simulate ECC errorsStefan Roese2010-07-23-0/+287
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the "ecctest" command to test and simulate ECC errors (single bit and/or double bit) while running from SDRAM. Currently only the IBM DDR2 controller is supported (405EX, 440SP(e), 460EX/GT). This is done by copying and calling functions, modifying the SDRAM controller operation mode, in internal SRAM/OCM. For correctable ECC errors (single bit) only the status will be printed since the DDR2 controller doesn't provide the faulting address: => ecctest 1000000 1 Using address 01000000 for 1 bit ECC error injection ECC: Correctable error Uncorrectable ECC errors (double bit) will also display the faulting address: => ecctest 1000000 2 Using address 01000000 for 2 bit ECC error injection ECC: Uncorrectable error at 0x0001000000 To enable this "ecctest" function you need to define CONFIG_CMD_ECCTEST in the board config header. Tested on katmai and t3corp. Signed-off-by: Stefan Roese <sr@denx.de>
| | * | ppc4xx: DDR/ECC: Use correct macros to clear error statusStefan Roese2010-07-23-1/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the correct macro instead of the hardcoded 0x4c to clear the ECC status in the 440/460 DDR(2) error status register after ECC initialization. Also the non-440 parts (405EX(r) right now) and the IBM DDR PPC variants (440GX) use a different registers to clear this error status. Use the correct ones. Signed-off-by: Stefan Roese <sr@denx.de>
| | * | ppc4xx: Only define DDR2 registers for the correct PowerPC variantsStefan Roese2010-07-23-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Make sure that some SDRAM/DDR2 registers are only defined for the PPC variants really implementing those registers. Signed-off-by: Stefan Roese <sr@denx.de>
| | * | ppc4xx: Add CONFIG_DDR_RFDC_FIXED to allow board specific RFDC valuesStefan Roese2010-07-23-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using this define, a board can define an opimized RFDC value and use the auto calibration code to "tune" the remaining DDR2 controller calibration register. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | powerpc/85xx: Rework P1022 SERDES is_serdes_configured supportKumar Gala2010-07-21-11/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move serdes init until after we are in ram so we can keep track of a global static protocal map for the particular serdes config we are in. This makes is_serdes_configured() much simplier and not constantly reading registers to determine if a given device is enabled based on the protocol. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | powerpc/85xx: Rework MPC8536 SERDES is_serdes_configured supportKumar Gala2010-07-21-40/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move serdes init until after we are in ram so we can keep track of a global static protocal map for the particular serdes config we are in. This makes is_serdes_configured() much simplier and not constantly reading registers to determine if a given device is enabled based on the protocol. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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