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* MLK-12434-1: imx: dynamic setting mmcdev and mmcrootPeng Fan2017-04-05-0/+5
| | | | | | | | Align to imx_v2015.04, dynamic setting mmcdev and mmcroot. Then when boot linux, we can have correct "root=/dev/mmcblk[x]p2" Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit b46b99a901eb194e81fc4836ee2259ad8857f4d3)
* MLK-12425-1: mx6sl/ul: introudce more pinmux macrosPeng Fan2017-04-05-3/+84
| | | | | | | Introuduce more pinmux macros definitions. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 06893558f2cc042b683247989be5127a8027ebf2)
* MLK-12693-2 nand: mxs: correct bitflip for erased NAND pagePeng Fan2017-04-05-1/+5
| | | | | | | | | | | | | | | | | | | | This patch is a porting of http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_4.1.15_1.0.0_ga&id=e4dacc44d22e9474ec456cb330df525cd805ea38 " i.MX6QP and i.MX7D BCH module integrated a new feature to detect the bitflip number for erased NAND page. So for these two platform, set the erase threshold to gf/2 and if bitflip detected, GPMI driver will correct the data to all 0xFF. Also updated the imx6qp dts file to ditinguish the GPMI module for i.MX6Q with the one for i.MX6QP. " In this patch, i.MX6UL is added and threshold changed to use ecc_strength. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 489929be0221bb7d4c46bb5bc6083650b78f73e0) Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-11528 imx: mx6ul check fuse before init beePeng Fan2017-03-14-1/+11
| | | | | | | | | | | | Need to check fuse bit 25 of bank 0 word 4 before initialize bee. The bit: 0 means bee enabled, 1 means bee disabled. If disabled, continuing initialize bee will cause system hang, so need to check this bit before initialize bee. Add macro to enable BEE in header file, default disabled. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit ef4cb7c53418e4e1dd7cfcb7c6974cfea77ef3c0)
* MLK-10958 imx: mx6ul support Bus Encryption EnginePeng Fan2017-03-14-1/+513
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to support Bus Encryption Engine(BEE) for i.MX 6UL. Supported feature: 1. SNVS key and soft key 2. CTR and ECB mode 3. Specify address region to bee. Two commands are included: bee init [key] [mode] [start] [end] - BEE block initial "Example: bee init 1 1 0x80000000 0x80010000\n" bee test [region] "Example: bee test 1\n" Mapping: [0x10000000 - (0x10000000 + size - 1)] : [start - (start + size - 1)] [0x30000000 - (0x30000000 + IRAM_SIZE - 1)] : [IRAM_BASE_ADDR - (IRAM_BASE_ADDR + IRAM_SIZE - 1)] Whatever start is, start - (start + size -1) will be fixed mapping to 0x10000000 - (0x10000000 + size - 1) Since default AES region's protected size is SZ_512M, so on mx6ul evk board, you can not simply run 'bee init', it will overlap with uboot execution environment, you can use 'bee init 0 0 0x80000000 0x81000000'. If want to use bee, Need to define CONFIG_CMD_BEE in board configuration header file, since CONFIG_CMD_BEE default is not enabled. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 29b9bdbbdac9678dba9b7bc2d3662598e9c548a5) (cherry picked from commit 6d45292ff7e7020a48842f033f8a337daabe4476)
* MLK-12416-4: imx: mx6: update imx-regs.hPeng Fan2017-03-14-13/+119
| | | | | | | Update imx-regs.h to align with 2016.03 Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 9bbd54e44ae1f0868d3f0dd34975e76606b0a5e8)
* MLK-14422 imx7d: wdog: Overwrite the reset_cpu to turn off internal reset signalYe Li2017-03-14-0/+15
| | | | | | | | Set wdog WCR register SRS bit to turn off internal reset signal WDOG_RESET_B_DEB for mx7d. So that the warm reset is disabled. The WDA is cleared to output WDOG_B immediately to reset the board. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14420-2 DTS: add DTS file for imx6q sabresd boardYe Li2017-03-14-0/+1123
| | | | | | Copy the dts and dtsi files from kernel to support imx6q sabresd board. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14420-1 DTS: Update imx6qdl relevant dts and clock definitionsYe Li2017-03-14-418/+451
| | | | | | Get the latest dtsi files and clock.h for imx6qdl from kernel Signed-off-by: Ye Li <ye.li@nxp.com>
* arm: omap-common: Fix typo in CONFIG_OMAP54XX guardMatthijs van Duin2017-03-11-1/+1
| | | | | | | | Some initialization was unintentionally being skipped on omap5. Fixes: f5af0827f276 ("arm: omap-common: Guard some parts of the code with CONFIG_OMAP44XX/OMAP54XX") Signed-off-by: Matthijs van Duin <matthijsvanduin@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: OMAP2+: nandecc: propagate error to command return statusLadislav Michl2017-03-11-20/+16
| | | | | | | | | Currently nandecc returns zero even if underlaying omap_nand_switch_ecc function fails. Fix that by propagating error returned to command return value. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: Migrate errata to KconfigTom Rini2017-03-09-6/+85
| | | | | | | | | This moves all of the current ARM errata from various header files and in to Kconfig. This allows for a minor amount of cleanup as we had some instances where both a general common header file was enabling errata as well as the board config. We now just select these once at the higher level in Kconfig Signed-off-by: Tom Rini <trini@konsulko.com>
* omap4: Migrate to using implyTom Rini2017-03-09-36/+12
| | | | | | | Move the default y options under arch/arm/mach-omap2/omap4/Kconfig to be using imply instead in arch/arm/Kconfig Signed-off-by: Tom Rini <trini@konsulko.com>
* omap3: Migrate to using implyTom Rini2017-03-09-33/+11
| | | | | | | Move the default y options under arch/arm/mach-omap2/omap3/Kconfig to be using imply instead in arch/arm/Kconfig Signed-off-by: Tom Rini <trini@konsulko.com>
* TI: Migrate board/ti/common/Kconfig to implyTom Rini2017-03-09-46/+39
| | | | | | | The option that we had set in board/ti/common/Kconfig as default y are best done with imply under the appropriate main Kconfig option instead. Signed-off-by: Tom Rini <trini@konsulko.com>
* am335x_evm: Switch to using imply keywordTom Rini2017-03-09-0/+3
| | | | | | | | These particular SPL options are part of what the ROM provides, but for compatibility with how we have previously used them, move them to being implied by the board being selected. Signed-off-by: Tom Rini <trini@konsulko.com>
* do_smhload: fix return codeRyan Harkin2017-03-09-2/+2
| | | | | | | | | | | | | do_smhload was using a ulong to store the return value from smh_load_file. That returns an int, where -1 indicates an error. As a ulong will never be negative, smh_load_file errors were not detected and so_smhload always returned zero. Also, when errors were spotted, do_smhload was returning 1, rather than the enumeration CMD_RET_FAILURE (which is also 1). Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* Freescale/NXP: Migrate CONFIG_FSL_CAAM to defconfigsTom Rini2017-03-09-10/+1
| | | | | | | | | | | | | | | | | | | | | | In some cases this is absolutely required, so select this for some secure features. This also requires migration of RSA_FREESCALE_EXP Cc: Ruchika Gupta <ruchika.gupta@nxp.com> Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com> Cc: Naveen Burmi <NaveenBurmi@freescale.com> Cc: Po Liu <po.liu@freescale.com> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Priyanka Jain <Priyanka.Jain@freescale.com> Cc: Sumit Garg <sumit.garg@nxp.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Feng Li <feng.li_2@nxp.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Mingkai Hu <Mingkai.Hu@freescale.com> Cc: York Sun <york.sun@nxp.com> Cc: Saksham Jain <saksham.jain@nxp.freescale.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* armv8: spl: Call spl_relocate_stack_gd for ARMv8Philipp Tomsich2017-03-01-2/+12
| | | | | | | | | | As part of the startup process for boards using the SPL, we need to call spl_relocate_stack_gd. This is needed to set up malloc with its DRAM buffer. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* armv5te: make 'ret lr' produce iinterworking 'bx lr'Albert ARIBAUD2017-03-01-1/+1
| | | | | | | | | | | | | | | | | Current ARM assembler helper for the 'return to caller' pseudo-instruction turns 'ret lr' into 'mov pc, lr' for ARMv5TE. This causes the core to remain in its current ARM state even when the routine doing the 'ret' was called from Thumb-1 state, triggering an undefined instruction exception. This causes early run-time failures in all boards compiled using the Thumb-1 instruction set (for instance the Open-RD family). ARMv5TE supports 'bx lr' which properly implements interworking and thus correctly returns to Thumb-1 state from ARM state. This change makes 'ret lr' turn into 'bx lr' for ARMv5TE. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* arm: mach-omap2: Flush cache after FIT post-processing imageAndrew F. Davis2017-02-27-0/+6
| | | | | | | | | | After we authenticate/decrypt an image we need to flush the caches as they may still contain bits of the encrypted image. This will cause failures if we attempt to jump to this image. Reported-by: Yogesh Siraswar<yogeshs@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: uniphier: set up charge pump current for MPLL of LD11 SoCMasahiro Yamada2017-02-23-0/+24
| | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add simple eMMC load APIs instead of ROM APIMasahiro Yamada2017-02-23-58/+195
| | | | | | | | | | | Re-use of routines embedded in the Boot ROM requires a function pointer table for each SoC. This is not nice in terms of the maintainability in a long run. Implement simple eMMC load APIs that are commonly used for LD11, LD20, and hopefully future SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: deassert RST_n of eMMC device for LD11/LD20Masahiro Yamada2017-02-23-1/+25
| | | | | | | | | | | | | For LD11 and LD20 SoCs, the RST_n pin is asserted by default. If the EXT_CSD[162], bit[1:0] (RST_n_ENABLE) is fused, the eMMC device would stay in the reset state until its RST_n pin is deasserted by software. Currently, this is cared by an ad-hoc way because the eMMC hardware reset provider is not supported in U-Boot for now. This code should be re-written once the "mmc-pwrseq-emmc" binding is supported. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add DRAM PHY clock duty adjustment for LD20 SoCKotaro Hayashi2017-02-23-2/+8
| | | | | | | | | | If the DRAM clock duty does not meet the allowable tolerance, it is marked in an efuse register. If the register is fused, the boot code should compensate for the DRAM clock duty error. Signed-off-by: Kotaro Hayashi <hayashi.kotaro@socionext.com> [masahiro: simplify code, add git-log] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: remove dram_nr_ch from board parametersMasahiro Yamada2017-02-23-26/+18
| | | | | | | This parameter is redundant because we can know the number of channels by checking if dram_ch[2].size is zero. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: rework spl_boot_device() and related codeMasahiro Yamada2017-02-23-344/+312
| | | | | | | | The current implementation has ugly switch statements here and there, and duplicates similar code. Rework it using table lookups for SoC data and reduce code duplication. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: move spl_boot_mode() to a separate fileMasahiro Yamada2017-02-23-24/+35
| | | | | | | | The spl_boot_mode() is unrelated to the other code in this file. Besides, this function is only called from common/spl/spl_mmc.c, so it is reasonable to guard with CONFIG_SPL_MMC_SUPPORT. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: move MMC code to a separate fileMasahiro Yamada2017-02-23-38/+47
| | | | | | | | | | Currently, arch/arm/mach-uniphier/boot-mode/boot-mode.c is messed up with unrelated code; there is no reason why the "mmcsetn" command must be placed in this file. Split out the MMC code into arch/arm/mach-uniphier/mmc-first-dev.c. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: dts: uniphier: drop u-boot, dm-pre-reloc from system-bus pinctrl nodeMasahiro Yamada2017-02-23-8/+0
| | | | | | | | Since commit 26b09c022ab6 ("ARM: uniphier: move SBC and Support Card init code to U-Boot proper"), SPL does not need pin-mux settings for the System Bus. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: remove DRAM base address from board parametersMasahiro Yamada2017-02-23-57/+36
| | | | | | | | | The base address of each DRAM channel can be calculated from other parameters, so does not need hard-coding. What we need is the size of each DRAM channel and DRAM_SPARSE flag to decide the start address of DRAM channel 1. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: print Support Card info very lateMasahiro Yamada2017-02-23-7/+4
| | | | | | | | | | | Since commit 26b09c022ab6 ("ARM: uniphier: move SBC and Support Card init code to U-Boot proper"), the System Bus is initialized by board_init(). The show_board_info() is called from board_init_f() by default, so the revision register of the Micro Support Card may not be accessed at this point. Show its revision after the System Bus is initialized. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: skip memreserve of unused DRAM bank of LD20Masahiro Yamada2017-02-23-0/+3
| | | | | | | | Now the "for" loop here iterates on the detected memory banks. It must skip unused DRAM banks. Fixes: c995f3a3c526 ("ARM: uniphier: use gd->bd->bi_dram for memory reserve on LD20 SoC") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: correct spelling of "invalid"Masahiro Yamada2017-02-23-3/+3
| | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: skip MEMCONF ch2 parsing if CH2_DISABLE bit is setMasahiro Yamada2017-02-23-1/+1
| | | | | | | If SG_MEMCONF_CH2_DISABLE bit is set, the DRAM channel 2 is unused. The register settings for the ch2 should be ignored. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: revive accidentally removed dcache_disable()Masahiro Yamada2017-02-23-0/+4
| | | | | | | | | Commit a8e6300d483d ("ARM: uniphier: refactor spl_init_board()") accidentally dropped dcache_disable() call. Since then, the SPL of LD11 and LD20 failed to load U-Boot proper. Fixes: a8e6300d483d ("ARM: uniphier: refactor spl_init_board()") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* x86: Intel MID platforms has no microcode updateAndy Shevchenko2017-02-21-1/+2
| | | | | | | | | | | There is no microcode update available for SoCs used on Intel MID platforms. Use conditional to bypass it. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* x86: zImage: add Intel MID platforms supportVincent Tinelli2017-02-21-0/+4
| | | | | | | | | | | | Intel MID platform boards have special treatment, such as boot parameter setting. Assign hardware_subarch accordingly if CONFIG_INTEL_MID is set. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* x86: Introduce INTEL_MID quirk optionAndy Shevchenko2017-02-21-0/+14
| | | | | | | | | | | | | | | | | | Intel Mobile Internet Device (MID) platforms have special treatment in some cases, such as CPU enumeration or boot parameters configuration. Besides that several drivers are specifically developed for the IP blocks found on Intel MID platforms. Those drivers will be dependent to this option. Here we introduce specific quirk option for such cases. It is supposed to be selected by Intel MID platform boards, for example, Intel Edison. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* x86: Force 32-bit jumps in interrupt handlersJ. Tang2017-02-21-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Depending upon the compiler used, IRQ entries could vary in sizes. With GCC 5.x, the code generator will use short jumps for some IRQ entries but near jumps for others. For example, GCC 5.4.0 generates the following: $ objdump -d interrupt.o <snip> 00000207 <irq_18>: 207: 6a 12 push $0x12 209: eb 85 jmp 190 <irq_common_entry> 0000020b <irq_19>: 20b: 6a 13 push $0x13 20d: eb 81 jmp 190 <irq_common_entry> 0000020f <irq_20>: 20f: 6a 14 push $0x14 211: e9 7a ff ff ff jmp 190 <irq_common_entry> 00000216 <irq_21>: 216: 6a 15 push $0x15 218: e9 73 ff ff ff jmp 190 <irq_common_entry> This causes a problem in cpu_init_interrupts(), because the IDT setup assumed same sizes for all IRQ entries. GCC 4.x always generated 32-bit jumps, so this previously was not a problem. The fix is to force 32-bit near jumps for all entries within the inline assembly. This works for GCC 5.x, and 4.x was already using that form of jumping. Signed-off-by: Jason Tang <tang@jtang.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* ARM: DRA7xx: Fix memory allocation overflowAndrew F. Davis2017-02-17-1/+1
| | | | | | | | | | When using early malloc the allocated memory can overflow into the SRAM scratch space, move NON_SECURE_SRAM_IMG_END down a bit to allow more dynamic allocation at the expense of a slightly smaller maximum image size. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* SPL: Move SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION to KconfigDalon Westergreen2017-02-17-0/+1
| | | | | | | | | | | Added SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION and SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION to Kconfig. Due to SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION being moved to Kconfig the board defconfigs for db-88f6820-gp_defconfig kc1_defconfig and sniper_defconfig need to be updated. Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
* SPL: add support to boot from a partition typeDalon Westergreen2017-02-17-0/+6
| | | | | | | | | | | | | the socfpga bootrom supports mmc booting from either a raw image starting at 0x0, or from a partition of type 0xa2. This patch adds support for locating the boot image in the first type 0xa2 partition found. Assigned a partition number of -1 will cause a search for a partition of type CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE and use it to find the u-boot image Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
* arm: omap5: Fix generation of reserved-memory DT nodeAndrew F. Davis2017-02-17-1/+6
| | | | | | | | | When the node 'reserved-memory' is not defined in the DT we fail to add needed properties. We also fail to move 'offs' to point to the new node. Fix these here. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* Merge tag 'xilinx-fixes-for-v2017.03' of git://www.denx.de/git/u-boot-microblazeTom Rini2017-02-13-1/+1
|\ | | | | | | | | | | | | | | Xilinx fixes for v2017.03 - defconfig alignment - Topic.nl board updates - Minor microblaze comment fix
| * microblaze: Fix endif macro commandMichal Simek2017-02-10-1/+1
| | | | | | | | | | | | Use correct name in endif comment. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | flash: complete CONFIG_SYS_NO_FLASH move with renamingMasahiro Yamada2017-02-12-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We repeated partial moves for CONFIG_SYS_NO_FLASH, but this is not completed. Finish this work by the tool. During this move, let's rename it to CONFIG_MTD_NOR_FLASH. Actually, we have more instances of "#ifndef CONFIG_SYS_NO_FLASH" than those of "#ifdef CONFIG_SYS_NO_FLASH". Flipping the logic will make the code more readable. Besides, negative meaning symbols do not fit in obj-$(CONFIG_...) style Makefiles. This commit was created as follows: [1] Edit "default n" to "default y" in the config entry in common/Kconfig. [2] Run "tools/moveconfig.py -y -r HEAD SYS_NO_FLASH" [3] Rename the instances in defconfigs by the following: find . -path './configs/*_defconfig' | xargs sed -i \ -e '/CONFIG_SYS_NO_FLASH=y/d' \ -e 's/# CONFIG_SYS_NO_FLASH is not set/CONFIG_MTD_NOR_FLASH=y/' [4] Change the conditionals by the following: find . -name '*.[ch]' | xargs sed -i \ -e 's/ifndef CONFIG_SYS_NO_FLASH/ifdef CONFIG_MTD_NOR_FLASH/' \ -e 's/ifdef CONFIG_SYS_NO_FLASH/ifndef CONFIG_MTD_NOR_FLASH/' \ -e 's/!defined(CONFIG_SYS_NO_FLASH)/defined(CONFIG_MTD_NOR_FLASH)/' \ -e 's/defined(CONFIG_SYS_NO_FLASH)/!defined(CONFIG_MTD_NOR_FLASH)/' [5] Modify the following manually - Rename the rest of instances - Remove the description from README - Create the new Kconfig entry in drivers/mtd/Kconfig - Remove the old Kconfig entry from common/Kconfig - Remove the garbage comments from include/configs/*.h Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge git://git.denx.de/u-boot-rockchipTom Rini2017-02-11-65/+65
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| * rockchip: rename miniarm to tinker boardEddie Cai2017-02-09-10/+10
| | | | | | | | | | | | | | | | Miniarm is the internal project code. Now it is officially named Tinker board. So rename it. Signed-off-by: Eddie Cai <eddie.cai@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * rockchip: dts: rk3288: correct sdram setting for miniarmJacob Chen2017-02-09-8/+8
| | | | | | | | | | | | | | | | | | | | | | miniarm board use lpddr3 Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Added 'rockchip:' prefix to subject: Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: I84c3679dab2dbd8d01c1ebfd22220946d07c03cd
generated by cgit v1.1 at 2024-08-24 12:57:46 +0000