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* Merge git://git.denx.de/u-boot-rockchipTom Rini2017-02-11-65/+65
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| * rockchip: rename miniarm to tinker boardEddie Cai2017-02-09-10/+10
| | | | | | | | | | | | | | | | Miniarm is the internal project code. Now it is officially named Tinker board. So rename it. Signed-off-by: Eddie Cai <eddie.cai@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * rockchip: dts: rk3288: correct sdram setting for miniarmJacob Chen2017-02-09-8/+8
| | | | | | | | | | | | | | | | | | | | | | miniarm board use lpddr3 Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Added 'rockchip:' prefix to subject: Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: I84c3679dab2dbd8d01c1ebfd22220946d07c03cd
* | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2017-02-09-2/+2
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| * | net: phy: dp83867: Add support for MAC impedance configurationMugunthan V N2017-02-07-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for programmable MAC impedance configuration and fix typo in DT impedance parameters names. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Tested-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mmcTom Rini2017-02-09-8/+142
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| * | | arm: dts: trats: add the pmic node for using DMJaehoon Chung2017-02-09-8/+142
| | |/ | |/| | | | | | | | | | | | | | | | | | | To use driver-model adds the pmic node for max8997. This is used as kernel device-tree in Linux. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2017-02-08-0/+9
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| * | arm: socfpga: set the mpuclk divider in the Altera group registerDinh Nguyen2017-02-08-0/+9
| |/ | | | | | | | | | | | | | | | | | | | | | | | | The mpuclk register in the Altera group of the clock manager divides the mpu_clk that is generated from the C0 output of the main pll. Without this patch, the default value of the register is 1, so the mpuclk will always get divided by 2 if the correct value is not set. For example, on the Arria5 socdk board, the MPU clock is only 525 MHz, and it should be 1.05 GHz. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
* | Merge git://git.denx.de/u-boot-dmTom Rini2017-02-08-27/+34
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| * | dm: core: Replace of_offset with accessorSimon Glass2017-02-08-27/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dtoc: Replace dot with underscore to avoid compiler errorsSimon Glass2017-02-08-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | If there is a '.' in a compatible string, then dtoc will produce a struct with a name containing a '.'. This won't work, so replace it with '_'. Also add a suitable test to the sandbox device tree to catch this. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | cmd: move CONFIG_CMD_UNZIP and CONFIG_CMD_ZIP to KconfigMasahiro Yamada2017-02-08-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_CMD_ZIP is not defined by any board. I am moving CONFIG_CMD_UNZIP to defconfig files except UniPhier SoC family. I am the maintainer of UniPhier platform, so I know "select CMD_UNZIP" is better for this platform. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Ryan Harkin <ryan.harkin@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
* | | arm64: fix comment in relocate_64.SMasahiro Yamada2017-02-08-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two typos in the comment "invalide i-cache is enabled". We can fix it by invalide -> invalidate is -> if Or, if we want to match the comment to the code, we can say "skip invalidating i-cache if disabled". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | ARM: dts: k2*: Rename the k2* files to keystone-k2* filesLokesh Vutla2017-02-08-20/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As reported in [1], rename the k2* dts files to keystone-* files this will force consistency throughout. Script for the same (and hand modified for Makefile and config files): for i in arch/arm/dts/k2* do b=`basename $i`; git mv $i arch/arm/dts/keystone-$b; sed -i -e "s/$b/keystone-$b/g" arch/arm/dts/*[si] done This is similar to linux kernel commit 5edafc29829bc ("ARM: dts: k2*: Rename the k2* files to keystone-k2* files") [1] http://marc.info/?l=linux-arm-kernel&m=145637407804754&w=2 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | arm64: use store with auto-incrementMasahiro Yamada2017-02-08-2/+1
| | | | | | | | | | | | | | | | | | | | | Save one instruction. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | arm64: use xzr to zero-out the bss sectionMasahiro Yamada2017-02-08-2/+1
|/ / | | | | | | | | | | | | AArch64 has a zero register (xzr). Use it instead of x2. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | x86: make LOAD_FROM_32_BIT visible for platformsAndy Shevchenko2017-02-07-10/+10
| | | | | | | | | | | | | | | | | | | | | | This option is useful not only for development, but for the platforms where U-Boot is run from custom ROM bootloader. For example, Intel Edison is that board. Make this option visible that platforms can select it if needed. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: qemu: Mark ucode as optional for SPL in u-boot.dtsiBin Meng2017-02-07-0/+6
| | | | | | | | | | | | | | | | QEMU does not need ucode and this is indicated in u-boot.dtsi for U-Boot proper. Now add the same for SPL. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | x86: qemu: Set up device tree for SPLBin Meng2017-02-07-0/+8
| | | | | | | | | | | | | | | | Add the correct pre-relocation tag so that the required device tree nodes are present in the SPL device tree. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | x86: qemu: Fix compiler warnings for 64-bitBin Meng2017-02-07-4/+4
| | | | | | | | | | | | | | This fixes compiler warnings for QEMU in 64-bit. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | x86: qemu: Hide arch_cpu_init() and print_cpuinfo() for U-Boot properBin Meng2017-02-07-1/+4
| | | | | | | | | | | | | | | | arch_cpu_init() and print_cpuinfo() should be only available in SPL build. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | x86: Compile irq.c for 64-bitBin Meng2017-02-07-1/+1
| | | | | | | | | | | | | | There is no reason not to compile irq.c for 64-bit. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | x86: spl: Add weak arch_cpu_init_dm()Bin Meng2017-02-07-0/+5
| | | | | | | | | | | | | | | | arch_cpu_init_dm() might not be implemented by every platform. Implement a weak version for SPL. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | x86: Wrap print_ch() with config optionBin Meng2017-02-07-0/+2
| | | | | | | | | | | | | | print_ch() should not be used if DEBUG_UART is off. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | x86: qemu: Add missing DECLARE_GLOBAL_DATA_PTR in e820.cBin Meng2017-02-07-0/+2
| | | | | | | | | | | | | | DECLARE_GLOBAL_DATA_PTR is missing which causes 64-bit build error. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | x86: Update compile/link flags to support 64-bit U-BootSimon Glass2017-02-07-4/+28
| | | | | | | | | | | | | | Update config.mk settings to support both 32-bit and 64-bit U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: link: Set up device tree for SPLSimon Glass2017-02-07-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | Add the correct pre-relocation tag so that the required device tree nodes are present in the SPL device tree. On x86 it doesn't make a lot of sense to have a separate SPL device tree. Since everything is in the same ROM we might as well just use the main device tree in both SPL and U-Boot proper. But we haven't implemented that, so this is a good first step. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: link: Add SPL declarations to the binman imageSimon Glass2017-02-07-0/+19
| | | | | | | | | | | | | | | | When building for 64-bit we need to put an SPL binary into the image. Update the binman image description to reflect this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Add a dummy setjmp implementation for x86_64Simon Glass2017-02-07-1/+21
| | | | | | | | | | | | | | | | We don't have the code for this yet. Add a dummy version for now, so that EFI builds correctly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Move setjmp to the i386 directorySimon Glass2017-02-07-3/+1
| | | | | | | | | | | | | | | | This code is only used in 32-bit mode. Move it so that it does not get built with 64-bit U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Move call64 to the i386 directorySimon Glass2017-02-07-1/+2
| | | | | | | | | | | | | | | | This code is only used in 32-bit mode. Move it so that it does not get built with 64-bit U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Change irq_already_routed to a local variableSimon Glass2017-02-07-4/+6
| | | | | | | | | | | | | | This avoids using BSS before SDRAM is set up in SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Move turbo_state to global_dataSimon Glass2017-02-07-4/+5
| | | | | | | | | | | | | | | | To avoid using BSS in SPL before SDRAM is set up, move this field to global_data. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Move pirq_routing_table to global_dataSimon Glass2017-02-07-7/+6
| | | | | | | | | | | | | | | | To avoid using BSS in SPL before SDRAM is set up, move this field to global_data. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Support jumping from SPL to U-BootSimon Glass2017-02-06-0/+76
| | | | | | | | | | | | | | | | Add a rough function to handle jumping from 32-bit SPL to 64-bit U-Boot. This still needs work to clean it up. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Drop interrupt support in 64-bit modeSimon Glass2017-02-06-0/+5
| | | | | | | | | | | | | | This is not currently supported, so drop the code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Don't try to boot Linux from SPLSimon Glass2017-02-06-0/+4
| | | | | | | | | | | | | | | | | | | | | | Booting into linux from 64-bit U-Boot is not yet supported. Avoid bringing in the bootm code until it is implemented. Of course 32-bit U-Boot still supports booting into both 32- and 64-bit kernels. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Don't build 32-bit efi files on x86_64Simon Glass2017-02-06-0/+4
| | | | | | | | | | | | | | These cannot be built in this mode, so drop them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Don't build cpu files which are not supported on 64-bitSimon Glass2017-02-06-1/+8
| | | | | | | | | | | | | | | | Some files cannot be built with 64-bit and mostly don't make sense in that context. Disable them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Don't build call64 and setjmp on 64-bitSimon Glass2017-02-06-1/+12
| | | | | | | | | | | | | | | | | | These are currently not supported. Calling 64-bit code from 64-bit U-Boot is much simpler, so this code is not needed. setjmp() is not yet implemented for 64-bit. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Don't try to run the VGA BIOS in 64-bit modeSimon Glass2017-02-06-0/+2
| | | | | | | | | | | | | | This is not supported, so disable it for now. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Provide a dummy SDRAM init for 64-bitSimon Glass2017-02-06-0/+31
| | | | | | | | | | | | | | | | | | | | We don't support SDRAM init in 64-bit mode since it is essentially impossible to get into that mode before SDRAM set up. Provide dummy functions for now. At some point we will need to pass the SDRAM parameters through from SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Skip SATA init in SPLSimon Glass2017-02-06-0/+2
| | | | | | | | | | | | | | This doesn't work at present. Disable it for now. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Fix up type sizes for 64-bitSimon Glass2017-02-06-0/+10
| | | | | | | | | | | | | | Adjust types as needed to support 64-bit compilation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Drop flag_is_changable() on x86_64Simon Glass2017-02-06-0/+3
| | | | | | | | | | | | | | | | This doesn't build at present and is not used in a 64-bit build. Disable it for now. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Fix up byteorder.h for x86_64Simon Glass2017-02-06-8/+9
| | | | | | | | | | | | | | Remove the very old x86 code and add support for 64-bit. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Add a link script for SPLSimon Glass2017-02-06-0/+74
| | | | | | | | | | | | | | | | If SPL is used it is always build in 32-bit mode. Add a link script to handle the correct placement of the sections. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Add a link script for 64-bit x86Simon Glass2017-02-06-0/+82
| | | | | | | | | | | | | | | | This needs a different image format from 32-bit x86, so add a new link script. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Fix up CONFIG_X86_64 checkSimon Glass2017-02-06-1/+1
| | | | | | | | | | | | | | | | When SPL and U-Boot proper have different settings for this flag, we need to use the correct one. Fix this up in the interrupt code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit v1.1 at 2024-07-15 05:44:44 +0000