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* arm: mx6: Add CCV xPress board supportStefan Roese2016-03-26-0/+8
* arm: mx6: Add UART8 base address for i.MX6ULStefan Roese2016-03-26-0/+1
* warp7: Add initial supportFabio Estevam2016-03-26-0/+7
* mx27: 16-bit wide watchdog registersLeonid Iziumtsev2016-03-25-7/+7
* arm: imx6: Switch DDR3 calibration to wait_for_bit()Marek Vasut2016-03-25-32/+12
* imx: print ARM clock for clocks commandPeng Fan2016-03-25-0/+1
* imx: mx6ul configure the PMIC_STBY_REQ pin as open drainPeng Fan2016-03-25-1/+11
* imx: mx6ul: skip setting ahb ratePeng Fan2016-03-25-7/+12
* imx: mx6: Fix incorrect clear mmdc_ch0 handshake maskYe Li2016-03-25-1/+4
* Merge branch 'next'Stefano Babic2016-03-20-0/+34
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| * mx7: Distinguish between dual and solo versionsFabio Estevam2016-03-09-0/+21
| * arm: imx: Add support for GE Bx50v3 boardsAkshay Bhat2016-03-09-0/+13
* | dts:exynos:update pinctrl size-cells and fix child regsPrzemyslaw Marczak2016-03-17-29/+29
* | x86: Add congatec conga-QA3/E3845-4G (Bay Trail) supportStefan Roese2016-03-17-0/+283
* | x86: Add support for the samus chromebookSimon Glass2016-03-17-0/+629
* | x86: Support a chained-boot development flowSimon Glass2016-03-17-0/+80
* | x86: dts: Drop memory SPD compatible stringSimon Glass2016-03-17-1/+0
* | x86: ivybridge: Convert to use the common SDRAM codeSimon Glass2016-03-17-311/+83
* | x86: Add common SDRAM-init codeSimon Glass2016-03-17-0/+327
* | x86: Move common PCH code into a common placeSimon Glass2016-03-17-84/+99
* | arm: Add a 64-bit division routine to the private librarySimon Glass2016-03-17-1/+247
* | x86: Add a function to set the IOAPIC IDSimon Glass2016-03-17-0/+18
* | x86: broadwell: Add support for high-speed I/O lane with MESimon Glass2016-03-17-0/+58
* | x86: broadwell: Add support for SDRAM setupSimon Glass2016-03-17-0/+509
* | x86: broadwell: Add power-control supportSimon Glass2016-03-17-0/+220
* | x86: broadwell: Add reference code supportSimon Glass2016-03-17-0/+114
* | x86: broadwell: Add an LPC driverSimon Glass2016-03-17-0/+110
* | x86: broadwell: Add a northbridge driverSimon Glass2016-03-17-0/+60
* | x86: broadwell: Add a SATA driverSimon Glass2016-03-17-0/+270
* | x86: broadwell: Add a pinctrl driverSimon Glass2016-03-17-0/+370
* | x86: broadwell: Add a PCH driverSimon Glass2016-03-17-0/+839
* | x86: Add basic support for broadwellSimon Glass2016-03-17-0/+1246
* | x86: Add support for running Intel reference codeSimon Glass2016-03-17-0/+23
* | x86: Drop all the old pin configuration codeSimon Glass2016-03-17-141/+0
* | x86: Add an ICH6 pin configuration driverSimon Glass2016-03-17-0/+218
* | x86: link: Add pin configuration to the device treeSimon Glass2016-03-17-0/+155
* | x86: Update microcode for secondary CPUsSimon Glass2016-03-17-2/+12
* | x86: ivybridge: Show microcode version for each coreSimon Glass2016-03-17-1/+2
* | x86: Record the CPU details when starting each coreSimon Glass2016-03-17-1/+20
* | x86: Move common MRC Kconfig options to the common fileSimon Glass2016-03-17-26/+62
* | x86: Allow I/O functions to use pointersSimon Glass2016-03-17-2/+10
* | x86: Add macros to clear and set I/O bitsSimon Glass2016-03-17-0/+22
* | x86: ivybridge: Drop sandybridge_early_init()Simon Glass2016-03-17-2/+0
* | x86: Move Intel Management Engine code to a common placeSimon Glass2016-03-17-369/+418
* | x86: Rename PORT_RESET to IO_PORT_RESETSimon Glass2016-03-17-5/+5
* | x86: Move common CPU code to its own placeSimon Glass2016-03-17-76/+162
* | x86: Move common LPC code to its own placeSimon Glass2016-03-17-85/+166
* | x86: Add the root-complex block to common intel registersSimon Glass2016-03-17-7/+9
* | x86: Create a common header for Intel register accessSimon Glass2016-03-17-6/+22
* | x86: Move microcode code to a common locationSimon Glass2016-03-17-4/+8
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