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* powerpc: BSC9132QDS: Remove CONFIG_BSC9132QDS macroYork Sun2016-11-23-2/+2
| | | | | | | Use CONFIG_TARGET_BSC9132QDS from Kconfig option, remove CONFIG_BSC9132QDS macro. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: BSC9131/2: Move CONFIG_BSC9131/2 to Kconfig optionsYork Sun2016-11-23-15/+23
| | | | | | | | | Replace CONFIG_BSC9131, CONFIG_BSC9132 with ARCH_BSC9131, ARCH_BSC9132 Kconfig options. Also drop #ifdef in BSC9131RDB.h since it is redundant. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: MPC8544: Move CONFIG_MPC8544 to Kconfig optionYork Sun2016-11-23-4/+9
| | | | | | Replace CONFIG_MPC8544 with ARCH_MPC8544 in Kconfig. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: MPC8548: Move CONFIG_MPC8548 to Kconfig optionYork Sun2016-11-23-7/+13
| | | | | | Replace CONFIG_MPC8548 with ARCH_MPC8548 in Kconfig. Signed-off-by: York Sun <york.sun@nxp.com>
* Merge tag 'signed-efi-next' of git://github.com/agraf/u-bootTom Rini2016-11-17-30/+687
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | Patch queue for efi - 2016-11-17 Highlights this time around: - x86 efi_loader support - hello world efi test case - network device name is now representative - terminal output reports modes correctly - fix psci reset for ls1043/ls1046 - fix efi_add_runtime_mmio definition for x86 - efi_loader support for ls2080
| * armv8: fsl-layerscape: Add support for efi_loader RTS resetAlexander Graf2016-11-17-2/+31
| | | | | | | | | | | | | | | | | | | | When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls2080a: Declare spin tables as reserved for efi loaderAlexander Graf2016-11-17-0/+6
| | | | | | | | | | | | | | | | The efi loader code has its own memory map, so it needs to be aware where the spin tables are located, to ensure that no code writes into those regions. Signed-off-by: Alexander Graf <agraf@suse.de>
| * ls2080: Exit dpaa only right before exiting U-BootAlexander Graf2016-11-17-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On ls2080 we have a separate network fabric component which we need to shut down before we enter Linux (or any other OS). Along with that also comes configuration of the fabric using a description file. Today we always stop and configure the fabric in the boot script and (again) exit it on device tree generation. This works ok for the normal booti case, but with bootefi the payload we're running may still want to access the network. So let's add a new fsl_mc command that defers configuration and stopping the hardware to when we actually exit U-Boot, so that we can still use the fabric from an EFI payload. For existing boot scripts, nothing should change with this patch. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> [agraf: Fix x86 build]
| * efi_loader: Disable PSCI reset for ls1043 and ls1046Alexander Graf2016-11-17-2/+3
| | | | | | | | | | | | | | The NXP ls1043 and ls1046 systems do not (yet) have PSCI enablement for reset. Don't enable generic PSCI reset code on them. Signed-off-by: Alexander Graf <agraf@suse.de>
| * efi: x86: Adjust EFI files support efi_loaderSimon Glass2016-11-14-4/+21
| | | | | | | | | | | | | | | | | | Add compiler flags and make a few minor adjustments to support the efi loader. Signed-off-by: Simon Glass <sjg@chromium.org> [agraf: Add Kconfig dep] Signed-off-by: Alexander Graf <agraf@suse.de>
| * x86: Move efi .S files into the 'lib' directorySimon Glass2016-11-14-19/+19
| | | | | | | | | | | | | | | | These files now need to be in a standard place so that they can be located by generic Makefile rules. Move them to the 'lib' directory. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Alexander Graf <agraf@suse.de>
| * x86: Move efi .lds files into the 'lib' directorySimon Glass2016-11-14-1/+1
| | | | | | | | | | | | | | | | These files now need to be in a standard place so that they can be located by generic Makefile rules. Move them to the 'lib' directory. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Alexander Graf <agraf@suse.de>
| * efi: arm: Add aarch64 EFI app supportSimon Glass2016-11-14-0/+296
| | | | | | | | | | | | | | | | | | Add support for EFI apps on aarch64. This includes start-up and relocation code plus a link script. Signed-off-by: Simon Glass <sjg@chromium.org> [agraf: add kconfig dep] Signed-off-by: Alexander Graf <agraf@suse.de>
| * efi: arm: Add EFI app supportSimon Glass2016-11-14-0/+291
| | | | | | | | | | | | | | | | | | Add support for EFI apps on ARM. This includes start-up and relocation code, plus a link script and some compiler setting changes. Signed-off-by: Simon Glass <sjg@chromium.org> [agraf: Remove whitespace change, add kconfig dep] Signed-off-by: Alexander Graf <agraf@suse.de>
| * elf: arm: Add a few ARM relocation typesSimon Glass2016-11-14-2/+4
| | | | | | | | | | | | | | | | Rather than hard-coding the relocation type, add it to the ELF header file and use it from there. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Alexander Graf <agraf@suse.de>
| * x86: Correct a build warning in x86 tablesSimon Glass2016-11-14-0/+2
| | | | | | | | | | | | | | | | | | There is a build warning for three x86 boards since write_smbios_table_wrapper() is not used. Fix it. Fixes: e824cf3f (smbios: Allow compilation on 64bit systems) Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Alexander Graf <agraf@suse.de>
* | ARM64: zynqmp: Adding prefetchable memory space to pcieBharat Kumar Gogada2016-11-15-2/+3
| | | | | | | | | | | | | | | | | | | | Adding prefetchable memory space to pcie device tree node. Shifting configuration space to 64-bit address space. Removing pcie device tree node from amba as it requires size-cells=<2> in order to access 64-bit address space. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add clocks for LPDDMAKedareswara rao Appana2016-11-15-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Zynqmp DMA driver expects two clocks (main clock and apb clock) For LPDDMA channels the two clocks are missing in the Dma node resulting probe failure. xilinx-zynqmp-dma ffa80000.dma: main clock not found. xilinx-zynqmp-dma ffa80000.dma: Probing channel failed xilinx-zynqmp-dma: probe of ffa80000.dma failed with error -2 This patch fixes this issue. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add description for LPDDMA channel usageKedareswara rao Appana2016-11-15-1/+4
| | | | | | | | | | | | | | | | | | | | | | LPDDMA default allows only secured access. inorder to enable these dma channels, one should ensure that it allows non secure access. This patch updates the same. Reported-by: Sai Pavan Boddu <saipava@xilinx.com> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Use 64bit size cell format for main amba busMichal Simek2016-11-15-65/+65
| | | | | | | | | | | | | | Use 64bit size cell for main amba bus instead of 32bit because PCIe node requires it Change 64bit sizes also for all others IPs. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add ocm node in dtsiNaga Sureshkumar Relli2016-11-15-0/+7
| | | | | | | | | | | | | | | | This patch adds ocm controller node in zynqmp.dtsi. needed for OCM edac support. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add device tree properties for ZynqMP GT coreAnurag Kumar Vulisha2016-11-15-0/+23
| | | | | | | | | | | | | | | | | | This patch adds the ZynqMP GT core device-tree properties for zynqmp.dtsi file. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Tested-by: Hyun Kwon <hyunk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Revert "ARM64: zynqmp: Added broken-tuning property to SD, eMMC nodes"Michal Simek2016-11-15-2/+0
| | | | | | | | | | | | | | | | | | | | This reverts commit bd750e7a6c515c081b72d4ef108a2bfa691a3fd1 Implemented the new workaround for auto tuning based on zynqmp compatible string, so removed the 'broken-tuning' property. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: change sdhci compatible string.Sai Krishna Potthuri2016-11-15-2/+9
| | | | | | | | | | | | | | | | This patch changes the compatible string for sdhci node, adds "xlnx,device_id" and "xlnx,mio_bank" property to sdhci node. Signed-off-by: Sai Krishna Potthuri <lakshmis@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: List all SMMU idsMichal Simek2016-11-15-1/+72
| | | | | | | | | | | | Add SMMU description for all tested IPs. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add support for zynqmp fpga managerNava kishore Manne2016-11-15-0/+4
| | | | | | | | | | | | | | Add support for zynqmp fpga manager. Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add cortexa53 edac nodeNaga Sureshkumar Relli2016-11-15-0/+4
| | | | | | | | | | | | | | | | This patch adds edac node for arm cortexa53 to report errors on L1 and L2 caches. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Revert "ARM64: zynqmp: Add serdes address space dp driver"Michal Simek2016-11-15-2/+1
| | | | | | | | | | | | | | | | | | | | | | This reverts commit 786db82bd5bf09cc8f78c8b14445e843d7566b1c. Since we are using serdes driver , no need of mapping serdes register space into DP driver. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Tested-by: Hyun Kwon <hyunk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: drm: Add DMA indexHyun Kwon2016-11-15-3/+5
| | | | | | | | | | | | | | | | Each plane can be associated with multiple DMA channels. So add index for each DMA channel. Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Sync gpio node propertiesMichal Simek2016-11-15-2/+2
| | | | | | | | | | | | Keep dtsi in sync with mainline kernel. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Remove xlnx,id propertyMichal Simek2016-11-15-16/+0
| | | | | | | | | | | | | | Remove unused xlnx,id property because it is not the part of DT binding. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: pci: Updating device tree as per upstreamBharat Kumar Gogada2016-11-15-1/+4
| | | | | | | | | | | | | | | | Updating required device tree changes as per mainlined driver from 4.6 kernel. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Support for multiple PM IDs assigned to a PM domainFilip Drazic2016-11-15-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, it was assumed that there is a 1:1 mapping between PM ID defined in the platform firmware and a PM domain. However, there can be a situation where multiple PM IDs belong to a single PM domain (e.g. PM IDs for GPU and two pixel processors correspond to a single PM domain). This patch adds support for assigning more than one PM ID to a single PM domain. Updated documentation accordingly. Assigned pixel processors PM IDs to GPU PM domain. Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: DT: Add PM domains for GPU and PCIEFilip Drazic2016-11-15-0/+12
| | | | | | | | | | | | Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: DT: Remove unused PM domains for PLLFilip Drazic2016-11-15-25/+0
| | | | | | | | | | | | Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: DT: Remove unused DDR PM domainFilip Drazic2016-11-15-5/+0
| | | | | | | | | | | | | | | | | | | | DDR power states are handled by the PM firmware, so this domain is redundant. Also, since there is no device using this PM domain, it will be powered off during boot, which is wrong. Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Remove note about level shifter on zcu102Michal Simek2016-11-15-1/+1
| | | | | | | | | | | | i2c device is just level shifter. Remove reference from dts. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add dcc port to dtsiMichal Simek2016-11-15-0/+11
| | | | | | | | | | | | | | | | Add dcc to dtsi for supporting system without serial port. DCC is enabled by default on ZynqMP. Adding dcc to zcu100 and zcu102 which were tested. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add gpio-keys for zcu102Michal Simek2016-11-15-0/+15
| | | | | | | | | | | | | | There is gpio push button on MIO22. Add it to DTS to have full board description. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Enable gpio-led as heartbeat on zcu102Michal Simek2016-11-15-0/+9
| | | | | | | | | | | | Show user that Linux is alive on the board. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Enable can1 for ep108Naga Sureshkumar Relli2016-11-15-0/+8
| | | | | | | | | | | | | | | | This patch enables can1 for ep108. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Reviewed-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Added clocks to DT for ep108VNSL Durga2016-11-15-0/+44
| | | | | | | | | | | | | | Added clks for ep108 platform. Signed-off-by: VNSL Durga <vnsldurg@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add clocks for LPDDMAKedareswara rao Appana2016-11-15-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | Zynqmp DMA driver expects two clocks (main clock and apb clock) LPDDMA clock cofiguration is missing for the same in the zynqmp-clk.dtsi file. This patch updates for the same. Reported-by: Sai Pavan Boddu <saipava@xilinx.com> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Remove DTC 1.4.2 warningsMichal Simek2016-11-15-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DTC 1.4.2 reports these warnings: Warning (unit_address_vs_reg): Node /amba_apu has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /amba has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /amba/usb@fe200000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/usb@fe300000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-video0channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-video1channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-video2channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-graphicschannel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-audio0channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-audio1channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name This patch is fixing them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: Remove DTC 1.4.2 warningsMichal Simek2016-11-15-14/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | DTC 1.4.2 reports these warnings: Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /pmu has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /fixedregulator@0 has a unit name, but no reg property This patch is fixing them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Fix secondary bootmode enablingMichal Simek2016-11-15-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Do not setup use_alt bit which copy alternative boot mode to boot mode. The reason is that this bit is cleared after POR but not after any software reset which will cause that after SW reset bootrom will look for different boot image. This patch setups alternative boot mode selection (purely SW handling) and extends code to read this alternative boot mode first and use it if it is setup. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add support for SD1 with level shifters bootmodeSiva Durga Prasad Paladugu2016-11-15-0/+1
| | | | | | | | | | | | | | Add support for SD1 with level shifters bootmode. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | zynq: nand: Runtime detection of nand buswidth through slcrMichal Simek2016-11-15-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support to check the buswidth on nand flash at runtime based on nand MIO configurations done by FSBL. User needs to correctly configure the MIO's based on the buswidth supported by the nand flash which is present on the board. Added nand8 and nand16 @periph names on slcr driver. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: Add support for the topic-miami system-on-modules and carrier boardsMike Looijmans2016-11-15-0/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The topic-miami SoMs contain a Zynq xc7z015 or xc7z030 SoC, 1GB DDR3L RAM, 32MB QSPI NOR flash and 256MB NAND flash. The topic-miamiplus SoMs contain a Zynq xc7z035, xc7z045 or xc7z100 SoC, 2x 1GB DDR3L RAM, 64MB dual-parallel QSPI flash, clock sources and a fan controller. The "Florida" carrier boards add SD, USB, ethernet and other interfaces. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: Make SYS_VENDOR configurableMike Looijmans2016-11-15-0/+1
| | | | | | | | | | | | | | | | Add a string description for SYS_VENDOR to allow configuring boards from other vendors than just "xilinx". Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
generated by cgit v1.1 at 2024-07-16 09:27:53 +0000