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* ARM: at91/dt: Add device tree for SAMA5D2 XplainedWenyou Yang2016-08-15-0/+874
| | | | | | Add device tree for SAMA5D2 Xplained board. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
* atmel: Bring in at91 pio4 device tree file and bindingsWenyou Yang2016-08-15-0/+880
| | | | | | | | Bring in required device tree file and bindings from Linux. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* gpio: atmel_pio4: Move PIO4 definitions to head fileWenyou Yang2016-08-15-0/+35
| | | | | | | | | In order to make these PIO4 definitions shared with AT91 PIO4 pinctrl driver, move them from the existing gpio driver to the head file, and rephrase them. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* clk: at91: Add clock driverWenyou Yang2016-08-15-3/+8
| | | | | | | | The patch is referred to at91 clock driver of Linux, to make the clock node descriptions in DT aligned with the Linux's. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* kconfig: use bool instead of boolean for type definition attributesMasahiro Yamada2016-08-12-5/+5
| | | | | | | | | | Linux stopped the use of keyword 'boolean' in Kconfig. Refer to commit 6341e62b212a2541efb0160c470e90bd226d5496 ("kconfig: use bool instead of boolean for type definition attributes") in Linux Kernel. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: dts: dra7xx-evm: add evm_3v3_sd regulatorVignesh R2016-08-12-2/+22
| | | | | | | | | | Add a node for evm_3v3_sd using onboard PCF GPIO expander which feeds on to mmc vdd. Update mapping for vmmc-supply and vmmc_aux-supply. evm_3v3_sd supplies to SD card vdd, and ldo1 to sdcard i/o lines. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* drivers/sysreset: group sysreset driversMax Filippov2016-08-12-181/+0
| | | | | | | | Create drivers/sysreset and move sysreset-uclass and all sysreset drivers there. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* ARM: non-sec: flush code cacheline alignedStefan Agner2016-08-12-1/+3
| | | | | | | | | | Flush operations need to be cacheline aligned to take effect, make sure to flush always complete cachelines. This avoids messages such as: CACHE: Misaligned operation at range [00900000, 009004d9] Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
* Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2016-08-11-172/+527
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| * ARM: uniphier: add PSCI support for UniPhier ARMv7 SoCsMasahiro Yamada2016-08-11-2/+269
| | | | | | | | | | | | Currently, only the CPU_ON function is supported. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: add uniphier_cache_set_active_ways()Masahiro Yamada2016-08-11-1/+22
| | | | | | | | | | | | | | | | This outer cache allows to control active ways independently for each CPU, so this function will be useful to set up active ways for a specific CPU. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: add uniphier_cache_inv_way() to support way invalidationMasahiro Yamada2016-08-11-1/+10
| | | | | | | | | | | | This invalidates entries in specified ways of the outer cache. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: move (and rename) CONFIG_UNIPHIER_L2CACHE_ON to KconfigMasahiro Yamada2016-08-11-1/+8
| | | | | | | | | | | | | | Move this option to Kconfig, renaming it into CONFIG_CACHE_UNIPHIER. The new option name makes sense enough, and the same as Linux has. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: move outer cache register macros to .c fileMasahiro Yamada2016-08-11-69/+55
| | | | | | | | | | | | | | Now, all of these macros are only used in cache-uniphier.c, so there is no need to export them in a header file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: reuse uniphier_cache_disable() for lowlevel_initMasahiro Yamada2016-08-11-7/+3
| | | | | | | | | | | | | | The DRAM is available at this point, so setup the temporary stack and call the C function to reduce the code duplication a bit. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: export uniphier_cache_enable/disable functionsMasahiro Yamada2016-08-11-10/+26
| | | | | | | | | | | | | | | | The System Cache (outer cache) is used not only as L2 cache, but also as locked SRAM. The functions for turning on/off it is necessary whether the L2 cache is enabled or not. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: move lowlevel debug init code after page table switchMasahiro Yamada2016-08-11-4/+4
| | | | | | | | | | | | | | | | | | As the sLD3 Boot ROM has a complex page table, it is difficult to set up the debug UART with enabling it. It will be much easier to initialize the UART port after switching over to the straight-mapped page table. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: fix ROM boot mode for PH1-sLD3Masahiro Yamada2016-08-11-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 4b50369fb535 ("ARM: uniphier: create early page table at run-time") broke the ROM boot mode for PH1-sLD3 SoC, because the run-time page table creation requires the outer cache register access but the page table in the sLD3 Boot ROM does not straight-map virtual/physical addresses. The idea here is to check the current page table to determine if it is a straight map table. If not, adjust the outer cache register base. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: refactor L2 zero-touching code in lowlevel_initMasahiro Yamada2016-08-11-26/+22
| | | | | | | | | | | | | | Here, the ldr pseudo-instruction falls into the ldr + data set. The register access by [r1, #offset] produces shorter code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: do not compile v7_outer_cache_disable if L2 is disabledMasahiro Yamada2016-08-11-1/+1
| | | | | | | | | | | | | | | | If CONFIG_UNIPHIER_L2CACHE_ON is undefined, the L2 cache is never enabled, so there is no need for v7_outer_cache_disable(). The weak stub avoids the compile error anyway. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: support prefetch and touch operations for outer cacheMasahiro Yamada2016-08-11-10/+57
| | | | | | | | | | | | | | | | | | | | The UniPhier outer cache (L2 cache on ARMv7 SoCs) can be used as SRAM by locking ways. These functions will be used to transfer the trampoline code for SMP into the locked SRAM. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: refactor outer cache codeMasahiro Yamada2016-08-11-47/+52
| | | | | | | | | | | | | | | | | | Unify the range/all operation routines into the common function, uniphier_cache_maint_common(), and sync code with Linux a bit more. This reduces the code duplication. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-08-11-1/+1
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| * dm: ls1021a: dts: Update USB 3.0 node to support DM USBRajesh Bhagat2016-08-07-1/+1
| | | | | | | | | | | | Update USB 3.0 controller dts node in ls1021a.dtsi. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
* | Merge git://www.denx.de/git/u-boot-ppc4xxTom Rini2016-08-09-21/+45
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| * | ppc4xx: Fix platform supportDirk Eibach2016-08-09-21/+45
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit "ecc3066 Fix board init code to respect the C runtime environment" broke platform support for ppc4xx. start.S prepares a stackframe that is later rendered unusable by appending the reserved space for global data. Instead the reserved space has to be put first. Then the stackframe can be pushed. I can only test the 405EP OCM case. At least all other ppc4xx boards still build. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Stefan Roese <sr@denx.de>
* | ARM: dts: dra72-evm: Add mode-gpios entry for mac nodeVignesh R2016-08-08-1/+1
| | | | | | | | | | | | | | | | | | | | | | On DRA72 EVM, cpsw slave1 is muxed with VIN2A, hence switch to cpsw slave0 for ethernet. This is controlled by pcf gpio line. Add appropriate mode-gpios DT entry so that driver can select the required slave. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* | ARM: dts: dra7xx: Add u-boot specific property for PCF8575 nodesVignesh R2016-08-08-0/+3
|/ | | | | | | | | | PCF8575 does not have any registers hence, offset field needs to be ignored for i2c read/write. Therefore populate u-boot,i2c-offset-len with 0 in PCF8575 DT nodes. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-rockchipTom Rini2016-08-06-8/+775
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| * dts: rk3399: enable dwmmc for sdcardKever Yang2016-08-05-2/+6
| | | | | | | | | | | | | | | | | | rk3399 sdcard is using dwmmc controller, enable it for sdcard. SCLK_SDMMC is the clock for controller operation clock, move it to the first place. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: add support for rk3288 miniarm boardXu Ziyuan2016-08-05-2/+607
| | | | | | | | | | | | | | | | Miniarm is a rockchip rk3288 based development board, which has lots of interface such as HDMI, USB, micro-SD card, Audio etc. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rk3399: add basic soc driverKever Yang2016-08-05-0/+160
| | | | | | | | | | | | | | | | | | | | This patch add driver for: - clock driver including set_rate for cpu, mmc, vop, I2C. - sysreset driver - grf syscon driver Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: rockchip, sdram-channel 0xff fix remaining dtsSandy Patterson2016-08-05-2/+2
| | | | | | | | | | | | | | Add an extra byte so that this data is not byteswapped. Signed-off-by: Sandy Patterson <apatterson@sightlogix.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: add fastboot support for rk3036 boardXu Ziyuan2016-08-05-2/+0
| | | | | | | | | | | | | | | | Enable fastboot feature on rk3036, please refer to doc/README.rockchip for more detailed usage. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2016-08-05-10/+267
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| * | ARM: tegra: call tegra_board_init on Tegra186Stephen Warren2016-08-04-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce tegra_board_init() and call it from board_init(). Tegra wil use tegra_board_init() for board-specific initialization, and board_init() for SoC-specific initialization. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: add I2C controllers to Tegra186 DTBryan Wu2016-08-04-0/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra186 has 8 I2C controllers including BPMP I2C. This patch adds the other 7 generic controllers to Tegra186's DT. Signed-off-by: Bryan Wu <pengw@nvidia.com> (swarren, fixed DT node sort order, tweak patch description) Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: add PCIe controller to Tegra186 SoC DTStephen Warren2016-08-04-0/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Tegra186 PCIe DT content is almost identical to previous chips, except that the: - There are 3 ports instead of 2. - Some physical addresses have moved. - PHY programming is handled by firmware, so CCPLEX DTs don't need to reference any PHY. - The power domain is explicitly represented in DT. This change is mandatory for Tegra186 since standard power domain APIs are used, and should be made to the DT for older SoCs, although we get away without doing so since U-Boot currently uses custom APIs that hard-code power domain IDs. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: add BPMP I2C to Tegra186 device treeStephen Warren2016-08-04-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | This allows the BPMP I2C device to be instantiated, which makes it available to other drivers and the user. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: add BPMP and dependencies to Tegra186 DTStephen Warren2016-08-04-2/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the DT content that's needed to allow board DTs to enable use of BPMP, clocks, resets, GPIOs, eMMC, and SD cards. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: adapt to latest HSP DT bindingStephen Warren2016-08-04-7/+3
| |/ | | | | | | | | | | | | | | | | | | The DT binding for the Tegra186 HSP module apparently wasn't quite final when I posted initial U-Boot support for it. Add the final DT binding doc and adapt all code and DT files to match it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | armv8: mmu: Detect page table overflow in emergency pt creationAlexander Graf2016-08-05-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We create 2 sets of page tables: One for normal operation, one for emergency (used while modifying the former). Because the page tables grow dynamically, we have code that checks for overflow. Unfortunately we didn't adjust the available space variable while creating the emergency tables, so potentially someone might run into an overflow there (not seen in real world yet though!). Fix it by properly adjusting the size as well as the base offset in emergency page table creation. Reported-by: York Sun <york.sun@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com>
* | omap3: Drop omap3_evm_quick_* targetsTom Rini2016-08-05-6/+0
| | | | | | | | | | | | | | | | | | These config targets were added well before the Kconfig migration began as a way to demonstrate how to make these platforms work with cut down features. At this point in time they no longer serve a good purpose so remove them. Signed-off-by: Tom Rini <trini@konsulko.com>
* | omap3, omap4: Enable USE_TINY_PRINTF for allTom Rini2016-08-05-0/+2
| | | | | | | | | | | | | | | | | | In the case of omap3 we have a number of platforms that are close to exceeding SRAM limits, depending on compiler. Move to USE_TINY_PRINTF to give them more room. OMAP4 will soon enough be in a similar place, so enable that now. Signed-off-by: Tom Rini <trini@konsulko.com>
* | omap3: Move to select SUPPORT_SPL for allTom Rini2016-08-05-19/+1
| | | | | | | | | | | | | | In reality all omap3 platforms support SPL so move the select for this up a level. Signed-off-by: Tom Rini <trini@konsulko.com>
* | treewide: move CONFIG_PHYS_64BIT to KconfigMasahiro Yamada2016-08-05-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to ensure that CONFIG_PHYS_64BIT is configured via Kconfig so that it is always available to the build system. Otherwise we can run into cases where we have inconsistent sizes of certain attributes. Ravi Babu reported offset mismatch of struct dwc3 across files since commit 95ebc253e6d4 ("types.h: move and redefine resource_size_t"). Since the commit, resource_addr_t points to phys_addr_t, whose size is dependent on CONFIG_PHYS_64BIT for ARM architecture. I tried my best to use "select" where possible (for example, ARMv8 architecture) because I think this kind of option is generally user- unconfigurable. However, I see some of PowerPC boards have 36BIT defconfigs as well as 32BIT ones. I moved CONFIG_PHYS_64BIT to the defconfigs for such boards. CONFIG_36BIT is no longer referenced, so all of the defines were removed from CONFIG_SYS_EXTRA_OPTIONS. Fixes: 95ebc253e6d4 ("types.h: move and redefine resource_size_t") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reported-by: Ravi Babu <ravibabu@ti.com> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | ARM: Rework and correct barrier definitionsTom Rini2016-08-05-40/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As part of testing booting Linux kernels on Rockchip devices, it was discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for some cases incomplete isb definitions. This was causing a failure to boot of the Linux kernel. In order to solve this problem as well as cover any corner cases that we may also have had a number of changes are made in order to consolidate things. First, <asm/barriers.h> now becomes the source of isb/dsb/dmb definitions. This however introduces another complexity. Due to needing to build SPL for 32bit tegra with -march=armv4 we need to borrow the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete form. Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add a comment about it. Now that we can always know what the target CPU is capable off we can get always do the correct thing for the barrier. The final part of this is that need to be consistent everywhere and call isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the function names in others. Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Sandy Patterson <apatterson@sightlogix.com> Reported-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reported-by: Sandy Patterson <apatterson@sightlogix.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* | arc: Rename AXS101 board to more generic AXS10xAlexey Brodkin2016-08-05-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As of now we have 2 flavors of ARC SDP boards: 1) AXS101 - with ARC770 in ASIC 2) AXS103 - with ARC HS38 in FPGA Both options share exactly the same base-board and only differ with CPU-tiles in use. That means all peripherals are the same (they are implemented in FPGA on the base-board) and so generic board could be used for both. While at it: * Recreated defconfigs with savedefconfig * In include/configs/axs10x.h numerical sizes replaced with defines from linux/sizes.h for better readability. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arc: Rename ARCangel4 board to nSIMAlexey Brodkin2016-08-05-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARCangel was one of the main development boards back in the day but now it's gone and replaced by other boards like ARC SDP. But we also used to have simulation platform very similar to ARCangel4 in terms of CPU settings as well as basic IO like UART. Even though ARCangel4 is long gone now we have a replacement for simulation which is a plain or stand-alone nSIM and Free nSIM. Note Free nSIM is available for download here: https://www.synopsys.com/cgi-bin/dwarcnsim/req1.cgi And while at it: * Finally switch hex numerical values in nsim.h to defines from include/linux/sizes.h * Add defconfigs with ARC HS38 cores * Recreated all defconfigs with savedefconfig Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | arc: No need in sections defined in sources with newer toolsAlexey Brodkin2016-08-05-64/+18
| | | | | | | | | | | | | | | | Starting from arc-2016.03 GNU tools linker properly works with symbols defined in linker script and so external declarations are no longer required, dump them. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
generated by cgit v1.1 at 2024-07-19 22:10:53 +0000