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* powerpc/mpc85xx: Add board support for ucp1020Oleksandr G Zhadan2015-05-04-0/+4
| | | | | | | | | | New QorIQ p1020 based board support from Arcturus Networks Inc. http://www.arcturusnetworks.com/products/ucp1020/ Signed-off-by: Michael Durrant <mdurrant@arcturusnetworks.com> Signed-off-by: Oleksandr G Zhadan <oleks@arcturusnetworks.com> [York Sun: remove patman tags from commit message] Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Fix compiling error for common/cmd_gpio.cOleksandr G Zhadan2015-05-04-2/+6
| | | | | | | | | | | | | | | | | | | | To replicate: 1. add to include/configs/p1_p2_rdb_pc.h "#define CONFIG_CMD_GPIO" 2. run `make P1020RDB-PC_defconfig` 3. run CROSS_COMPILE=powerpc-linux- make and you will get: common/built-in.o: In function `do_gpio': u-boot/common/cmd_gpio.c:186: undefined reference to `gpio_request' u-boot/common/cmd_gpio.c:194: undefined reference to `gpio_direction_input' u-boot/common/cmd_gpio.c:195: undefined reference to `gpio_get_value' u-boot/common/cmd_gpio.c:200: undefined reference to `gpio_get_value' u-boot/common/cmd_gpio.c:203: undefined reference to `gpio_direction_output' u-boot/common/cmd_gpio.c:209: undefined reference to `gpio_free Signed-off-by: Michael Durrant <mdurrant@arcturusnetworks.com> Signed-off-by: Oleksandr G Zhadan <oleks@arcturusnetworks.com> Reviewed-by: York Sun <yorksun@freescale.com>
* mmc: fsl_esdhc: Add peripheral clock supportYangbo Lu2015-05-04-3/+56
| | | | | | | | | | | | The SD clock could be generated by platform clock or peripheral clock for some platforms. This patch adds peripheral clock support for T1024/T1040/T2080. To enable it, define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Cc: York Sun <yorksun@freescale.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Reviewed-by: York Sun <yorksun@freescale.com>
* mmc: fsl_esdhc: Add adapter card type identification supportYangbo Lu2015-05-04-0/+3
| | | | | | | | | | | | Add adapter card type identification support by reading FPGA STAT_PRES1 register SDHC Card ID[0:2] bits. To use this function, define CONFIG_FSL_ESDHC_ADAPTER_IDENT. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Cc: York Sun <yorksun@freescale.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> [York Sun: resolve conflicts in README.fsl-esdhc] Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Don't deref NULL if qman portal lacks cell-indexScott Wood2015-05-04-2/+7
| | | | | | Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Madalin-Cristian Bucur <madalin.bucur@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc: add 2 common dcache assembly functionsValentin Longchamp2015-05-04-164/+48
| | | | | | | | | | | | | | This patch defines the 2 flush_dcache_range and invalidate_dcache_range functions for all the powerpc architecture. Their implementation is borrowed from the kernel's misc_32.S file and replace the ones from mpc86xx and ppc4xx since they were equivalent. This is a fix for the problem introduced by this patch: http://patchwork.ozlabs.org/patch/448849/ Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <yorksun@freescale.com>
* fsl/pci: Set CFG_READY for PCIe v3.0 and laterMinghuan Lian2015-05-04-0/+1
| | | | | | | | | | | | | | Freescale PCIe controllers v3.0 and later need to set bit CFG_READY to allow all inbound configuration transactions to be processed normally when in EP mode. However, bit CFG_READY has been moved from PCIe configuration space to CCSR PCIe configuration register comparing previous version. The patch is to set this bit according to PCIe version. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/t4rdb: Add SD boot support for T4240RDB boardChunhe Lan2015-05-04-0/+1
| | | | | | | | | | | | This patch adds SD boot support for T4240RDB board. SPL framework is used. PBL initializes the internal RAM and copies SPL to it. Then SPL initializes DDR using SPD and copies u-boot from SD card to DDR, finally SPL transfers control to u-boot. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> [York Sun: Fix T4240RDB_SDCARD_defcofig] Reviewed-by: York Sun <yorksun@freescale.com>
* drivers: usb: fsl: Workaround for Erratum A004477Nikhil Badola2015-05-04-0/+10
| | | | | | | | | | Add a delay of 1 microsecond before issuing soft reset to the controller to let ongoing ULPI transaction complete. This prevents corruption of ULPI Function Control Register which eventually prevents phy clock from entering to low power mode Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* mpc85xx/T4240EMU: Remove T4240EMU boardYork Sun2015-05-04-3/+0
| | | | | | | T4240 SoC has been available for a long time. Emulator support is no longer needed. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Use GOT when loading IVORs post-relocationScott Wood2015-05-04-15/+20
| | | | | | | | | | | | | | | | | | | | | Commit 96d2bb952bb ("powerpc/mpc85xx: Don't relocate exception vectors") simplified IVOR initialization a bit too much, failing to use the post-relocation offset. This doesn't cause a problem with normal NOR boot, in which both the pre-relocation and post-relocation addresses are 64 KiB aligned. However, if TEXT_BASE is only 4 KiB aligned, such as for NAND/SD/etc. boot on some targets, as well as the QEMU target, the post-relocation address will not be the same in the lower 16 bits, as reserve_uboot() ensures that the relocation address is always 64 KiB aligned even if the pre-relocation address was not. Use the GOT to get the proper post-relocation offsets. Fixes: 96d2bb952bb ("powerpc/mpc85xx: Don't relocate exception vectors") Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Alexander Graf <agraf@suse.de> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Tested-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblazeTom Rini2015-04-29-28/+594
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| * ARM: zynq: rename CONFIG_ZYNQ to CONFIG_ARCH_ZYNQMasahiro Yamada2015-04-29-4/+4
| | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM: zynq: move SoC headers to mach-zynq/include/machMasahiro Yamada2015-04-29-0/+0
| | | | | | | | | | | | | | | | Move arch/arm/include/asm/arch-zynq/* -> arch/arm/mach-zynq/include/mach/* Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM: zynq: move SoC sources to mach-zynqMasahiro Yamada2015-04-29-2/+2
| | | | | | | | | | | | | | Move arch/arm/cpu/armv7/zynq/* -> arch/arm/mach-zynq/* Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM: zynq: pass "-mfpu=neon" only to lowlevel_init.SMasahiro Yamada2015-04-29-7/+1
| | | | | | | | | | | | | | | | | | The comment line in arch/arm/cpu/armv7/zynq/config.mk says that the option "-mfpu=neon" is necessary for compiling lowlevel_init.S. We do not have to give it to all the source files. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * zynqmp: Enable SDHCI0 optionsMichal Simek2015-04-29-0/+12
| | | | | | | | | | | | | | Enable SDHCI0 for zynqmp. Add empty gpio.h because of sdhci requirement. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * zynqmp: Add SPI driver support for ZynqMPSiva Durga Prasad Paladugu2015-04-29-0/+3
| | | | | | | | | | | | | | | | | | Added the SPI driver support for ZynqMP The controller is same as zynq SPI controller Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * zynqmp: i2c: Enable i2c driver for zynqMPSiva Durga Prasad Paladugu2015-04-29-0/+3
| | | | | | | | | | | | | | | | | | | | Enable the i2c driver for ZynqMP Also enable the eeprom for read and writes to eeprom on ZynqMP ZynqMP uses the same i2c controller as in Zynq Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * zynqmp: Add support for EMMC bootmodeMichal Simek2015-04-29-1/+2
| | | | | | | | | | | | Add support for EMMC bootmode. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * zynqmp: Add support for emulation platform - VeloceMichal Simek2015-04-29-0/+6
| | | | | | | | | | | | | | Add support for Veloce - zynqmp emulation platform. Platform doesn't support SDHCI. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * zynq: timer: Fix wrong timer calculationSiva Durga Prasad Paladugu2015-04-29-1/+3
| | | | | | | | | | | | | | | | | | | | Fix wrong timer calculation in get_timer_masked incase of overflow. This fixes the issue of getting wrong time from get_timer() calls. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * zynqmp: Add support for R5 sw loadingMichal Simek2015-04-29-3/+283
| | | | | | | | | | | | | | Add support for loading sw for R5 with enabling for zynqmp. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
| * zynqmp: caches: Enable dcache for zynqmpSiva Durga Prasad Paladugu2015-04-29-0/+164
| | | | | | | | | | | | | | | | Define the mmu table till 2MB granularity enable dcaches for zynqmp. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * zynq: slcr: Disable all level shiftersSiva Durga Prasad Paladugu2015-04-29-0/+7
| | | | | | | | | | | | | | | | | | | | | | Disable all level shifters before enabling the PS-to-PL level shifters as it would be good to disable all level shifters before enabling the PS-to-PL in order to ensure that it is in proper state Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM: zynq: drop legacy ps7_init.c/h supportMasahiro Yamada2015-04-29-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We are about to change the location for ps7_init files, breaking the current work-flows. It is good time to drop the legacy ps7_init.c/h support. Going forward, please use ps7_init_gpl.c/h all the time. If you are still using old Xilinx tools that are only able to generate ps7_init.c/h, rename them into ps7_init_gpl.c/h. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Suggested-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * zynq: Add Zynq PicoZed board supportNathan Rossi2015-04-29-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PicoZed is a System-on-Module board which is marketed as part of the ZedBoard/MicroZed/etc. collection. It includes a Zynq-7000 processor. This patch adds support that covers all the variants of the PicoZed including the SKUs with Z7010/Z7020 and Z7015/Z7030 Zynq chips. This patch set however only covers support for the System-on-Module and does not cover any extra components that are available on carrier boards (except those that are fanned out of the module itself). More information on this board, its variants and available carrier boards is available at: http://zedboard.org/product/picozed Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * gpio: add Xilinx Zynq PS GPIO driverAndrea Scian2015-04-29-0/+66
| | | | | | | | | | | | | | | | | | Most of the code is taken (and adapted) from Linux kernel driver. Just add CONFIG_ZYNQ_GPIO to you config to enable it Signed-off-by: Andrea Scian <andrea.scian@dave.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-socfpgaTom Rini2015-04-28-47/+169
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| * | socfpga: implement arria V socdk SPI flash config in dtsPavel Machek2015-04-27-0/+24
| | | | | | | | | | | | | | | | | | | | | Arria V SocDK has same QSPI and SPI flash configuration as Socrates. Add support for it. Signed-off-by: Pavel Machek <pavel@denx.de>
| * | socfpga: implement socdk SPI flash config in dtsPavel Machek2015-04-24-0/+24
| | | | | | | | | | | | | | | | | | | | | SocDK has same QSPI and SPI flash configuration as Socrates. Add support for it. Signed-off-by: Pavel Machek <pavel@denx.de>
| * | arm: socfpga: spl: Add stub sdram.hMarek Vasut2015-04-21-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the SoCFPGA SDRAM support is not yet applied to u-boot, we still need to be able to compile the codebase. Introduce stub functions which temporarily supplement the missing SDRAM setup functions. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Vince Bridgers <vbridger@opensource.altera.com>
| * | arm: socfpga: spl: add board_init_f to SPLDinh Nguyen2015-04-21-0/+29
| | | | | | | | | | | | | | | | | | | | | Remap SDRAM to 0x0, and clear OCRAM's ECC in board_init_f(). Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Reviewed-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: spl: Add SDRAM checkDinh Nguyen2015-04-21-0/+6
| | | | | | | | | | | | Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
| * | arm: socfpga: spl: Use common lowlevel_initDinh Nguyen2015-04-21-47/+1
| | | | | | | | | | | | | | | | | | | | | For SoCFGPA, use the common ARMv7 lowlevel_init. Thus, we can delete the SoCFPGA lowlevel_init.S file. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
| * | arm: socfpga: spl: printout sdram sizeDinh Nguyen2015-04-21-0/+4
| | | | | | | | | | | | | | | Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Reviewed-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: spl: add sdram init and calibrationDinh Nguyen2015-04-21-0/+13
| | | | | | | | | | | | | | | | | | Add a call to checkboard along with sdram intilialization and calibration. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
| * | arm: socfpga: spl: allow bootrom to enable IOs after warm resetDinh Nguyen2015-04-21-0/+13
| | | | | | | | | | | | | | | Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: spl: Add call to timer_initDinh Nguyen2015-04-21-0/+2
| | | | | | | | | | | | Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
| * | arm: socfpga: spl: enable sdram, timer and uartDinh Nguyen2015-04-21-0/+4
| | | | | | | | | | | | | | | | | | | | | Add the calls in the spl_board_init to enable SDRAM, timer, and UART. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: add functions to bring sdram, timer, and uart out of resetDinh Nguyen2015-04-21-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | These functions will be needed for use by the SPL for enabling the console and sdram initialization. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-04-28-24/+19
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| * | mx6: Add initial SPL support for HummingBoard-i2eXFabio Estevam2015-04-22-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the initial SPL support for HummingBoard-i2eX, which is based on a MX6 Dual. For more information about HummingBoard, please check: http://www.solid-run.com/products/hummingboard/ Based on the work from Jon Nettleton and Rabeeh Khoury. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | arm: mx6: ddr: add pd_fast_exit flag to system informationTim Harvey2015-04-22-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DDR3 has a special Precharge power-down mode: fast-exit vs slow-exit. In slow-exit mode the DLL is off but in some quiescent state that makes it easy to turn on again in tXPDLL cycles (about 10tCK) vs the full tDLLK (512tCK). In fast-exist mode the DLL is maintained such that it is ready again in about 3tCK. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * | ARM: mxs: Get boot mode from OCRAMJörg Krause2015-04-22-23/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reading the boot mode pins after power-up does not necessarily represent the boot mode used by the ROM loader. For example the state of a pin may have changed because a recovery switch which was pressed to enter USB mode is already released after plugging in USB. The ROM loader stores the value a fixed address in OCRAM. Use this value instead of reading the boot map pins. The GLOBAL_BOOT_MODE_ADDR for i.MX28 is taken from an U-Boot patch for the MX28EVK: http://repository.timesys.com/buildsources/u/u-boot/u-boot-2009.08/u-boot-2009.08-mx28-201012211513.patch Leave the boot mode detection for the i.MX23 untouched. Someone has to test whether the i.MX ROM loader does also store the boot mode in OCRAM and if the address match. This patch superseeds my incorrect patch: ARM: mxs: get boot mode from OTP http://patchwork.ozlabs.org/patch/454930/ Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks> Cc: Stefano Babic <sbabic@denx.de>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2015-04-24-7/+8
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| * | | MIPS: implement device-tree handover to Linux kernelDaniel Schwierzeck2015-04-24-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add device-tree handover to Linux kernel conforming with MIPS UHI [1]. Register $a0 will be set to the reserved value -2. The address of the device-tree blob will be stored as KSEG0 address in $a1. $a2 and $a3 are set to zero. [1] http://prplfoundation.org/wiki/MIPS_documentation Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-04-24-316/+956
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| * | | armv8/fsl-lsch3: Implement workaround for I2C erratum A009203York Sun2015-04-23-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This erratum requires setting GLITCH_EN bit in debug register to enable digital filter to improve clock stability. Signed-off-by: York Sun <yorksun@freescale.com> CC: Heiko Schocher <hs@denx.de>
| * | | ls2085a: esdhc: Add esdhc support for ls2085aYangbo Lu2015-04-23-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds esdhc support for ls2085a. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-08-23 08:15:43 +0000