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* x86: cache: define ARCH_DMA_MINALIGN for DMA buffer alignmentAnton Staaf2011-10-23-0/+35
| | | | | | | Signed-off-by: Anton Staaf <robotboy@chromium.org> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Graeme Russ <graeme.russ@gmail.com>
* mips: cache: define ARCH_DMA_MINALIGN for DMA buffer alignmentAnton Staaf2011-10-23-0/+36
| | | | | | | Signed-off-by: Anton Staaf <robotboy@chromium.org> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Shinya Kuribayashi <skuribay@pobox.com>
* microblaze: cache: define ARCH_DMA_MINALIGN for DMA buffer alignmentAnton Staaf2011-10-23-0/+37
| | | | | | | Signed-off-by: Anton Staaf <robotboy@chromium.org> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Michal Simek <monstr@monstr.eu>
* avr32: cache: define ARCH_DMA_MINALIGN for DMA buffer alignmentAnton Staaf2011-10-23-0/+40
| | | | | | | Signed-off-by: Anton Staaf <robotboy@chromium.org> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Reinhard Meyer <u-boot@emk-elektronik.de>
* sparc: cache: define ARCH_DMA_MINALIGN for DMA buffer alignmentAnton Staaf2011-10-23-0/+10
| | | | | | | Signed-off-by: Anton Staaf <robotboy@chromium.org> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Daniel Hellstrom <daniel@gaisler.com>
* sh: cache: define ARCH_DMA_MINALIGN for DMA buffer alignmentAnton Staaf2011-10-23-0/+17
| | | | | | | Signed-off-by: Anton Staaf <robotboy@chromium.org> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* powerpc: cache: define ARCH_DMA_MINALIGN for DMA buffer alignmentAnton Staaf2011-10-23-0/+6
| | | | | | | | | Signed-off-by: Anton Staaf <robotboy@chromium.org> Acked-by: Stefan Roese <sr@denx.de> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de>
* nios2: cache: define ARCH_DMA_MINALIGN for DMA buffer alignmentAnton Staaf2011-10-23-0/+11
| | | | | | | Signed-off-by: Anton Staaf <robotboy@chromium.org> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Scott McNutt <smcnutt@psyent.com>
* m68k: cache: define ARCH_DMA_MINALIGN for DMA buffer alignmentAnton Staaf2011-10-23-0/+10
| | | | | | | Signed-off-by: Anton Staaf <robotboy@chromium.org> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Jason Jin <jason.jin@freescale.com>
* arm: cache: define ARCH_DMA_MINALIGN for DMA buffer alignmentAnton Staaf2011-10-23-0/+11
| | | | | | | Signed-off-by: Anton Staaf <robotboy@chromium.org> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
* build: add missing $(AR)->$(cmd_link_o_target) updateMike Frysinger2011-10-22-3/+3
| | | | | | | | | Seems people fixed their files to use libfoo.o, but didn't actually update the creation targets to use $(cmd_link_o_target). Update the rest of the Makefile's found with grep. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Tested-by: Simon Glass <sjg@chromium.org>
* consolidate mdelay by providing a common function for all usersAnatolij Gustschin2011-10-22-12/+0
| | | | | | | | | There are several mdelay() definitions in the driver and board code. Remove them all and provide a common mdelay() in lib/time.c. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Mike Frysinger <vapier@gentoo.org>
* nds32/lib: add generic funcs in NDS32 libMacpaul Lin2011-10-22-0/+890
| | | | | | | Add Makefile, board.c, interrupts.c and bootm.c functions to nds32 architecture. Signed-off-by: Macpaul Lin <macpaul@andestech.com>
* nds32/ag101: cpu and init funcs of SoC ag101Macpaul Lin2011-10-22-0/+895
| | | | | | | | | | | | | SoC ag101 is the first chip using NDS32 N1213 cpu core. Add header file of device offset support for SoC ag101. Add main function of SoC ag101 based on NDS32 n1213 core. Add lowlevel_init.S and other periphal related code. This version of lowlevel_init.S also replace hardcode value by MARCO defines from the GPL version andesboot for better code quality. Signed-off-by: Macpaul Lin <macpaul@andestech.com>
* nds32/core N1213: NDS32 N12 core family N1213Macpaul Lin2011-10-22-0/+649
| | | | | | | | | | | | | Add N1213 cpu core (N12 Core family) support for NDS32 arch. This patch includes start.S for the initialize procedure of N1213. Start procedure: start.S will start up the N1213 CPU core at first, then jump to SoC dependent "lowlevel_init.S" and "watchdog.S" to configure peripheral devices. Signed-off-by: Macpaul Lin <macpaul@andestech.com> Signed-off-by: Greentime Hu <greentime@andestech.com>
* nds32: add header files support for nds32Macpaul Lin2011-10-22-0/+1450
| | | | | | | Add generic header files support for nds32 architecture. Cache, ptregs, data type and other definitions are included. Signed-off-by: Macpaul Lin <macpaul@andestech.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2011-10-21-26/+423
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-mpc85xx: mpc85xx: Add inline GPIO acessor functions powerpc/85xx: wait for alignment before resetting SERDES RX lanes (SERDES9) powerpc/85xx: Fix P2020DS booting powerpc/85xx: Update USB device tree status based on pin settings fdt: Add new fdt_set_node_status & fdt_set_status_by_alias helpers powerpc/85xx: Add support for RMan LIODN initialization powerpc/85xx: Update device tree handling for SRIO powerpc/85xx: Update setting of SRIO LIODNs fm: Don't allow disabling of FM1-DTSEC1 fm-eth: Don't mark the MAC we use for MDIO as disabled in device tree
| * mpc85xx: Add inline GPIO acessor functionsKyle Moffett2011-10-21-0/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To ease the implementation of other MPC85xx board ports, several common GPIO helpers are added to <asm/mpc85xx_gpio.h>. Since each of these compiles to no more than 4-5 instructions it would be very inefficient to call them out of line, therefore we put them entirely in the header file. The HWW-1U-1A board port which these were written for strongly prefers to set multiple GPIOs as a single batch operation, so the API is designed around that basis. To assist other board ports, a small set of wrappers are used which provides a standard gpio_request() interface around the MPC85xx-specific functions. This can be enabled with CONFIG_MPC85XX_GENERIC_GPIO Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> Cc: Andy Fleming <afleming@gmail.com> Cc: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: wait for alignment before resetting SERDES RX lanes (SERDES9)Timur Tabi2011-10-20-10/+0
| | | | | | | | | | | | | | | | The work-around for P4080 erratum SERDES9 says that the SERDES receiver lanes should be reset after the XAUI starts tranmitting alignment signals. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Update USB device tree status based on pin settingsShengzhou Liu2011-10-18-0/+23
| | | | | | | | | | | | | | | | | | For P3060 and P4080, USB pins are multiplexed with other functions. Update the device tree status for USB ports based on setting of RCW[EC1] & RCW[EC2] which describe if pins are muxed to usb. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add support for RMan LIODN initializationKumar Gala2011-10-18-0/+112
| | | | | | | | | | | | | | | | | | This patch is intended to initialize RMan LIODN related registers on P2041, P304S and P5020 SocS. It also adds the "rman@0" child node to qman-portal nodes, adds "fsl,liodn" property to RMan inbound block nodes. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Update device tree handling for SRIOKumar Gala2011-10-18-10/+93
| | | | | | | | | | | | | | | | | | | | | | Update device tree handling for SRIO controller to support updated fsl,srio device tree binding. We handle disabling of individual ports, the whole controller, RMU, and RMAN. Additionally, we setup the SRIO related LIODNs in the device tree. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Update setting of SRIO LIODNsKumar Gala2011-10-18-6/+72
| | | | | | | | | | | | | | | | | | | | | | Properly set the LIODN values associated with SRIO controller. On P4080/P3060 we have an LIODN per port and one for the RMU. On P2041/P3041/P5020 we have 2 LIODNs per port. Update the tables for all of these devices to properly handle both styles. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ColdFire: Add $(obj) before cpu lib to correct buildstany MARCEL2011-10-19-5/+5
|/ | | | | | | Missing $(obj) prevented the build of ColdFire boards in a directory than sources Signed-off-by: Stany MARCEL <stany.marcel@novasys-ingenierie.com>
* Move timestamp and version files into 'generated' subdirSimon Glass2011-10-17-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a rather subtle build problem where the build time stamp is not updated for out-of-tree builds if there exists an in-tree build which has a valid timestamp file. So if you do an in-tree build, then an out-of-tree build your timestamp will not change. The correct timestamp_autogenerated.h lives in the object tree, but it is not always found there. The source still lives in the source tree and when compiling version.h, it includes timestamp_autogenerated.h. Since the current directory is always searched first, this will come from the source tree rather than the object tree if it exists there. This affects dependency generation also, which means that common/cmd_version.o will not even be rebuilt if you have ever done an in-tree build. A similar problem exists with the version file. This change moves both files into the 'generated' subdir, which is already used for asm-offsets.h. Then timestamp.h and version.h are updated to include the files from there. There are other places where these generated files are included, but I cannot see why these don't just use the timestamp.h and version.h headers. So this change also tidies that up. I have tested this with in- and out-of-tree builds, but not SPL. I have looked at various other options for fixing this, including sed on the dep files, -I- and -include flags to gcc, but I don't think they can be made to work. Comments welcome. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Mike Frysinger <vapier@gentoo.org>
* sandbox: Add main programSimon Glass2011-10-17-1/+34
| | | | | | Add a main program so that we can run U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org>
* sandbox: Add OS dependent layerSimon Glass2011-10-17-5/+62
| | | | | | | We want to keep all OS-dependent code in once place, with a simple interface to U-Boot. For now, this is that place. Signed-off-by: Simon Glass <sjg@chromium.org>
* sandbox: Add architecture lib filesSimon Glass2011-10-17-0/+366
| | | | | | | | | | These files are taken from the ARM board implementation and then reduced to remove unneeded cruft. Ideally we would work towards unifying arch/xxx/lib files, particularly board.c. Signed-off-by: Simon Glass <sjg@chromium.org>
* sandbox: Add cpu filesSimon Glass2011-10-17-0/+164
| | | | | | | | This is an initial implementation with all functions defined but not working. The lds file is very simple since we can mostly rely on the linker defaults. Signed-off-by: Simon Glass <sjg@chromium.org>
* sandbox: Add architecture image supportSimon Glass2011-10-17-0/+3
| | | | | | | We won't actually load an image with this architecture, but we still need to define it. Signed-off-by: Simon Glass <sjg@chromium.org>
* sandbox: Add architecture header filesSimon Glass2011-10-17-0/+683
| | | | | | | This adds required header files for the sandbox architecture, and a basic description of what sandbox is (README.sandbox). Signed-off-by: Simon Glass <sjg@chromium.org>
* Blackfin: define CONFIG_SYS_CACHELINE_SIZEMike Frysinger2011-10-17-0/+74
| | | | | | | | Common U-Boot API wants this define, so import asm/cache.h from Linux to provide suitable defines. Acked-by: Anton Staaf <robotboy@chromium.org> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* mx31: make HSP clock for mx3fb driver availableHelmut Raiger2011-10-17-13/+42
| | | | | | | | | | | | This additionally updates mx31/generic.c by - replacing __REG() macro accesses with readl() and writel() - providing macros for PDR0 and PLL bit accesses Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> Acked-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Anatolij Gustschin <agust@denx.de>
* punt unused clean/distclean targetsMike Frysinger2011-10-15-24/+0
| | | | | | | | | | The top level Makefile does not do any recursion into subdirs when cleaning, so these clean/distclean targets in random arch/board dirs never get used. Punt them all. MAKEALL didn't report any errors related to this that I could see. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Merge branch 'master' of git://git.denx.de/u-boot-fdtWolfgang Denk2011-10-15-3/+2
|\ | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-fdt: powerpc/85xx: use fdt_create_phandle() to create the Fman firmware phandles fdt: update fdt_alloc_phandle to use fdt_get_phandle fdt: check for fdt errors in fdt_create_phandle fdt: Add a do_fixup_by_path_string() function
| * powerpc/85xx: use fdt_create_phandle() to create the Fman firmware phandlesTimur Tabi2011-10-15-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | Function fdt_create_phandle() conveniently creates new phandle properties using both "linux,phandle" and "phandle", so it should be used by all code that wants to create a phandle. The Fman firmware code, which embeds an Fman firmware into the device tree, was creating the phandle properties manually. Instead, change it to use fdt_create_phandle(). Signed-off-by: Timur Tabi <timur@freescale.com>
* | powerpc/p3060: remove all references to RCW bits EC1_EXT, EC2_EXT, and EC3Timur Tabi2011-10-13-30/+0
| | | | | | | | | | | | | | | | The EC1_EXT, EC2_EXT, and EC3 bits in the RCW don't officially exist on the P3060 and should always be set to zero. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/p3041: fixup portal config infoHaiying Wang2011-10-13-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | P3041 has 10 qman portals, we need to configure all of them: * As there are only 4 physical cores sdest can only be 0 to 3 * We assign dqrr & frame data LIODNs for all portals so if they are utilized the proper mapping tables can be setup uniquely (PAMU stashing) * We set Portal 6-10 to LIODN offsets 1-5 as the global LIODN assignments are tuned around an assumption of at most 5 partitions. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/p2041: fixup portal config infoHaiying Wang2011-10-13-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | P2041 has 10 qman portals, we need to configure all of them: * As there are only 4 physical cores sdest can only be 0 to 3 * We assign dqrr & frame data LIODNs for all portals so if they are utilized the proper mapping tables can be setup uniquely (PAMU stashing) * We set Portal 6-10 to LIODN offsets 1-5 as the global LIODN assignments are tuned around an assumption of at most 5 partitions. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/p5020: fixup portal config infoHaiying Wang2011-10-13-10/+10
|/ | | | | | | | | | | | | | P5020 has 10 qman portals, we need to configure all of them: * As there are only 2 physical cores sdest can only be 0 or 1 * We assign dqrr & frame data LIODNs for all portals so if they are utilized the proper mapping tables can be setup uniquely (PAMU stashing) * We set Portal 6-10 to LIODN offsets 1-5 as the global LIODN assignments are tuned around an assumption of at most 5 partitions. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of git://git.denx.de/u-boot-mipsWolfgang Denk2011-10-12-0/+2081
|\ | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-mips: MIPS: Jz4740: Add qi_lb60 board support MIPS: Jz4740: Add NAND driver MIPS: Ingenic XBurst Jz4740 processor support
| * MIPS: Ingenic XBurst Jz4740 processor supportXiangfu Liu2011-10-10-0/+2081
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Jz4740 is a multimedia application processor targeting for mobile devices like e-Dictionary, eBook, portable media player (PMP) and GPS navigator. Jz4740 is powered by Ingenic 360 MHz XBurst CPU core (JzRISC), in which RISC/SIMD/DSP hybrid instruction set architecture provides high integration, high performance and low power consumption. JzRISC incorporated in Jz4740 is the advanced and power-efficient 32-bit RISC core, compatible with MIPS32, with 16K I-Cache and 16K D-Cache, and can operate at speeds up to 400 MHz. On-chip modules such as LCD controller, embedded audio codec, multi- channel SAR-ADC, AC97/I2S controller and camera I/F offer a rich suite of peripherals for multimedia application. NAND controller (SLC/MLC), USB (host 1.1 and device 2.0), UART, I2C, SPI, etc. are also available. For more info about Ingenic XBurst Jz4740: http://en.ingenic.cn/eng/ http://www.linux-mips.org/wiki/Ingenic This patch introduces XBurst CPU support in U-Boot. It's compatible with MIPS32, but requires a bit different cache maintenance, timer routines, and boot mechanism using USB boot tool, so XBurst support can go into a separate new home, cpu/xburst/. Signed-off-by: Xiangfu Liu <xiangfu@openmobilefree.net> Acked-by: Daniel <zpxu@ingenic.cn> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-microblazeWolfgang Denk2011-10-12-17/+48
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-microblaze: microblaze: Copy bootfile from variables microblaze: Fix unaligned.h for endians microblaze: Initialize jumptable and console microblaze: Support flashes on lower addresses microblaze: Call common console_init_f initialization function
| * | microblaze: Copy bootfile from variablesMichal Simek2011-10-10-0/+4
| | | | | | | | | | | | | | | | | | Setup bootfile. Signed-off-by: Michal Simek <monstr@monstr.eu>
| * | microblaze: Fix unaligned.h for endiansMichal Simek2011-10-10-16/+1
| | | | | | | | | | | | | | | | | | | | | Also support little endian MB. Signed-off-by: Michal Simek <monstr@monstr.eu> Acked-by: Mike Frysinger <vapier@gentoo.org>
| * | microblaze: Initialize jumptable and consoleMichal Simek2011-10-10-0/+6
| | | | | | | | | | | | | | | | | | This changes were done to get support for netconsole. Signed-off-by: Michal Simek <monstr@monstr.eu>
| * | microblaze: Support flashes on lower addressesMichal Simek2011-10-10-1/+36
| | | | | | | | | | | | Signed-off-by: Michal Simek <monstr@monstr.eu>
| * | microblaze: Call common console_init_f initialization functionMichal Simek2011-10-10-0/+1
| |/ | | | | | | | | | | Calling console_init_f enables CTRL+C usage. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | powerpc/mpc8536ds: Add eSPI support for MPC8536DSXie Xiaobo2011-10-09-0/+5
| | | | | | | | | | | | | | | | | | | | 1. The SD_DATA[4:7] signals are shared with the SPI chip selects on 8536DS, so don't set MPC85xx_PMUXCR_SD_DATA that config eSDHC data bus-width to 4-bit and enable SPI signals. 2. Add eSPI controller and SPI-FLASH definition. Signed-off-by: Xie Xiaobo <r63061@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/mpc86xx: Disable translation for BAT setupBecky Bruce2011-10-09-29/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We really shouldn't be overwriting bat registers with translation enabled, especially when we're executing code using one of them for translating the current instruction stream. Instead, disable address translation while doing the final BAT setup. In order to do this, setup_bats has to move back to asm code, because we require translation to be enabled to have a stack for C code. The yucky thing about that is that the assembler doesn't like ULL so we have to switch to using HIGH/LOW pairs for physical addresses that are > 32 bits in length. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
generated by cgit v1.1 at 2024-08-20 08:23:12 +0000