| Commit message (Collapse) | Author | Age | Lines |
|
|
|
|
|
|
| |
Removed unused declare serdes_get_prtcl() which was no longer needed.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
| |
1, Implemented board_ft_fman_fixup_port() to fix port for kernel.
2, Implemented fdt_fixup_board_enet() to fix node status of different
slots and interfaces.
3, Adding detection of slot present for XGMII interface.
4, There is no PHY for XFI, so removed related phy address settings.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
|
|
|
|
|
|
|
| |
When CONFIG_SYS_FSL_QORIQ_CHASSIS2 is not defined, QMAN frequency will not
be initialized, and QMAN will have a wrong frequency display.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
|
|
|
|
|
|
|
|
|
| |
T4160 SoC is low power version of T4240. The T4160 combines eight dual
threaded Power Architecture e6500 cores and two memory complexes (CoreNet
platform cache and DDR3 memory controller) with the same high-performance
datapath acceleration, networking, and peripheral bus interfaces.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
|
|
|
|
|
|
| |
Protocols are constants. Fix arrays with const prefix.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
|
|
|
|
|
|
|
| |
The PIR parsing algorithm we used is not only for E6500. It applies to all
SoCs with chassis 2.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
|
|
|
|
|
|
|
| |
Use decimal and hexadecimal for protocol numbers. It helps to match with
SoC user manual.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
|
| |
T4240 internal UTMI phy is different comparing to previous UTMI PHY
in P3041.
This patch adds USB 2.0 UTMI Dual PHY new memory map and enable it for
T4240.
The phy timing is very sensitive and moving the phy enable code to
cpu_init.c will not work.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
|
|
|
|
|
|
|
|
| |
Missing nodes of crypto, pme, etc in device tree is not a fatal error.
Setting up the qman portal should skip the missing node and continue
to finish the rest.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
|
|
|
|
|
|
| |
Should check if interleaving is enabled before using interleaving mode.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
|
|
|
|
|
|
|
| |
Lane H on SerDes4 should be SATA2 instead of SATA1
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
|
|
|
|
|
|
|
|
|
| |
The L1 D-cache on e6500 is write-through. This means that it's not
considered a good idea to have the L1 up and running if the L2 is
disabled. We don't actually *use* the L1 until after the L2 is
brought up on e6500, so go ahead and move the L1 enablement after
that code is done.
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
|
|
|
|
|
|
|
| |
Fix ccsr_gur for corenet platform. Remove non-exist registers. Add fuse
status register.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
|
|
|
|
|
|
|
| |
Makes it a bit easier to see if we've properly set them. While
we're in there, modify the accesses to HDBCR0 and HDBCR1 to actually
use those definitions.
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
|
|
|
|
|
|
|
|
| |
The bit positions for FMAN1 freq in RCW is different for B4860.
Also addded a case when FMAN1 frewuency is equal to systembus.
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
|\ |
|
| |
| |
| |
| |
| |
| |
| | |
Add selected coreboot timestamps into bootstage to get a unified view of
the boot timings.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| |
| |
| |
| |
| |
| |
| | |
Coreboot provides a lot of useful timing information. Provide a facility
to add this to bootstage on start-up.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| |
| |
| |
| |
| |
| |
| |
| | |
While we don't want PCAT timers for timing, we want timer 2 so that we can
still make a beep. Re-purpose the PCAT driver for this, and enable it in
coreboot.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| |
| |
| |
| |
| |
| |
| |
| | |
This is no longer used since we prefer the more accurate TSC timer, so
remove the dead code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Tidy up some old broken and unneeded implementations. These are not used
by coreboot or anything else now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Michael Spang <spang@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
This timer runs at a rate that can be calculated, well over 100MHz. It is
ideal for accurate timing and does not need interrupt servicing.
Tidy up some old broken and unneeded implementations at the same time.
To provide a consistent view of boot time, we use the same time
base as coreboot. Use the base timestamp supplied by coreboot
as U-Boot's base time.
Signed-off-by: Simon Glass <sjg@chromium.org>base
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
The 'Starting linux' message appears twice in the code, but both call
through the same place. Unify these and add calls to bootstage to
mark the occasion.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Michael Spang <spang@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
|
| |
| |
| |
| |
| |
| |
| |
| | |
panic_puts() can be called in early boot to display a message. It might
help with early debugging.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Wai-Hong Tam <waihong@chromium.org>
|
| |
| |
| |
| |
| |
| |
| |
| | |
Several files use the global_data pointer without declaring it. This works
because the declaration is currently a NOP. But still it is better to
fix this so that x86 lines up with other archs.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| |
| |
| |
| |
| |
| |
| | |
Since we use CONFIG_SYS_GENERIC_BOARD on x86, we don't need this anymore.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
|
| |
| |
| |
| |
| |
| |
| |
| | |
Since we don't have real-mode code now, we can remove this chunk of the link
script.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
|
| |
| |
| |
| |
| |
| |
| | |
Graeme Russ pointed out that this code is no longer used. Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
|
|/
|
|
|
|
|
|
|
|
|
|
| |
Commit 1865286466a5d0c7f2e3c37632da56556c838e9e (Introduce generic link
section.h symbol files) changed the __bss_end symbol type from char[] to
ulong. This led to wrong relocation parameters which ended up in a not working
u-boot. Unfortunately this is not clear to see cause due to RAM aliasing we
may get a 'half-working' u-boot then.
Fix this by dereferencing the __bss_end symbol where needed.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
|
|
|
|
|
|
| |
Unifies the openrisc boards linker scripts into a common one.
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Microblaze uses gpio which is connected to the system reset.
Currently gpio subsystem wasn't used for it.
Add gpio driver and change Microblaze reset logic to be done
via gpio subsystem.
There are various configurations which Microblaze can have
that's why gpio_alloc/gpio_alloc_dual(for dual channel)
function has been introduced and gpio can be allocated
dynamically.
Adding several gpios IP is also possible and supported.
For listing gpio configuration please use "gpio status" command
This patch also remove one compilation warning:
microblaze-generic.c: In function 'do_reset':
microblaze-generic.c:38:47: warning: operation on '*1073741824u'
may be undefined [-Wsequence-point]
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
|
|
|
|
|
|
| |
fdt_initrd add additional information to DTB about initrd
addresses which are later used by kernel.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
|
|
|
|
|
| |
Prepare place for new patch.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
|
|
|
|
|
|
|
| |
Include this header to get access to link symbols, which are otherwise
removed.
Signed-off-by: Kuan-Yu Kuo <ken.kuoky@gmail.com>
Cc: Macpaul Lin <macpaul@gmail.com>
|
|\ |
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Extending LIODN offset range from 1-5 to 1-10
While using a qman portal with a higher index the LIODN offset
is incorrectly set, thus extending the range of offsets covers
all 10 qman portals
Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com>
Acked-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
| |
| |
| |
| |
| |
| |
| | |
Erratum DDR_A003 applies to P5020, P3041, P4080, P3060, P2041, P5040.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
| |
| |
| |
| |
| |
| |
| |
| | |
Only some chips have four SerDes banks, so don't define lanes for a bank
that doesn't exist.
Signed-off-by: Timur Tabi <timur@tabi.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
| |
| |
| |
| |
| |
| |
| |
| | |
As per Errata list of BSC9131 and BSC9132, IFC Errata A003399 is no more
valid. So donot compile its workaround.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| | |
cpu.c:288:2:
warning: implicit declaration of function 'reset_85xx_watchdog'
[-Wimplicit-function-declaration]
Signed-off-by: Horst Kronstorfer <hkronsto@frequentis.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
On P204x/P304x/P50x0 Rev1.0, USB transmit will result in false internal
multi-bit ECC errors, which has impact on performance, so software should
disable all ECC reporting from USB1 and USB2.
In formal release document, the errata number should be USB14 instead of USB138.
Signed-off-by: xulei <Lei.Xu@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: xulei <B33228@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Some legacy RGMII phys don't have in band signaling for the
speed information. so set the RGMII MAC mode according to
the speed got from PHY.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Reported-by: John Traill <john.traill@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
| |
| |
| |
| |
| |
| |
| |
| | |
For T4/B4, the clockgen node compatible string is updated to version 2.
Add clock-frequency setting for this new version.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
| |
| |
| |
| |
| |
| |
| |
| | |
Per the latest errata updated, B4860/B4420 Rev 1.0 has also
errata A-005871, so adding define A-005871 for B4 SoCs.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
B4420/B4860 PCIE can not work because of the wrong definition of
the PCIE register offset in the file:
arch/powerpc/include/asm/immap_85xx.h
Add the judgement of B4420/B4860 to make the register offset to:
#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
| |
| |
| |
| |
| |
| |
| |
| | |
Set the device tree property associated with the mpic source
frequency. The frequency is used for mpic timer.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
The 'fsl,pme-rev1' and 'fsl-pme-rev2' properties have been added to the
pme portal node. This is required for software to determine which version
of PME hardware is present and take appropriate actions.
These properties are a direct reflection of the corresponding ccsr pme
register value.
Also removed unnecessary static global variables.
Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
|\ \
| |/
|/| |
|
| |
| |
| |
| |
| |
| |
| | |
The prt_mpc512x_clks() function isn't referenced
anywhere and its prototype is wrong. Remove it.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
|
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Delete all occurrences of hang() and provide a generic function.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
[trini: Modify check around puts() in hang.c slightly]
Signed-off-by: Tom Rini <trini@ti.com>
|