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* Remove linker lists (LGAs) from SPL linker scriptsAlbert ARIBAUD2013-03-12-16/+160
| | | | | | | | | | | | Many SPL linker scripts needlessly include linker lists (aka LGAs). Remove them whenever possible; keep it only in the seven am335x_evm variants (am335x_evm, am335x_evm_uart[1-5], am335x_evm_spiboot), where there is actual content in output section .u_boot_list. This commit keeps all u-boot.bin and u-boot-spl.bin in ARM targets byte-identical. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* arm: omap: map u_boot_lists section to .sramAlbert ARIBAUD2013-03-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Output section .u_boot_list was left unmapped in u-boot-spl.lds for omap-common, causing the location counter to roll back to bteween .rodata and .data, making __image_copy_end and _end symbols wrong. Mapping output section .u_boot_list to memory .sram fixes these symbols' mapping. This modifies the SPL binary but has no functional impact, as __image_copy_end and _end are never used in SPLs and u_boot_list is empty for all 29 boards affected (omap4_sdp4430 eco5pk igep0030 am335x_evm_uart3 omap3_beagle am3517_crane igep0032 mt_ventoux pcm051 am3517_evm omap3_evm_quick_mmc am335x_evm_uart2 am335x_evm_spiboot am335x_evm_uart1 omap3_evm igep0030_nand omap3_overo igep0020 am335x_evm omap4_panda omap5_evm am335x_evm_uart4 devkit8000 tricorder mcx twister omap3_evm_quick_nand am335x_evm_uart5 igep0020_nand). Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* Merge branch 'u-boot-atmel/master' into 'u-boot-arm/master'Albert ARIBAUD2013-03-12-21/+15
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| * ARM: sam9x5: fix ethernet pins in MII modeJesse Gilles2013-03-12-8/+8
| | | | | | | | | | | | | | Fix pin setting in MII mode Signed-off-by: Jesse Gilles <jgilles@multitech.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * ARM: at91sam9x5: Using CPU string directlyBo Shen2013-03-12-13/+7
| | | | | | | | | | | | | | As the CPU name is not configurable, using CPU string directly Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | Merge u-boot/master into u-boot-ti/masterTom Rini2013-03-11-431/+3187
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In master we had already taken a patch to fix the davinci GPIO code for CONFIG_SOC_DM646X and in u-boot-ti we have additional patches to support DA830 (which is CONFIG_SOC_DA8XX && !CONFIG_SOC_DA850). Resolve these conflicts manually and comment the #else/#endif lines for clarity. Conflicts: arch/arm/include/asm/arch-davinci/gpio.h drivers/gpio/da8xx_gpio.c Signed-off-by: Tom Rini <trini@ti.com>
| * | x86: Add error checking to x86 relocation codeSimon Glass2013-03-04-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This does not actually change normal behaviour, but adds a check that should detect corruption of relocation data (e.g. by using BSS data prior to relocation). Also add additional debugging output when enabled. During this investigation, two situations have been seen: 1. calculate_relocation_address(): uintptr_t size = (uintptr_t)&__bss_end - (uintptr_t)&__text_start; turns into 111166f: b8 83 c4 17 01 mov $0x117c483,%eax whih is beyond the end of bss: 0117b484 g .bss 00000000 __bss_end Somehow the __bss_end here is 255 bytes ahead. 2. do_elf_reloc_fixups(): uintptr_t size = (uintptr_t)&__bss_end - (uintptr_t)&__text_start; Here the __text_start is 0 in the file: 1111d9f: bb a0 e0 13 01 mov $0x113e0a0,%ebx 1111da4: 81 ef 00 00 00 00 sub $0x0,%edi As it happens, both of these are in pre-relocation code. For these reasons we silent check and ignore bad relocations. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Support relocation of FDT on start-upSimon Glass2013-03-04-2/+46
| | | | | | | | | | | | | | | | | | | | | With CONFIG_OF_CONTROL we may have an FDT in the BSS region. Relocate it up with the rest of U-Boot to keep the rest of memory free. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Rearrange the output input to remove BSSSimon Glass2013-03-04-7/+12
| | | | | | | | | | | | | | | | | | | | | At present BSS data is including in the image, which wastes binary space. Remove it by rearranging the sections so that BSS is last. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Add an __end symbol to signal the end of the U-Boot binarySimon Glass2013-03-04-1/+4
| | | | | | | | | | | | | | | | | | | | | With this symbol we can easy append something (e.g. an FDT) to the U-Boot binary and access it from within U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Permit bootstage and timer data to be used prior to relocationSimon Glass2013-03-04-18/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | It is useful to be able to access the timer before U-Boot has relocated so that we can fully support bootstage. Add new global_data members to support this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Add basic cache operationsSimon Glass2013-03-04-0/+23
| | | | | | | | | | | | | | | | | | | | | At present most x86 cache operations are undefined. Add a basic implementation for these. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Add function to get top of usable ramSimon Glass2013-03-04-24/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The memory layout calculations are done in calculate_relocation_address(), and coreboot has its own version of this function. But in fact all we really need is to set the top of usable RAM, and then the base version will work as is. So instead of allowing the whole calculate_relocation_address() function to be replaced, create board_get_usable_ram_top() which can be used by a board to specify the top of the area where U-Boot relocations to. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | sandbox: Add a way of obtaining directory listingsSimon Glass2013-03-04-0/+101
| | | | | | | | | | | | | | | | | | | | | | | | This implementation uses opendir()/readdir() to access the directory information and then puts it in a linked list for the caller's use. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com>
| * | Merge branch 'mem' of git://git.denx.de/u-boot-x86Tom Rini2013-03-04-0/+22
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| | * | sandbox: Add un/map_sysmen() to deal with sandbox's ram_bufSimon Glass2013-02-28-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sandbox doesn't actually provide U-Boot access to the machine's physical memory. Instead it provides a RAM buffer of configurable size, and all memory accesses are within that buffer. Sandbox memory starts at 0 and is CONFIG_DRAM_SIZE bytes in size. Allowing access outside this buffer might produce unpredictable results in the event of an error, and would expose the host machine's memory architecture to the sandbox U-Boot. Most U-Boot functions assume that they can just access memory at given address. For sandbox this is not true. Add a map_sysmem() call which converts a U-Boot address to a system address. In most cases this is a NOP, but for sandbox it returns a pointer to that memory inside the RAM buffer. To get a U-Boot feature to work correctly within sandbox, you should call map_sysmem() to get a pointer to the address, and then use that address for any U-Boot memory accesses. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | sandbox: Improve sandbox serial port keyboard interfaceTaylor Hutt2013-02-28-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implements the tstc() interface for the serial driver. Multiplexing the console between the serial port and a keyboard uses a polling method of checking if characters are available; this means that the serial console must be non-blocking when attempting to read characters. Signed-off-by: Taylor Hutt <thutt@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | sandbox: fix compiler warningAllen Martin2013-02-28-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add back return statement to fix compiler warning about control flow reaching end of non void function that was introduced with: e05e5de arm: move C runtime setup code in crt0.S Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | blackfin: bf60x: add resume from hibernateSteven Miao2013-03-04-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Bf60x resume from hibernate support Signed-off-by: Steven Miao <realmz6@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bob Liu <lliubbo@gmail.com> Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
| * | | blackfin: bf60x: add hw watchdog supportBob Liu2013-03-04-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Bob Liu <lliubbo@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
| * | | blackfin: add bf6xx spi driverScott Jiang2013-03-04-0/+240
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Spi driver for bf60x is different from old one, so implement a new driver for it. Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bob Liu <lliubbo@gmail.com> Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
| * | | blackfin: bf60x: add rsi/sdh supportSonic Zhang2013-03-04-2/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add rsi/sdh support for bf60x. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bob Liu <lliubbo@gmail.com> Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
| * | | blackfin: bf60x: add gpio supportBob Liu2013-03-04-8/+181
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Bob Liu <lliubbo@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
| * | | blackfin: bf60x: support big cplb pageBob Liu2013-03-04-6/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BF60x support 16K, 64K, 16M and 64M cplb pages, this patch add support for them. So that bf609-ezkit can use it's 128M memory. Signed-off-by: Bob Liu <lliubbo@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
| * | | blackfin: bf60x: add dma supportBob Liu2013-03-04-76/+156
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add dma support for bf60x. Signed-off-by: Bob Liu <lliubbo@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
| * | | blackfin: bf60x: add serial supportSonic Zhang2013-03-04-238/+642
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add serial for bf60x. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bob Liu <lliubbo@gmail.com> Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
| * | | blackfin: bf60x: Port blackfin core architecture code to boot on bf60x.Sonic Zhang2013-03-04-41/+468
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set up clocks, DDR controller, Nor flash controller, reboot, serial port. Add new SPI boot modes. Signed-off-by: Bob Liu <lliubbo@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
| * | | blackfin: bf60x: new processor header filesBob Liu2013-03-04-1/+1090
| |/ / | | | | | | | | | | | | | | | | | | | | | Add header files for blackfin new processor bf60x. Signed-off-by: Bob Liu <lliubbo@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
| * | mac: Fix the condition check for setting the MAC from the EEPROMHolger Hans Peter Freyther2013-02-20-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The issue got introduced in a cleanup by Manjunath Hadli in commit 826e99136e2bce61f3f6572e32d7aa724c116e6d. The eth_getenv_enetaddr_by_index method will validate the MAC addr and if none is set in the environment 0 will be returned. Set the MAC from the eeprom if no valid address is found in environment. Signed-off-by: Holger Hans Peter Freyther <holger@freyther.de>
| * | gpio: Build the da8xx_gpio code for the davinci644x deviceHolger Hans Peter Freyther2013-02-20-1/+7
| | | | | | | | | | | | | | | | | | | | | The differences include the number of GPIOs and that one is not required to set the pinmux on request. Signed-off-by: Holger Hans Peter Freyther <holger@freyther.de>
| * | malloc: make malloc_bin_reloc staticGabor Juhos2013-02-19-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On architectures where manual relocation is needed, the 'malloc_bin_reloc' function must be called after 'mem_malloc_init'. Make the 'malloc_bin_reloc' function static and call it directly from 'mem_malloc_init' instead of calling that from board_init_{r,f} functions of the affected architectures. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Wolfgang Denk <wd@denx.de> Cc: Andreas Bießmann <andreas.devel@gmail.com> Cc: Jason Jin <Jason.jin@freescale.com> Cc: Macpaul Lin <macpaul@andestech.com> Cc: Daniel Hellstrom <daniel@gaisler.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * | nds32: Add a basic errno.hSimon Glass2013-02-18-0/+1
| |/ | | | | | | | | | | | | This is available on other architectures, and nds32 will start to break without it as code starts to use error numbers more. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: dra7xx: Add silicon id support for DRA752 socLokesh Vutla2013-03-11-2/+14
| | | | | | | | | | | | | | | | Adding CPU detection support for the DRA752 ES1.0 soc. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* | arm: dra7xx: Add board files for DRA7XX socsLokesh Vutla2013-03-11-9/+349
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding new board files for DRA7XX socs. The pad registers layout is changed completely from OMAP5 So introducing the new structure here and also adding the minimal data. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishant Kamat <nskamat@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com> [trini: Adapt omap_mmc_init call for last 2 params] Signed-off-by: Tom Rini <trini@ti.com>
* | arm: dra7xx: Add DDR related data for DRA752 ES1.0Lokesh Vutla2013-03-11-6/+42
| | | | | | | | | | | | | | | | | | | | DRA752 uses DDR3. Populating the corresponding structures with DDR3 data. Writing into MA registers if only MA is present in that soc. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* | arm: dra7xx: Add control module changesLokesh Vutla2013-03-11-2/+85
| | | | | | | | | | | | | | | | | | | | Control module register addresses are changed from OMAP5 to DRA7XX socs. So adding the necessary changes for the same. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* | arm: dra7xx: clock: Add the dplls dataLokesh Vutla2013-03-11-8/+94
| | | | | | | | | | | | | | | | | | | | | | | | A new DPLL DDR is added in DRA7XX socs. Now clocks to EMIF CD is from DPLL DDR. So DPLL DDR should be locked before initializing RAM. Also adding other dpll data which are different from OMAP5 ES2.0. SYS_CLK running at 20MHz is introduced in DRA7xx socs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* | arm: dra7xx: clock: Add the prcm changesLokesh Vutla2013-03-11-8/+252
| | | | | | | | | | | | | | | | PRCM register addresses are changed from OMAP5 ES2.0 to DRA7XX. So adding the necessary register changes for DRA7XX socs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com>
* | ARM: OMAP5: srcomp: enable slew rate compensation cells after powerupLokesh Vutla2013-03-11-1/+152
| | | | | | | | | | | | | | | | | | | | | | | | | | | | After power-up SRCOMP cells are by-passed by default in OMAP5. Software has to enable these SRCOMP sells. For ES2: All 5 SRCOMP cells needs to be enabled. For ES1: Only 4 SRCOMP cells in core power domain are enabled. The 1 in wkup domain is not enabled because smart i/os of wkup domain work with default compensation code. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com> Cc: Tom Rini <trini@ti.com>
* | ARM: OMAP5: Add DDR changes required for OMAP543X ES2.0 SOCsLokesh Vutla2013-03-11-2/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | Add pre calculated timing settings of LPDDR2 and DDR3 memories present in OMAP5430 and OMAP5432 ES2.0 versions. Also adding the DDR pad io settings required for OMAP543X SOCs here. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com> Cc: Tom Rini <trini@ti.com>
* | ARM: OMAP4/5: clocks: Add the required OPP settings as per the latest addendumSRICHARAN R2013-03-11-189/+254
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change OPP settings as per the latest 0.5 version of addendum for OMAP5430 ES2.0. omap4/hw_data.c is touched here to add dummy dividers. While here correcting OPP_NOM mpu, core frequency for OMAP4430 ES2.x Note that OMAP5430 ES1.0 support is still kept alive and would be removed in a cleanup later. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Nishanth Menon <nm@ti.com>
* | ARM: OMAP5: clock: Add the prcm register changes required for ES2.0SRICHARAN R2013-03-11-0/+292
| | | | | | | | | | | | | | | | | | | | | | PRCM register addresses are changed from ES1.0 to ES2.0 due to PER power domain getting moved to CORE power domain. So adding the nessecary register changes for the same. Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com> Cc: Tom Rini <trini@ti.com>
* | ARM: OMAP5: Add silicon id support for ES2.0 revision.SRICHARAN R2013-03-11-11/+21
| | | | | | | | | | | | | | | | | | Adding the CPU detection suport for OMAP5430 and OMAP5432 ES2.0 SOCs. Signed-off-by: R Sricharan <r.sricharan@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Nishanth Menon <nm@ti.com>
* | ARM: OMAP5: Clean up iosettings codeLokesh Vutla2013-03-11-44/+78
| | | | | | | | | | | | | | | | | | | | | | There is some code duplication in the ddr io settings code. This is avoided by moving the data to a Soc specific place and letting the code generic. This avoids unnessecary code addition for future socs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* | ARM: OMAP4+: Make control module register structure genericLokesh Vutla2013-03-11-191/+259
| | | | | | | | | | | | | | | | | | | | | | | | A seperate omap_sys_ctrl_regs structure is defined for omap4 & 5. If there is any change in control module for any of the ES versions, a new structure needs to be created. In order to remove this dependency, making the register structure generic for all the omap4+ boards. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* | ARM: OMAP4+: Cleanup emif specific filesLokesh Vutla2013-03-11-85/+108
| | | | | | | | | | | | | | | | | | | | | | | | Removing the duplicated code in ddr3 initialization. Also creating structure for lpddr2 mode registers to avoid unnessecary revision checks. These change reduces code addition for future Socs. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* | ARM: OMAP4+: Clean up the pmic codeSRICHARAN R2013-03-11-260/+198
| | | | | | | | | | | | | | | | | | | | The pmic code is duplicated for OMAP 4 and 5. Instead move the data to Soc specific place and share the code. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* | ARM: OMAP4+: Cleanup the clocks layerSRICHARAN R2013-03-11-895/+869
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently there is quite a lot of code which is duplicated in the clocks code for OMAP 4 and 5 Socs. Avoiding this here by moving the clocks data to a SOC specific place and the sharing the common code. This helps in addition of a new Soc with minimal changes. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* | ARM: OMAP4+: Change the PRCM structure prototype common for all SocsSRICHARAN R2013-03-11-1205/+1312
| | | | | | | | | | | | | | | | | | | | | | | | The current PRCM structure prototype directly matches the hardware register layout. So there is a need to change this for every new silicon revision which has register space changes. Avoiding this by making the prototye generic and populating the register addresses seperately for all Socs. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: OMAP4+: emif: Detect SDRAM from SDRAM config registerLokesh Vutla2013-03-11-7/+28
| | | | | | | | | | | | | | | | | | | | | | Now SDRAM initialization is done on the basis of omap revision. Instead this should be done on basis of SDRAM type read from EMIF_SDRAM_CONFIG register. This will be helpful to avoid unnessecary cpu checks for new boards Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
generated by cgit v1.1 at 2024-09-12 08:53:25 +0000