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| * ARM: uniphier: do not compile v7_outer_cache_disable if L2 is disabledMasahiro Yamada2016-08-11-1/+1
| | | | | | | | | | | | | | | | If CONFIG_UNIPHIER_L2CACHE_ON is undefined, the L2 cache is never enabled, so there is no need for v7_outer_cache_disable(). The weak stub avoids the compile error anyway. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: support prefetch and touch operations for outer cacheMasahiro Yamada2016-08-11-10/+57
| | | | | | | | | | | | | | | | | | | | The UniPhier outer cache (L2 cache on ARMv7 SoCs) can be used as SRAM by locking ways. These functions will be used to transfer the trampoline code for SMP into the locked SRAM. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: refactor outer cache codeMasahiro Yamada2016-08-11-47/+52
| | | | | | | | | | | | | | | | | | Unify the range/all operation routines into the common function, uniphier_cache_maint_common(), and sync code with Linux a bit more. This reduces the code duplication. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-08-11-1/+1
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| * dm: ls1021a: dts: Update USB 3.0 node to support DM USBRajesh Bhagat2016-08-07-1/+1
| | | | | | | | | | | | Update USB 3.0 controller dts node in ls1021a.dtsi. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
* | Merge git://www.denx.de/git/u-boot-ppc4xxTom Rini2016-08-09-21/+45
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| * | ppc4xx: Fix platform supportDirk Eibach2016-08-09-21/+45
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit "ecc3066 Fix board init code to respect the C runtime environment" broke platform support for ppc4xx. start.S prepares a stackframe that is later rendered unusable by appending the reserved space for global data. Instead the reserved space has to be put first. Then the stackframe can be pushed. I can only test the 405EP OCM case. At least all other ppc4xx boards still build. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Stefan Roese <sr@denx.de>
* | ARM: dts: dra72-evm: Add mode-gpios entry for mac nodeVignesh R2016-08-08-1/+1
| | | | | | | | | | | | | | | | | | | | | | On DRA72 EVM, cpsw slave1 is muxed with VIN2A, hence switch to cpsw slave0 for ethernet. This is controlled by pcf gpio line. Add appropriate mode-gpios DT entry so that driver can select the required slave. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* | ARM: dts: dra7xx: Add u-boot specific property for PCF8575 nodesVignesh R2016-08-08-0/+3
|/ | | | | | | | | | PCF8575 does not have any registers hence, offset field needs to be ignored for i2c read/write. Therefore populate u-boot,i2c-offset-len with 0 in PCF8575 DT nodes. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-rockchipTom Rini2016-08-06-8/+775
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| * dts: rk3399: enable dwmmc for sdcardKever Yang2016-08-05-2/+6
| | | | | | | | | | | | | | | | | | rk3399 sdcard is using dwmmc controller, enable it for sdcard. SCLK_SDMMC is the clock for controller operation clock, move it to the first place. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: add support for rk3288 miniarm boardXu Ziyuan2016-08-05-2/+607
| | | | | | | | | | | | | | | | Miniarm is a rockchip rk3288 based development board, which has lots of interface such as HDMI, USB, micro-SD card, Audio etc. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rk3399: add basic soc driverKever Yang2016-08-05-0/+160
| | | | | | | | | | | | | | | | | | | | This patch add driver for: - clock driver including set_rate for cpu, mmc, vop, I2C. - sysreset driver - grf syscon driver Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: rockchip, sdram-channel 0xff fix remaining dtsSandy Patterson2016-08-05-2/+2
| | | | | | | | | | | | | | Add an extra byte so that this data is not byteswapped. Signed-off-by: Sandy Patterson <apatterson@sightlogix.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: add fastboot support for rk3036 boardXu Ziyuan2016-08-05-2/+0
| | | | | | | | | | | | | | | | Enable fastboot feature on rk3036, please refer to doc/README.rockchip for more detailed usage. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2016-08-05-10/+267
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| * | ARM: tegra: call tegra_board_init on Tegra186Stephen Warren2016-08-04-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce tegra_board_init() and call it from board_init(). Tegra wil use tegra_board_init() for board-specific initialization, and board_init() for SoC-specific initialization. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: add I2C controllers to Tegra186 DTBryan Wu2016-08-04-0/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra186 has 8 I2C controllers including BPMP I2C. This patch adds the other 7 generic controllers to Tegra186's DT. Signed-off-by: Bryan Wu <pengw@nvidia.com> (swarren, fixed DT node sort order, tweak patch description) Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: add PCIe controller to Tegra186 SoC DTStephen Warren2016-08-04-0/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Tegra186 PCIe DT content is almost identical to previous chips, except that the: - There are 3 ports instead of 2. - Some physical addresses have moved. - PHY programming is handled by firmware, so CCPLEX DTs don't need to reference any PHY. - The power domain is explicitly represented in DT. This change is mandatory for Tegra186 since standard power domain APIs are used, and should be made to the DT for older SoCs, although we get away without doing so since U-Boot currently uses custom APIs that hard-code power domain IDs. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: add BPMP I2C to Tegra186 device treeStephen Warren2016-08-04-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | This allows the BPMP I2C device to be instantiated, which makes it available to other drivers and the user. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: add BPMP and dependencies to Tegra186 DTStephen Warren2016-08-04-2/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the DT content that's needed to allow board DTs to enable use of BPMP, clocks, resets, GPIOs, eMMC, and SD cards. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: adapt to latest HSP DT bindingStephen Warren2016-08-04-7/+3
| |/ | | | | | | | | | | | | | | | | | | The DT binding for the Tegra186 HSP module apparently wasn't quite final when I posted initial U-Boot support for it. Add the final DT binding doc and adapt all code and DT files to match it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | armv8: mmu: Detect page table overflow in emergency pt creationAlexander Graf2016-08-05-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We create 2 sets of page tables: One for normal operation, one for emergency (used while modifying the former). Because the page tables grow dynamically, we have code that checks for overflow. Unfortunately we didn't adjust the available space variable while creating the emergency tables, so potentially someone might run into an overflow there (not seen in real world yet though!). Fix it by properly adjusting the size as well as the base offset in emergency page table creation. Reported-by: York Sun <york.sun@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com>
* | omap3: Drop omap3_evm_quick_* targetsTom Rini2016-08-05-6/+0
| | | | | | | | | | | | | | | | | | These config targets were added well before the Kconfig migration began as a way to demonstrate how to make these platforms work with cut down features. At this point in time they no longer serve a good purpose so remove them. Signed-off-by: Tom Rini <trini@konsulko.com>
* | omap3, omap4: Enable USE_TINY_PRINTF for allTom Rini2016-08-05-0/+2
| | | | | | | | | | | | | | | | | | In the case of omap3 we have a number of platforms that are close to exceeding SRAM limits, depending on compiler. Move to USE_TINY_PRINTF to give them more room. OMAP4 will soon enough be in a similar place, so enable that now. Signed-off-by: Tom Rini <trini@konsulko.com>
* | omap3: Move to select SUPPORT_SPL for allTom Rini2016-08-05-19/+1
| | | | | | | | | | | | | | In reality all omap3 platforms support SPL so move the select for this up a level. Signed-off-by: Tom Rini <trini@konsulko.com>
* | treewide: move CONFIG_PHYS_64BIT to KconfigMasahiro Yamada2016-08-05-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to ensure that CONFIG_PHYS_64BIT is configured via Kconfig so that it is always available to the build system. Otherwise we can run into cases where we have inconsistent sizes of certain attributes. Ravi Babu reported offset mismatch of struct dwc3 across files since commit 95ebc253e6d4 ("types.h: move and redefine resource_size_t"). Since the commit, resource_addr_t points to phys_addr_t, whose size is dependent on CONFIG_PHYS_64BIT for ARM architecture. I tried my best to use "select" where possible (for example, ARMv8 architecture) because I think this kind of option is generally user- unconfigurable. However, I see some of PowerPC boards have 36BIT defconfigs as well as 32BIT ones. I moved CONFIG_PHYS_64BIT to the defconfigs for such boards. CONFIG_36BIT is no longer referenced, so all of the defines were removed from CONFIG_SYS_EXTRA_OPTIONS. Fixes: 95ebc253e6d4 ("types.h: move and redefine resource_size_t") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reported-by: Ravi Babu <ravibabu@ti.com> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | ARM: Rework and correct barrier definitionsTom Rini2016-08-05-40/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As part of testing booting Linux kernels on Rockchip devices, it was discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for some cases incomplete isb definitions. This was causing a failure to boot of the Linux kernel. In order to solve this problem as well as cover any corner cases that we may also have had a number of changes are made in order to consolidate things. First, <asm/barriers.h> now becomes the source of isb/dsb/dmb definitions. This however introduces another complexity. Due to needing to build SPL for 32bit tegra with -march=armv4 we need to borrow the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete form. Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add a comment about it. Now that we can always know what the target CPU is capable off we can get always do the correct thing for the barrier. The final part of this is that need to be consistent everywhere and call isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the function names in others. Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Sandy Patterson <apatterson@sightlogix.com> Reported-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reported-by: Sandy Patterson <apatterson@sightlogix.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* | arc: Rename AXS101 board to more generic AXS10xAlexey Brodkin2016-08-05-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As of now we have 2 flavors of ARC SDP boards: 1) AXS101 - with ARC770 in ASIC 2) AXS103 - with ARC HS38 in FPGA Both options share exactly the same base-board and only differ with CPU-tiles in use. That means all peripherals are the same (they are implemented in FPGA on the base-board) and so generic board could be used for both. While at it: * Recreated defconfigs with savedefconfig * In include/configs/axs10x.h numerical sizes replaced with defines from linux/sizes.h for better readability. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arc: Rename ARCangel4 board to nSIMAlexey Brodkin2016-08-05-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARCangel was one of the main development boards back in the day but now it's gone and replaced by other boards like ARC SDP. But we also used to have simulation platform very similar to ARCangel4 in terms of CPU settings as well as basic IO like UART. Even though ARCangel4 is long gone now we have a replacement for simulation which is a plain or stand-alone nSIM and Free nSIM. Note Free nSIM is available for download here: https://www.synopsys.com/cgi-bin/dwarcnsim/req1.cgi And while at it: * Finally switch hex numerical values in nsim.h to defines from include/linux/sizes.h * Add defconfigs with ARC HS38 cores * Recreated all defconfigs with savedefconfig Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | arc: No need in sections defined in sources with newer toolsAlexey Brodkin2016-08-05-64/+18
| | | | | | | | | | | | | | | | Starting from arc-2016.03 GNU tools linker properly works with symbols defined in linker script and so external declarations are no longer required, dump them. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | arc: Update exception & interrupt handling for ARCv2Alexey Brodkin2016-08-05-13/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initially IVT for ARCv2 was simply copypasted from ARCompact with some selected fixes so basic stuff works. Now we update it with more ARCv2 specific vectors like * Software Interrupt * Division by zero * Data cache consistency error * Misaligned access Also normal interrupts are now implemented properly and extened to all possible 240 items. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | arc: Add debug messages during relocation fixupsAlexey Brodkin2016-08-05-0/+7
|/ | | | | | | | This might be useful to make sure relocation fixups really happen. And since this info gets printed only in DEBUG build it doesn't really hurt normal execution. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-08-02-45/+42
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| * ARMv8/fsl-ppa: Consolidate PPA image stored-media flag for XIPHou Zhiqiang2016-08-02-1/+1
| | | | | | | | | | | | | | | | | | | | | | The PPA binary may be stored on QSPI flash instead of NOR. So, deprecated CONFIG_SYS_LS_PPA_FW_IN_NOR in favour of CONFIG_SYS_LS_PPA_FW_IN_XIP to prevent fragmentation of code by addition of a new QSPI specific flag. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arm/PSCI: Add support for creating ARMv7 PSCI version 1.0 DT nodeHou Zhiqiang2016-08-02-0/+2
| | | | | | | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arm/PSCI: Fixed the backward compatiblity issueHou Zhiqiang2016-08-02-26/+38
| | | | | | | | | | | | | | | | | | | | | | | | Appended the compatible strings of old version PSCI to the latest version supported. And there are some psci functions' property must be added to DT only for psci version 0.1, including cpu_on, cpu_off, cpu_suspend, migrate. Note, ARMv8 Secure Firmware Framework doesn't support PSCI ver 0.1. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arm/PSCI: Removed unused codeHou Zhiqiang2016-08-02-17/+0
| | | | | | | | | | | | | | | | Identify the PSCI node only by its name, so removed the code finding it by compatible string. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * powerpc/mpc85xx: Update erratum workaround for A006379York Sun2016-08-02-1/+1
| | | | | | | | | | | | | | | | Update erratum workaround for A006379 to set register CPCHDBCR0 with value 0x001e0000, replacing the old value 0x003c0000. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Dave Liu <dave.liu@nxp.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2016-08-02-3/+2
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| * | ARM64: zynqmp: Do not enable DM_MMC by defaultMichal Simek2016-08-02-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch: "dm: mmc: zynq: Convert zynq to use driver model for MMC" (sha1: 329a449f2c289b4de8f892fca1d9379ce5fd81b8) added dependency on enabling some MMC options by default. There are minimal ZynqMP configurations which require only minimal configurations to be enabled to keep u-boot size as lower as possible. Move options to defconfig instead. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM64: zynqmp: Add u-boot,dm-pre-reloc to clk nodesMichal Simek2016-08-01-0/+2
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Serial driver is getting clk information via DT that's why also clk node needs to have this flag. Different behavior was introduced by: "dm: Use dm_scan_fdt_dev() directly where possible" (sha1: 911954859d6dece49c3e4835faea004cfe392506) where simple-bus driver starts to call dm_scan_fdt_dev() which has additional logic around pre_reloc_only parameter which exclude clk nodes. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | libfdt: Introduce new ARCH_FIXUP_FDT optionMichal Simek2016-07-31-0/+6
|/ | | | | | | | | | Add new Kconfig option to disable arch_fixup_fdt() calls for cases where U-Boot shouldn't update memory setup in DTB file. One example of usage of this option is to boot OS with different memory setup than U-Boot use. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-rockchipTom Rini2016-07-31-19/+1101
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| * rockchip: add support for rk3288 PopMetal boardjk.kernel@gmail.com2016-07-31-0/+593
| | | | | | | | | | | | | | | | | | PopMetal is a rockchip rk3288 based board made by ChipSpark, which has many interface such as HDMI, VGA, USB, micro-SD card, WiFi, Audio and Gigabit Ethernet. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: add basic support for fennec-rk3288 boardjk.kernel@gmail.com2016-07-31-2/+493
| | | | | | | | | | | | | | | | | | | | Fennec is a RK3288-based development board with 2 USB ports, HDMI, micro-SD card, audio and WiFi and Gigabit Ethernet. It also includes on-board 8GB eMMC and 2GB of SDRAM. Expansion connectors provides access to display pins, I2C, SPI, UART and GPIOs. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: rk3288: move evb board to rockchip folderjk.kernel@gmail.com2016-07-31-1/+1
| | | | | | | | | | | | | | | | The 'evb-rk3288' is not a vendor name, change it to 'rockchip' which is the real vendor name. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * Revert "rockchip: Move the MMC setup check earlier"jk.kernel@gmail.com2016-07-31-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boot Rom wouldn't initialize sdmmc while booting from eMMC. We need to setup sdmmc gpio, otherwise we will hit an error below: =>mmc info blk_get_device: if_type=6, devnum=0: dwmmc@ff0c0000.blk, 6, 0 uclass_find_device_by_seq: 0 -1 uclass_find_device_by_seq: 0 0 - -1 -1 - -1 0 - found uclass_find_device_by_seq: 0 1 - -1 -1 - -1 0 - not found fdtdec_get_int_array: interrupts get_prop_check_min_len: interrupts Buswidth = 1, clock: 0 Buswidth = 1, clock: 400000 Sending CMD0 dwmci_send_cmd: Timeout on data busy dwmci_send_cmd: Timeout on data busy dwmci_send_cmd: Timeout on data busy dwmci_send_cmd: Timeout on data busy This reverts commit 6efeeea79c880d3dd262e0dca9da2687f0ab68c9. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * rockchip: add a dummy byte for the sdram-channel propertyjk.kernel@gmail.com2016-07-31-1/+2
| | | | | | | | | | | | | | | | Add an extra byte so that this data is not byteswapped. Signed-off-by: Ziyuan Xu <jk.kernel@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
| * configs: rockchip: remove no use MACROKever Yang2016-07-31-3/+0
| | | | | | | | | | | | | | | | The CONFIG_ROCKCHIP_COMMON and CONFIG_SPL_ROCKCHIP_COMMON are no use now, remove them. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-08-21 05:59:26 +0000