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* imx: mx6ull: update clock settings and CCM register mapPeng Fan2016-10-04-29/+89
| | | | | | | | Update Clock settings and CCM register map for i.MX6ULL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6ull: adjust POR_B setting for i.MX6ULLPeng Fan2016-10-04-0/+14
| | | | | | | | | | | | | | Adjust POR_B settings on i.MX6ULL according to IC design team's suggestion: 2'b00 : always PUP100K 2'b01 : PUP100K when PMIC_ON_REQ || SOC_NOT_FAIL 2'b10 : always disable PUP100K 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL -- recommended setting Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6ull: misc soc updatePeng Fan2016-10-04-4/+4
| | | | | | | | | | Update misc SOC related settings for i.MX6ULL, such as FEC mac address, cpu speed grading and mmdc channel mask clearing. Also update s_init to skip pfd reset. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6ul: using runtime check when configuring PMIC_STBY_REQPeng Fan2016-10-04-1/+1
| | | | | | | | | Since MX6ULL select MX6UL, we can not use IS_ENABLED(CONFIG_MX6UL) here, because this piece code is only for i.MX6UL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
* imx: mx6ull: skip setting ahb clockPeng Fan2016-10-04-1/+1
| | | | | | | | | Rom already initialized clock at 396M and 132M for arm core and ahb, so skip setting them again in U-Boot. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
* imx: timer: update gpt driver for i.MX6ULLPeng Fan2016-10-04-3/+4
| | | | | | | | | | The i.MX6ULL's GPT supportting taking OSC as clock source. Add i.MX6ULL support. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
* imx-common: introduce is_mx6ullPeng Fan2016-10-04-0/+1
| | | | | | | Introduce is_mx6ull macro. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6ull: add kconfig entry for MX6ULLYe Li2016-10-04-0/+4
| | | | | | | | | i.MX6ULL is derivative from i.MX6UL, so select MX6UL for MX6ULL. If need to differenate MX6ULL from MX6UL, use CONFIG_MX6ULL Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6ull: add mx6ull major cpu typePeng Fan2016-10-04-1/+4
| | | | | | | | | Add i.MX6ULL major cpu type. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
* imx: mx6ull: add iomux header filePeng Fan2016-10-04-0/+1067
| | | | | | | | | Add iomux header file for i.MX6ULL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
* imx: iomux-v3: fix pad setup on i.MX6DQP when CONFIG_MX6QDL is definedFilip Brozovic2016-10-04-1/+1
| | | | | | | | The CPU detection macro is_mx6dq returns 0 on an i.MX6DQP, so we need to check for it explicitly in order to correctly initialize the pads when CONFIG_MX6QDL is defined. Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
* Merge git://git.denx.de/u-boot-rockchipTom Rini2016-10-03-25/+205
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| * rockchip: add boot-mode support for rk3288, rk3036Jacob Chen2016-10-01-5/+103
| | | | | | | | | | | | | | | | | | | | | | | | rockchip platform have a protocol to pass the the kernel reboot mode to bootloader by some special registers when system reboot. In bootloader we should read it and take action. We can only setup boot_mode in board_late_init becasue "setenv" need env setuped. So add CONFIG_BOARD_LATE_INIT to common header and use a entry "rk_board_late_init" to replace "board_late_init" in board file. Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: move common function from board-file to rk3036-board.cJacob Chen2016-10-01-0/+84
| | | | | | | | | | | | | | To keep it same with 3288 Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: rename board.c to rk3288-board.cJacob Chen2016-10-01-1/+1
| | | | | | | | | | Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: miniarm: remove eMMC supportXu Ziyuan2016-10-01-12/+0
| | | | | | | | | | | | | | The latest rk3288-miniarm board doesn't have eMMC device, so remove it. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * dts: evb-rk3399: add init voltage node for vdd-centerKever Yang2016-10-01-0/+1
| | | | | | | | | | | | | | | | | | | | | | Add a regulator-init-microvolt for vdd_center regulator so that we can get a init value for driver probe. Not like pmic regulator, the PWM regulator do not have a known default output value, so we would like to init the regulator when driver probe. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * Kconfig: rockchip: enable DM_PWM and DM_REGULATORKever Yang2016-10-01-0/+2
| | | | | | | | | | | | | | Enable DM_PWM and DM_REGULATOR on rockchip SoCs. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: rkpwm: fix the register sequenceKever Yang2016-10-01-1/+1
| | | | | | | | | | | | | | | | | | Reference to kernel source code, rockchip pwm has three type, we are using v2 for rk3288 and rk3399, so let's update the register to sync with pwm_data_v2 in kernel. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: rk3399: update PPLL and pmu_pclk frequencyKever Yang2016-10-01-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Update PPLL to 676MHz and PMU_PCLK to 48MHz, because: 1. 48MHz can make sure the pwm can get exact 50% duty ratio, but 99MHz can not, 2. We think 48MHz is fast enough for pmu pclk and it is lower power cost than 99MHz, 3. PPLL 676 MHz and PMU_PCLK 48MHz are the clock rate we are using internally for kernel,it suppose not to change the bus clock like pmu_pclk in kernel, so we want to change it in uboot. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * Disable SPL_MMC_SUPPORT if ROCKCHIP_SPL_BACK_TO_BROM is enabled.Sandy Patterson2016-10-01-0/+3
| | | | | | | | | | | | | | | | Default SPL_MMC_SUPPORT to false when ROCKCHIP_SPL_BACK_TO_BROM is enabled. Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com> Signed-off-by: Sandy Patterson <apatterson@sightlogix.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: Fix SPL console output when ROCKCHIP_SPL_BACK_TO_BROM is enabledSandy Patterson2016-10-01-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move back_to_bootrom() call later in SPL init so that the console is initialized and printouts happen. Currently when ROCKCHIP_SPL_BACK_TO_BROM is enabled there is no console output from the SPL init stages. I wasn't sure exactly where this should happen, so if we are set to do run spl_board_init, then go back to bootrom there after preloader_console_init(). Otherwise fall back to old behavior of doing it in board_init_f. Signed-off-by: Sandy Patterson <apatterson@sightlogix.com> Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: rk3288: sdram: fix DDR address rangeXu Ziyuan2016-10-01-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The all current Rockchip SoCs supporting 4GB of ram have problems accessing the memory region 0xfe000000~0xff000000. Actually, some IP controller can't address to, so let's limit the available range. This patch fixes a bug which found in miniarm-rk3288-4GB board. The U-Boot was relocated to 0xfef72000, and .bss variants was also relocated, such as do_fat_read_at_block. Once eMMC controller transfer data to do_fat_read_at_block via DMA, DMAC can't access more than 0xfe000000. So that DMAC didn't work sane. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | ti: omap-common: Allow AM33xx devices to be built securelyAndrew F. Davis2016-10-02-1/+1
| | | | | | | | | | | | | | | | | | | | Like OMAP54xx and AM43xx family SoCs, AM33xx based SoCs have high security enabled models. Allow AM33xx devices to be built with HS Device Type Support. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
* | am33xx: config.mk: Fix option used to enable SPI SPL image typeAndrew F. Davis2016-10-02-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | The option SPL_SPI_SUPPORT is used to enable support in SPL for loading images from SPI flash, it should not be used to determine the build type of the SPL image itself. The ability to read images from SPI flash does not imply the SPL will be booted from SPI flash. Unconditionally build SPI flash compatible SPL images. Signed-off-by: Andrew F. Davis <afd@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | am33xx: config.mk: Add support for additional secure boot image typesAndrew F. Davis2016-10-02-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Depending on the boot media, different images are needed for secure devices. The build generates u-boot*_HS_* files as appropriate for the different boot modes. For AM33xx devices additional image types are needed for various SPL boot modes as the ROM checks for the name of the boot mode in the file it loads. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
* | Kconfig: Separate AM33XX SOC config from target board configAndrew F. Davis2016-10-02-88/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The config option AM33XX is used in several boards and should be defined as a stand-alone option for this SOC. We break this out from target boards that use this SoC and common headers then enable AM33XX on in all the boards that used these targets to eliminate any functional change with this patch. This is similar to what has already been done in 9de852642cae ("arm: Kconfig: Add support for AM43xx SoC specific Kconfig") and is done for the same reasons. Signed-off-by: Andrew F. Davis <afd@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: omap5: add fdt secure dram reservation fixupDaniel Allred2016-10-02-2/+62
| | | | | | | | | | | | | | | | | | | | Adds a secure dram reservation fixup for secure devices, when a region in the emif has been set aside for secure world use. The size is defined by the CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE config option. Signed-off-by: Daniel Allred <d-allred@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: DRA7: Add secure emif setup callsDaniel Allred2016-10-02-0/+15
| | | | | | | | | | | | | | | | | | | | | | After EMIF DRAM is configured, but before it is used, calls are made on secure devices to reserve any configured memory region needed by the secure world and then to lock the EMIF firewall configuration. If any other firewall configuration needs to be applied, it must happen before the lock call. Signed-off-by: Daniel Allred <d-allred@ti.com>
* | arm: omap5: secure API for EMIF memory reservationsDaniel Allred2016-10-02-0/+151
| | | | | | | | | | | | | | | | | | | | | | Create a few public APIs which rely on secure world ROM/HAL APIs for their implementation. These are intended to be used to reserve a portion of the EMIF memory and configure hardware firewalls around that region to prevent public code from manipulating or interfering with that memory. Signed-off-by: Daniel Allred <d-allred@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ti: omap5: Add Kconfig options for secure EMIF reservationsDaniel Allred2016-10-02-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | Adds start address and size config options for setting aside a portion of the EMIF memory space for usage by security software (like a secure OS/TEE). There are two sizes, a total size and a protected size. The region is divided into protected (secure) and unprotected (public) regions, that are contiguous and start at the start address given. If the start address is zero, the intention is that the region will be automatically placed at the end of the available external DRAM space. Signed-off-by: Daniel Allred <d-allred@ti.com>
* | ARM: keystone2: Add support for parsing monitor headerLokesh Vutla2016-10-01-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Given that boot monitor image is being generated to a specific target location depending on the SoC and U-boot relies on addr_mon env variable to be aligned with boot monitor target location. When ever the target address gets updated in boot monitor, it is difficult to sync between u-boot and boot monitor and also there is no way to update user that boot monitor image is updated. To avoid this problem, boot monitor image is being generated with mkimage header. Adding support in mon_install command for parsing this header. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | board: k2g: Enable ECC byte laneLokesh Vutla2016-10-01-2/+1
| | | | | | | | | | | | | | Enable ECC byte lane for k2g-evm Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | input: specify the default of I8042_KEYB in more correct mannerMasahiro Yamada2016-10-01-3/+0
| | | | | | | | | | | | | | | | | | | | Creating multiple entries of "config FOO" often gives us bad experiences. In this case, we should specify "default X86" as platforms that want this keyboard by default. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* | sandbox, x86: select DM_KEYBOARD instead of default y entryMasahiro Yamada2016-10-01-6/+2
|/ | | | | | | | | | Once we migrate to DM-based drivers, we cannot go back to legacy ones, i.e. config options like DM_* are not user-configurable. Make SANDBOX and X86 select DM_KEYBOARD like other platforms do. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-nds32Tom Rini2016-09-30-73/+77
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| * nds32: Support relocation.rick2016-09-29-73/+77
| | | | | | | | | | | | | | Enable pie option for relocation. Signed-off-by: rick <rick@andestech.com> Cc: Andes <uboot@andestech.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-09-30-1/+31
|\ \ | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: include/configs/dra7xx_evm.h
| * | ARM: dts: vf-colibri: Enable USB device tree node for Colibri VybridSanchayan Maity2016-09-27-0/+11
| | | | | | | | | | | | | | | | | | Enable USB device tree node for Toradex Colibri Vybrid module. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
| * | ARM: dts: vf: Add device tree node for USB on VybridSanchayan Maity2016-09-27-0/+14
| | | | | | | | | | | | | | | | | | Add device tree node for USB peripheral on Vybrid. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
| * | dra7x: boot: add dfu bootmode supportB, Ravi2016-09-27-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | This patch enables the DFU boot mode support for dra7x platform. Signed-off-by: Ravi Babu <ravibabu@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | mpc85xx: powerpc: usb: Update the list of Socs afftected by erratum A006261Sriram Dash2016-09-28-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Apply the erratum A006261 for the following Socs: P2041 rev 2.0, P2040 rev 2.0, P5040 rev 2.0, 2.1 Do not apply erratum A006261 for the following Socs: T4160, T4080, T1040, T1042, T1020, T1022, T2080, T2081 Erratum A006261 is applicable for the following Socs: P1010(1.0, 2.0), P2041(1.0, 1.1, 2.0, 2.1), P2040(1.0, 1.1, 2.0, 2.1), P3041(1.0, 1.1, 2.0, 2.1), P5010(1.0, 2.0), P5020(1.0, 2.0), P5021(1.0, 2.0), T4240(1.0, 2.0), P5040(1.0,2.0,2.1). Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | mpc85xx: powerpc: usb: Enable Usb phy initialisation settings for P1010Sriram Dash2016-09-28-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_SYS_FSL_USB1_PHY_ENABLE is set and the USB Phy offset are set to enable the initial setting of Usb Phy for P1010. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | mpc85xx: powerpc: usb: Modified the erratum A006261 according to endiannessSriram Dash2016-09-28-2/+2
| |/ |/| | | | | | | | | | | | | | | | | Modifies erratum implementation due to the fact that P3041, P5020, and P5040 are all big endian for the USB PHY registers, but they were specified little endian. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2016-09-27-673/+2730
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| * | ARM: tegra: flush caches via SMC callStephen Warren2016-09-27-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Tegra186, it is necessary to perform an SMC to fully flush all caches; flushing/cleaning by set/way is not enough. Implement the required hook to make this happen. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: fix ULPI PHY on Ventana and SeaboardStephen Warren2016-09-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit ce02a71c2374 "tegra: dts: Sync tegra20 device tree files with Linux" enabled the ULPI USB port on Ventana, but made no attempt to ensure that U-Boot code could handle this. In practice, various code is missing, and various configuration options are not enabled, which causes U-Boot to hang when attempting to initialize this USB port. This patch enables ULPI PHY support on Ventana, and adds the required pinmux setup for the port to operate. Note that Ventana is so similar to Seaboard that this change is made in the Seaboard board file, which is shared with Ventana. Seaboard also has the ULPI USB port wired up in hardware, although to an internal port that often doesn't have anything attached to it. However, the DT nodes for the USB controller and PHY had different status property values, so the port was not initialized by U-Boot. Fix this inconsistency, and enable the ULPI port, just like in the Linux kernel DT. This likewise requires enabling ULPI support in the Seaboard defconfig. Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: fix USB controller aliasesStephen Warren2016-09-27-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some boards have a different set of USB controllers enabled in DT than the set referenced by /alias entries. This patch fixes that. For example, this avoids the following message while booting on Ventana, which is caused by the fact that the USB0 controller had no alias, and defaulted to wanting a sequence number of 0, which was later explicitly requested by the alias for USB controller 2. USB2: Device 'usb@c5008000': seq 0 is in use by 'usb@c5000000' This didn't affect USB operation in any way though. Related, there's no need for the USB controller aliases to have an order that's different from the HW order, so re-order any aliases to match the HW ordering. This has the benefit that since USB controller 0 is the only one that supports device-mode in HW, and U-Boot only supports enabling device move on controller 0, there's now good synergy in the ordering! For Tegra20, that's not relevant at present since USB device mode doesn't work correctly on that SoC, but it will save some head-scratching later. This patch doesn't fix the colibri_t20 board, even though it has the same issue, since Marcel already sent a patch for that. Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-on: Harmony and Ventana
| * | ARM: tegra: fix USB ULPI PHY reset signal inversion confusionStephen Warren2016-09-27-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USB ULPI PHY reset signals are typically active low. Consequently, they should be marked as GPIO_ACTIVE_LOW in device tree, and indeed they are in the Linux kernel DTs, and in DT properties that U-Boot doesn't yet use. However, in DT properties that U-Boot does use, the value has been set to 0 (== GPIO_ACTIVE_HIGH) to work around a bug in U-Boot. This change fixes the DT to correctly represent the HW, and fixes the Tegra USB driver to cope with the fact that dm_gpio_set_value() internally handles any inversions implied by the DT value GPIO_ACTIVE_LOW. Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: enable standard clock/reset APIs everywhereStephen Warren2016-09-27-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implementations of the standard clock and reset APIs are available on all Tegra SoCs now, so enable compilation of those uclasses. Enable the Tegra CAR drivers for all SoCs prior to the BPMP being available. This provides an implementation of those APIs everywhere. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
generated by cgit v1.1 at 2024-09-17 19:43:39 +0000