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* arm: socfpga: Make /soc available in pre-relocMarek Vasut2015-12-22-0/+4
* arm: socfpga: Actually enable L2 cacheMarek Vasut2015-12-22-2/+11
* Merge branch 'master' of git://www.denx.de/git/u-boot-socfpgaTom Rini2015-12-19-11/+119
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| * arm: socfpga: fix up a questionable macro for SDMMCDinh Nguyen2015-12-20-3/+7
| * arm: socfpga: remove building scan managerDinh Nguyen2015-12-20-2/+3
| * arm: socfpga: introduce TARGET_SOCFPGA_GEN5 config propertyDinh Nguyen2015-12-20-0/+5
| * arm: socfpga: Introduce common board codeMarek Vasut2015-12-20-1/+65
| * arm: socfpga: socrates: Probe DWC2 UDC from OF instead of hard-coded dataMarek Vasut2015-12-20-0/+8
| * arm: socfpga: sockit: Probe DWC2 UDC from OF instead of hard-coded dataMarek Vasut2015-12-20-2/+7
| * arm: socfpga: mcvevk: Probe DWC2 UDC from OF instead of hard-coded dataMarek Vasut2015-12-20-0/+5
| * arm: socfpga: de0_nano: Probe DWC2 UDC from OF instead of hard-coded dataMarek Vasut2015-12-20-0/+5
| * arm: socfpga: cyclone5-socdk: Probe DWC2 UDC from OF instead of hard-coded dataMarek Vasut2015-12-20-4/+5
| * arm: socfpga: arria5-socdk: Probe DWC2 UDC from OF instead of hard-coded dataMarek Vasut2015-12-20-0/+1
| * arm: socfpga: socrates: Add missing PHY skew configMarek Vasut2015-12-20-0/+9
* | nios2: display altera sysid at startupThomas Chou2015-12-19-0/+8
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* microblaze: Enable DM by defaultMichal Simek2015-12-18-0/+1
* microblaze: Enable OF_CONTROL by defaultMichal Simek2015-12-18-0/+1
* arm: zynq: Update ZYBO config optionsNathan Rossi2015-12-18-0/+16
* ARM: zynq: Add default ps7_init_gpl.c/h for ZYBONathan Rossi2015-12-18-1/+0
* ARM: zynq: Enable u-boot,dm-pre-reloc for sdhciMichal Simek2015-12-18-0/+6
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-12-17-1/+19
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| * armv8/ls1043a: Implement workaround for PEX erratum A009929Mingkai Hu2015-12-17-0/+18
| * armv8/fsl_lsch2: fix DCSR_DCFG addressMingkai Hu2015-12-17-1/+1
* | Merge git://git.denx.de/u-boot-rockchipTom Rini2015-12-16-28/+9
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| * rockchip: Add basic support for kylin boardhuang lin2015-12-13-0/+4
| * rockchip: rk3036 sdram setting cs1_row when rank larger than 1huang lin2015-12-13-1/+5
| * Revert "rockchip: Add max spl size & spl header configs"Jeffy Chen2015-12-13-27/+0
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-12-14-85/+415
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| * | armv8: Add sata support on Layerscape ARMv8 boardTang Yuantian2015-12-15-0/+78
| * | armv8/ls1043ardb: add SECURE BOOT target for NORAneesh Bansal2015-12-15-4/+8
| * | armv8: Make SEC read/write as snoopable for LS1043Aneesh Bansal2015-12-15-0/+5
| * | armv8: define usec2ticks functionAneesh Bansal2015-12-15-0/+11
| * | armv8: fsl-layerscale: Rewrite reserving memory for MC and debug serverYork Sun2015-12-15-0/+21
| * | armv8: fsl-layerscape: Make DDR non secure in MMU tablesYork Sun2015-12-15-19/+122
| * | move erratum a008336 and a008514 to soc specific fileYao Yuan2015-12-15-0/+37
| * | armv7/fsl-ls102xa: Workaround for DDR erratum A008514Yao Yuan2015-12-15-1/+11
| * | armv7: ls102xa: cci-400: Enable snoop and DVM message requests.Yao Yuan2015-12-15-1/+7
| * | arm: ls102xa: enable all the snoop signal for masters.Yao Yuan2015-12-13-0/+14
| * | arm: ls1021a: merge SoC specific code in a separate fileYao Yuan2015-12-13-0/+79
| * | fsl_*_serdes.c: Modify memset call in serdes_initTom Rini2015-12-13-3/+3
| * | armv8/ls1043ardb: Add support for >2GB memoryShaohui Xie2015-12-13-2/+2
| * | fsl/ddr: updated ddr errata-A008378 for arm and power SoCsShengzhou Liu2015-12-13-0/+2
| * | fsl/errata: move fsl_errata.h to common directoryShengzhou Liu2015-12-13-56/+3
| * | arm: ls102x: add get_svr and IS_SVR_REV helperShengzhou Liu2015-12-13-0/+13
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* | armv7: omap-common: Rework SPL board_mmc_init()Tom Rini2015-12-14-0/+1
* | m68k: add private libgccangelo@sysam.it2015-12-13-0/+176
* | am33xx,ddr3: fix ddr3 sdram configurationEgli, Samuel2015-12-12-1/+10
* | stm32: Convert serial driver to DMKamil Lulko2015-12-12-1/+11
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* sunxi: Fix H3 DRAM DQ read delay configurationJens Kuske2015-12-10-6/+6
* sun4i: clock: Cleanup some whitespace errorsOlliver Schinagl2015-12-10-3/+3
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