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* Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2014-01-06-465/+3892
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| * DTS: Add dts support for SMDK5420Rajeshwari Birje2013-12-30-190/+272
| | | | | | | | | | | | | | | | | | | | | | This patch adds dts support for SMDK5420. exynos5.dtsi created is a common file which has the nodes common to both 5420 and 5250. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos5420: Add support for 5420 in pinmux and gpioRajeshwari Birje2013-12-30-16/+390
| | | | | | | | | | | | | | | | | | | | Adds code in pinmux and gpio framework to support Exynos5420. Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos5420: Add DDR3 initialization for 5420Rajeshwari Birje2013-12-30-58/+484
| | | | | | | | | | | | | | | | | | This patch intends to add DDR3 initialization code for Exynos5420. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos5420: Add clock initialization for 5420Rajeshwari Birje2013-12-30-202/+1679
| | | | | | | | | | | | | | | | | | | | This patch adds code for clock initialization and clock settings of various IP's and controllers, required for Exynos5420 Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * EXYNOS5420: Add dmc and phy_control register structureRajeshwari Birje2013-12-30-0/+167
| | | | | | | | | | | | | | | | Add dmc and phy_control register structure for 5420. Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * EXYNOS5420: Add power register structure.Rajeshwari Birje2013-12-30-0/+837
| | | | | | | | | | | | | | | | Add structure for power register for Exynos5420 Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos5420: Add base addresses for 5420Rajeshwari Birje2013-12-30-1/+48
| | | | | | | | | | | | | | | | | | | | Adds base addresses of various IPs and controllers required for Exynos5420. Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * EXYNOS5: Create a common board fileRajeshwari Birje2013-12-30-0/+17
| | | | | | | | | | | | | | | | | | | | | | Create a common board.c file for all functions which are common across all EXYNOS5 platforms. exynos_init function is provided for platform specific code. Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-01-06-3308/+2329
|\ \ | |/ |/| | | | | | | | | | | Conflicts: include/micrel.h The conflict above was trivial, caused by four lines being added in both branches with different whitepace.
| * arm: mx5: Add fuse supply enable in fsl_iimSergey Alyoshin2014-01-03-0/+16
| | | | | | | | | | | | | | Enable fuse supply before fuse programming and disable after. Signed-off-by: Sergey Alyoshin <alyoshin.s@gmail.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * ARM: mx6: Allow enablement of FEC Anatop based clock for all MX6Otavio Salvador2014-01-03-10/+11
| | | | | | | | | | | | | | | | | | | | The enable_fec_anatop_clock method should be available for all MX6 variant as it is not MX6 SoloLite specific. This moves the code out of the #ifdef/#endif and we make it conditional to CONFIG_FEC_MXC instead. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de>
| * imx: Easy enabling of SION per-pin using MUX_MODE_SION helper macroOtavio Salvador2014-01-03-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The macro allows easy setting in per-pin, as for example: ,---- | imx_iomux_v3_setup_pad(MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_MODE_SION); `---- The IOMUX_CONFIG_SION allows for reading PAD value from PSR register. The following quote from the datasheet: ,---- | ... | 28.4.2.2 GPIO Write Mode | The programming sequence for driving output signals should be as follows: | 1. Configure IOMUX to select GPIO mode (Via IOMUXC), also enable SION if need | to read loopback pad value through PSR | 2. Configure GPIO direction register to output (GPIO_GDIR[GDIR] set to 1b). | 3. Write value to data register (GPIO_DR). | ... `---- This fixes the gpio_get_value to properly work when a GPIO is set for output and has no conflicts. Thanks for Benoît Thébaudeau <benoit.thebaudeau@advansee.com>, Fabio Estevam <fabio.estevam@freescale.com> and Eric Bénard <eric@eukrea.com> for helping to properly trace this down. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de>
| * mx6: soc: Disable VDDPU regulatorFabio Estevam2014-01-02-0/+65
| | | | | | | | | | | | | | | | | | As U-boot does not use GPU/VPU peripherals, shutdown the VDDPU regulator in order to save power. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6: soc: Add the required LDO ramp up delayFabio Estevam2014-01-02-3/+19
| | | | | | | | | | | | | | | | | | | | When changing LDO voltages we need to wait for the required amount of time for the voltage to settle. Also, as the timer is still not available when arch_cpu_init() is called, we need to call it later at board_postclk_init() phase. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6: soc: Introduce set_ldo_voltage()Fabio Estevam2014-01-02-7/+26
| | | | | | | | | | | | Introduce set_ldo_voltage() so that all three LDO regulators can be configured. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6: soc: Set the VDDSOC at 1.175 VFabio Estevam2014-01-02-1/+1
| | | | | | | | | | | | | | | | | | | | mx6 datasheet specifies that the minimum VDDSOC at 792 MHz is 1.15 V. Add a 25 mV margin and set it to 1.175V. This also matches the VDDSOC voltages for 792MHz operation that the kernel configures: http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/cpu_op-mx6.c?h=imx_3.0.35_4.1.0 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6: soc: Clear the LDO ramp values up prior to setting the LDO voltagesFabio Estevam2014-01-02-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since ROM may modify the LDO ramp up time according to fuse setting, it is safer to reset the ramp up field to its default value of 00: 00: 64 cycles of 24MHz clock; 01: 128 cycles of 24MHz clock; 02: 256 cycles of 24MHz clock; 03: 512 cycles of 24MHz clock; Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6: soc: Staticize set_vddsoc()Fabio Estevam2014-01-02-3/+1
| | | | | | | | | | | | set_vddsoc() is not used anywhere else, so make it static. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * MX6: fix sata compilation for i.MX6Stefano Babic2013-12-19-1/+2
| | | | | | | | | | | | | | Commit 164d98466103a46b7c881149e92ec2a28a6375be breaks board with SATA support, because sata is not compiled. Signed-off-by: Stefano Babic <sbabic@denx.de>
| * imx6: fix random hang when download by usbFrank Li2013-12-17-0/+2
| | | | | | | | | | | | | | | | ROM did not invalidate L1 cache when download by usb Need invalidate L1 cache before enable cache Signed-off-by: Huang yongcai <b20788@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com>
| * mx6: clock: Fix the calculation of PLL_ENET frequencyFabio Estevam2013-12-17-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the mx6 quad reference manual, the DIV_SELECT field of register CCM_ANALOG_PLL_ENETn has the following meaning: "Controls the frequency of the ethernet reference clock. - 00 - 25MHz - 01 - 50MHz - 10 - 100MHz - 11 - 125MHz" Current logic does not handle the 25MHz case correctly, so fix it. Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * nitrogen6x: Move setup_sata to common partGiuseppe Pagano2013-12-17-0/+52
| | | | | | | | | | | | | | | | | | | | Move setup_sata function definition from platform file nitrogen6x.c to arch/arm/imx-common/sata.c to avoid code duplication. Signed-off-by: Giuseppe Pagano <giuseppe.pagano@seco.com> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Eric Nelson <eric.nelson@boundarydevices.com>
| * i.MX6 (DQ/DLS): use macros for mux and pad declarationsEric Nelson2013-12-17-2106/+2118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows the use of either or both declarations from the files mx6q_pins.h and mx6dl_pins.h. All board files should include <asm/arch/mx6-pins.h> with one of the following defined in boards.cfg MX6Q - for boards targeting i.MX6Q or i.MX6D MX6DL - for boards targeting i.MX6DL MX6S - for boards targeting i.MX6S MX6QDL - for boards that support any of the above with run-time detection Pad declarations will be MX6_PAD_x for single-variant boards and MX6Q_PAD_x and MX6DL_PAD_x for boards supporting both processor classes. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * imx-common: remove extraneous semicolon from macroEric Nelson2013-11-27-2/+2
| | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| * i.MX6DQ/DLS: whitespace: Align IOMUX_PAD column in declarationsEric Nelson2013-11-13-490/+490
| | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| * i.MX6DQ/DLS: remove unused pad declarationsEric Nelson2013-11-13-1043/+0
| | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| * i.MX6DQ: Add Pinmux settings that are present in mainline and Dual-Lite/SoloEric Nelson2013-11-13-0/+24
| | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| * i.MX6DQ/DLS: remove useless mux/pad declarationsEric Nelson2013-11-13-160/+0
| | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| * i.MX6DQ/DLS: replace pad names with their Linux kernel equivalentsEric Nelson2013-11-13-1761/+1761
| | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* | ARM: AM43xx: GP_EVM: Add support for DDR3Lokesh Vutla2013-12-18-16/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH). Adding details for the same. Below is the brief description of DDR3 init sequence(SW leveling): -> Enable VTT regulator -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program leveling registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: AM43xx: EPOS_EVM: Add support for LPDDR2Lokesh Vutla2013-12-18-3/+190
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A) Adding LPDDR2 init sequence and register details for the same. Below is the brief description of LPDDR2 init sequence: -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register -> Wait till initialization is complete and the configure MR registers. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: AM33xx+: Update ioregs to pass different valuesLokesh Vutla2013-12-18-9/+23
| | | | | | | | | | | | | | | | | | | | | | Currently same value is programmed for all ioregs. This is not the case for all SoC's like AM4372. So adding a structure for ioregs and updating in all board files. And also return from config_cmd_ctrl() and config_ddr_data() functions if data is not passed. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> [trini: Fixup dxr2, cm_t335, adapt pcm051 rev3] Signed-off-by: Tom Rini <trini@ti.com>
* | ARM: AM43xx: clocks: Update DPLL detailsLokesh Vutla2013-12-18-14/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updating the Multiplier and Dividers value for all DPLLs. Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value returned the MPU DPLL is locked. At different OPPs follwoing are the MPU locked frequencies. OPP50 300MHz OPP100 600MHz OPP120 720MHz OPPTB 800MHz OPPNT 1000MHz According to the latest DM following is the OPP table dependencies: VDD_CORE VDD_MPU OPP50 OPP50 OPP50 OPP100 OPP100 OPP50 OPP100 OPP100 OPP100 OPP120 So at different OPPs of MPU it is safest to lock CORE at OPP_NOM. Following are the DPLL locking frequencies at OPP NOM: Core locks at 1000MHz Per locks at 960MHz LPDDR2 locks at 266MHz DDR3 locks at 400MHz Touching AM33xx files also to get DPLL values specific to board but no functionality difference. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: AM43xx: mux: Update mux dataLokesh Vutla2013-12-18-0/+45
| | | | | | | | | | | | | | Updating the mux data for UART, adding data for i2c0 and mmc. And also updating pad_signals structure. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: AM43xx: Update Current Booting devices listLokesh Vutla2013-12-18-3/+10
| | | | | | | | | | | | | | Current Booting devices list is different from that of AM33xx. Updating the same. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: AM43xx: Select clk source for Timer2Lokesh Vutla2013-12-18-0/+4
| | | | | | | | | | | | Selecting the Master osc clk as Timer2 clock source. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: AM43XX: board: add support for reading onboard EEPROMSekhar Nori2013-12-18-0/+2
| | | | | | | | | | | | | | | | Add support for reading onboard EEPROM to enable board detection. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: AM43xx: Adapt to ti_armv7_common.h config fileLokesh Vutla2013-12-18-1/+1
| | | | | | | | | | | | | | Use ti_armv7_common.h config file to inclde the common configs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: AM43xx: Update the base addresses of modulesLokesh Vutla2013-12-18-13/+15
| | | | | | | | | | | | | | PRCM, timer base addresses and offsets are different from AM33xx. Updating the same. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | Merge remote-tracking branch 'u-boot-pxa/master' into 'u-boot-arm/master'Albert ARIBAUD2013-12-18-0/+1
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| * | ARM: pxa: prevent PXA270 occasional reboot freezesSergei Ianovich2013-12-18-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Erratum 71 of PXA270M Processor Family Specification Update (April 19, 2010) explains that watchdog reset time is just 8us insead of 10ms in EMTS. If SDRAM is not reset, it causes memory bus congestion and the device hangs. We put SDRAM in selfresh mode before watchdog reset, removing potential freezes. Signed-off-by: Sergei Ianovich <ynvich@gmail.com> CC: Marek Vasut <marex@denx.de>
* | | arm: tegra: Fix the CPU complex reset masksAlban Bedel2013-12-18-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CPU complex reset masks are not matching with the datasheet for the CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 registers. For both T20 and T30 the register consist of groups of 4 bits, with one bit for each CPU core. On T20 the 2 high bits of each group are always stubbed as there is only 2 cores. Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swrren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | ARM: tegra: support SKU b1 of Tegra30Alban Bedel2013-12-18-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Add the Tegra30 SKU b1 and treat it like other Tegra30 chips. Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> Reviewed-by: Julian Scheel <julian.scheel@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | Tegra114: Do not program CPCON field for PLLXThierry Reding2013-12-18-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | PLLX no longer has the CPCON field on Tegra114, so do not attempt to program it. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | Tegra114: Fix PLLX M, N, P init settingsJimmy Zhang2013-12-18-24/+59
|/ / | | | | | | | | | | | | | | | | | | | | | | The M, N and P width have been changed from Tegra30. The maximum value for N is limited to 255. So, the tegra_pll_x_table for Tegra114 should be set accordingly. Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Reviewed-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: OMAP5: clocks: Update MPU settings for OPP_NOMLokesh Vutla2013-12-12-12/+2
| | | | | | | | | | | | | | | | | | | | As per the latest 0.6 version of DM for OMAP5430 ES2.0, MPU_GCLK is given as 1000MHz. In order to achieve this DPLL_MPU should be locked at 2000MHz. Fixing the same and cleaning the previously used dpll values. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: DRA7xx: Change clk divider settingLokesh Vutla2013-12-12-5/+5
| | | | | | | | | | | | | | | | | | Commit "armv7: hw_data: change clock divider setting" updates the setting for m6 divider for 20MHz sys_clk frequency. But missed to update for other sys_clk frequencies. Doing the same. Reported-by: Rajendran, Vinothkumar <vinothr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | arm: omap: abb: add missing includeNikita Kiryanov2013-12-12-0/+1
| | | | | | | | | | | | | | | | | | | | | | ABB code uses LDELAY but does not include the header that provides its definition. Include the header. Cc: Tom Rini <trini@ti.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Nishanth Menon <nm@ti.com>
* | arm: am437: Fix offset for USB registersDan Murphy2013-12-12-2/+2
| | | | | | | | | | | | Fix the offset for the USB clock registers Signed-off-by: Dan Murphy <dmurphy@ti.com>
generated by cgit v1.1 at 2024-08-26 19:40:27 +0000