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* m68k:correct io macros about endianChao Fu2014-06-19-4/+4
| | | | | | M68k is big endian cpu ,so use be_out and be_in in big endian. Signed-off-by: Chao Fu <b44548@freescale.com>
* m68k: eliminate a warning in cpu_initMasahiro Yamada2014-06-19-1/+1
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* Remove ${objtree}/include/asm/proc/ linkVasili Galka2014-06-11-5/+5
| | | | | | | | | | | | mkconfig links ${objtree}/include/asm/proc/ to ${srctree}/arch/${arch}/include/asm/proc-armv/. This seems to be a remnant from the past. Ever since its introduction in 2003 it is used only in ARM build and always links to same place, so let's simplify the code, remove it and reference directly where needed. Successful MAKEALL for ARM and PowerPC verified on Linux. Signed-off-by: Vasili Galka <vvv444@gmail.com>
* cosmetic: Whitespace fixVasili Galka2014-06-11-2/+2
| | | | Signed-off-by: Vasili Galka <vvv444@gmail.com>
* m68k: Fix warnings with gcc 4.6Simon Glass2014-06-11-7/+4
| | | | | | | | Most of the warnings seem to be related to using 'int' for size_t. Change this and fix up the remaining warnings and problems. For bootm, the warning was masked by others, and there is an actual bug in the code. Signed-off-by: Simon Glass <sjg@chromium.org>
* Check run_command() return code properlyThomas Betker2014-06-11-1/+1
| | | | | | | | | | run_command() returns 0 for success, 1 for failure. Fix places which assume that failure is indicated by a negative return code. Signed-off-by: Thomas Betker <thomas.betker@rohde-schwarz.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Tested-by: Stefan Roese <sr@denx.de>
* am33xx/omap: Enable CONFIG_OF_CONTROLSimon Glass2014-06-11-0/+1097
| | | | | | | Add support for device tree control and add device tree files for the beaglebone black initially. Signed-off-by: Simon Glass <sjg@chromium.org>
* am33xx/omap: Allow cache enable for all Sitara/OMAPSimon Glass2014-06-11-58/+60
| | | | | | | | | Enable the cache for all devices, unless CONFIG_SYS_DCACHE_OFF is defined. This speeds up the Beaglebone Black boot considerable. (Tested only on Beaglebone Black with SD card boot) Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-06-08-80/+250
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| * Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2014-06-08-31/+83
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| | * arm:am33xx: Add a scale_vcores() hookTom Rini2014-06-06-0/+12
| | | | | | | | | | | | | | | | | | | | | Similar to OMAP4/5 we need to scale the voltage up prior to changing the clock frequencies up higher. Add a similar hook to start with. Signed-off-by: Tom Rini <trini@ti.com>
| | * arch-am33xx: Add defines for timer0-7Hannes Petermaier2014-06-06-6/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For usage of timer6 within B&R we need this defines to enable clock modules and clk-source. Also the 'Timer register bits' are expanded. By the way we add defines for all timers within AM335x SoC. Cc: trini@ti.com Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
| | * ARM: AM43xx: Fix UART clocks enablingLokesh Vutla2014-06-06-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After enabling a module, SW has to wait on IDLEST bit until it is Fully functional. This wait is missing for UART module and there is a immediate access of UART registers after this. So there is a chance of hang on this module( This can happen when we are running from MPU SRAM). So waiting for IDLEST bit. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| | * keystone: init: enable UART1 to be able use it from kernelMurali Karicheri2014-06-06-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently PWREMU_MGMT is not configured in the Linux generic UART driver as this register seems to be specific TI UART IP. So this needs to be enabled in u-boot to use UART1 from kernel space. Acked-By: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * arm:am33xx: Rework s_init and add board_early_init_fTom Rini2014-06-06-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the changes to the i2c framework (and adopting the omap24xx_i2c driver to them) we can no longer call i2c functions prior to gd having been set and cleared. When SPL booting, this is handled by setting gd to point to SRAM in s_init. However in the cases where we are loaded directly by ROM (memory mapped NOR or QSPI) we need to make use of the normal hooks to slightly delay these calls. Signed-off-by: Tom Rini <trini@ti.com>
| | * arm:am33xx: Make dram_init call sdram_init() in some contextsTom Rini2014-06-06-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have two contexts for booting these platforms. One is SPL which is roughly: reset, cpu_init_crit, lowlevel_init, s_init, sdram_init, _main, board_init_f from SPL, ... then U-Boot loads. The other is a memory-mapped XIP case (NOR or QSPI) where we do not run an SPL. In this case we go, roughly: reset, cpu_init_crit, lowlevel_init, s_init, _main, regular board_init_f. In the first case s_init will set a valid gd and then be able to call sdram_init which in many cases will need i2c (which needs a valid gd for gd->cur_i2c_bus). In this second case we must (and are able to and should) defer sdram_init() into dram_init() called by board_init_f as gd will have been set in _main and cleared in board_init_f. Signed-off-by: Tom Rini <trini@ti.com>
| | * am43xx_evm: Add qspiboot targetSourav Poddar2014-06-06-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ePOS EVM and EVM SK have QSPI as an option to boot. Add a qspiboot target that utilizes QSPI for env and so forth as an example of best practices. As QSPI is booted from directly we need to chang CONFIG_SYS_TEXT_BASE. Note that on ePOS EVM the QSPI and NAND are mutually exclusive choices we need to handle that elsewhere, once NAND support is also added. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
| | * omap3: remove remnant macros GPMC_NAND_ECC_LP_x8_LAYOUT and ↵pekon gupta2014-06-06-20/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPMC_NAND_ECC_LP_x16_LAYOUT OMAP3 used GPMC_NAND_ECC_LP_x8_LAYOUT and GPMC_NAND_ECC_LP_x16_LAYOUT macros to configure GPMC controller for x7 or x8 bit device connected to its interface. Now this information is encoded in CONFIG_SYS_NAND_DEVICE_WIDTH macro, so above macros can be completely removed. Signed-off-by: Pekon Gupta <pekon@ti.com>
| * | ARM: tegra: enable USB device mode and UMS on some boardsStephen Warren2014-06-05-3/+24
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For each of Jetson TK1, Venice2, and Beaver: - Enable the first USB controller in DT, and describe its configuration. - Enable USB device/gadget support. This allows the user to type e.g. "ums 0 mmc 0" at the command-line to cause U-Boot to act a USB device implementing the USB Mass Storage protocol, and expose MMC device 0 that way. This allows a host PC to mount the Tegra device's MMC, partition it, and install a filesystem on it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2014-06-02-46/+143
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| | * Exynos: Make sure ps_hold gets set in the SPLDoug Anderson2014-05-31-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Setting ps_hold ought to be one of the first things we do when we first boot up. If we wait until the main u-boot runs we won't set it in time and the PMIC may power us back off. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * exynos: dts: Enable LCD for snowSimon Glass2014-05-28-0/+57
| | | | | | | | | | | | | | | | | | | | | Enable LCD for snow. This is a 1366 x 768 panel. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * exynos: Enable PSHOLD in SPLSimon Glass2014-05-28-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is quite a tight deadline in enabling PSHOLD, less than a second. In some cases (e.g. with USB download), U-Boot takes longer than that to load, so the board powers off before U-Boot starts. Add a call in SPL to enable PSHOLD. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * exynos: dts: Correct EC interrupt GPIOSimon Glass2014-05-28-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Now that the GPIO numbering series has been applied, we can use the correct GPIO for the EC interrupt. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * ARM: dts: exnyos: enable dw-mmc controllerJaehoon Chung2014-05-16-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enabled the dw-mmc controller. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * ARM: dts: exynos: rename from EXYNOS5_DWMMC to EXYNOS_DWMMCJaehoon Chung2014-05-16-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Exynos serise can be supported the dw-mmc controller. So, it's good that used the general prefix as "_EXYNOS_DWMMC". Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * ARM: exynos: clock: modify the set_mmc_clk for exynos4Jaehoon Chung2014-05-16-5/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modified the mmc_set_clock for eynos4. The goal of this patch is that fsys-div register should be reset. And retore the div-value, not using the value of lowlevel_init. (For using SDMMC4, this patch is needs) Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * board: trats2: Enable device tree on Trats2Beomho Seo2014-05-16-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add dwmmc emmc controller node on exynos4 and exynos4412 device tree. Signed-off-by: Beomho Seo <beomho.seo@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Piotr Wilczek <p.wilczek@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Piotr Wilczek <p.wilczek@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * arm: exynos: clock: Remove exynos4x12_set_mmc_clk functionBeomho Seo2014-05-16-28/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | exynos4x12_set_mmc_clk function have been removed. Because, exynos4x12_clock and exynos4_clock return same div_fsys* value. Signed-off-by: Beomho Seo <beomho.seo@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Piotr Wilczek <p.wilczek@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Piotr Wilczek <p.wilczek@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * arm: exynos: pinmux: add sdmmc4 gpio configratuionBeomho Seo2014-05-16-6/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For use dwmmc controller at exynos4, add SDMMC4 gpio configuration. Signed-off-by: Beomho Seo <beomho.seo@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Piotr Wilczek <p.wilczek@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Piotr Wilczek <p.wilczek@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-06-05-6/+469
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| * | | powerpc/mpc85xx: Add workaround to enable TDM on T1040Sandeep Singh2014-06-05-1/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a workaround for 32 bit hardware limitation of TDM. T1040 has 36 bit physical addressing, TDM DMAC register are 32 bit wide but need to store address of CCSR space which lies beyond 32 bit address range. This workaround creats a LAW to enable access of TDM DMA to CCSR by mapping CCSR to overlap with DDR. A hole of 16M is created in memory using device tree. This workaround law is set only if "tdm" is defined in hwconfig. Also disable POST tests and add LIODN for TDM Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | powerpc/serdes: Add the workaround for erratum A-007186Shaveta Leekha2014-06-05-2/+188
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SerDes PLL is calibrated at reset. When the junction temperature delta from the time the PLL is calibrated exceeds +56C/-66C, jitter may increase and can cause PLL to unlock. This workaround overwrite the SerDes registers with new values, to calibrate SerDes registers. These values are known to work fine for all temperature ranges. This workaround is valid for B4, T4 and T2 platforms, so added in their config. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com> [York Sun: replaced typedef ccsr_sfp_regs_t with struct ccsr_sfp_regs] Reviewed-by: York Sun <yorksun@freescale.com>
| * | | powerpc/mpc85xx: Add workaround for DDR erratum A004508York Sun2014-06-05-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the DDR controller is initialized below a junction temperature of 0°C and then operated above a junction temperature of 65°C, the DDR controller may cause receive data errors, resulting ECC errors and/or corrupted data. This erratum applies to the following SoCs and their variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023, P2020. Signed-off-by: York Sun <yorksun@freescale.com>
| * | | powerpc/t2080: add serdes2 protocol 0x27Shengzhou Liu2014-06-05-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new serdes2 protocol 0x27. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | powerpc/t4qds: Add alternate serdes protocols to align with A-007186Shaohui Xie2014-06-05-0/+172
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A-007186: SerDes PLL is calibrated at reset. It is possible for jitter to increase and cause the PLL to unlock when the temperature delta from the time the PLL is calibrated exceeds +56C/-66C when using X VDD of 1.35 V (or +70C/-80C when using XnVDD of 1.5 V). No issues are seen with LC VCO. Only the protocols using Ring VCOs are impacted. Workaround: For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring VCO, this need to use alternate serdes protocols. The alternate option has the same functionality as the original option; the only difference being LC VCO rather than Ring VCO. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | board/t208x: update t2080qds/t2080rdb for errata A-007186Shengzhou Liu2014-06-05-3/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As errata A-007186, we need to use the alternate serdes protocol instead of those impacted protocols. - add support for serdes protocols: 0x1b, 0x50, 0x5e, 0x64, 0x6a, 0xd2, 0x67, 0x70. - update t2080_rcw.cfg to adapt to new rcw_66_15 for t2080qds and t2080rdb. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | | nand_spl: remove nand_spl infrastructureMasahiro Yamada2014-06-05-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the common infrastructure of nand_spl and clean-up the code inside ifdef(CONFIG_NAND_U_BOOT)..endif. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | | kbuild: move cmd_mkimage to scripts/Makefile.libMasahiro Yamada2014-06-05-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Because cmd_mkimage is used in various subdirectories, it seems reasonable to define it in scripts/Makefile.lib. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | | openrisc: fix relocation codeFranck Jullien2014-06-05-14/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The relocation code can now relocate from anywhere to the RAM. The old code assumed that the binary was copied to the RAM by some PBL and then it just relocated the .text section from the loaded address to the linked address. Now, it first checks if vectors are somewhere else than the linked address. If yes, there are copied to address 0 (or to the exception vector base address if register EVBAR is present). Then, the .text section is relocated from its current location to the RAM. Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
* | | | openrisc: update SPR registers definitionFranck Jullien2014-06-05-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The OpenRISC architecture specification v1.0 defines new SPR registers. This patch adds registers definition for group 0 and update bit definitions for the CPU configuration register. Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
* | | | arm: fdt_control: fix a build error with CONFIG_OF_EMBED=yMasahiro Yamada2014-06-05-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The build fails if a non-generic ARM board is compiled with CONFIG_OF_EMBED=y. The correct symbol name for embedded FDT is not __dtb_db_begin, but __dtb_dt_begin. (A typo introduced by commit 6ab6b2af) Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | | ARC: enable CONFIG_SYS_BOOT_RAMDISK_HIGHAlexey Brodkin2014-06-03-0/+1
|/ / / | | | | | | | | | | | | | | | | | | This enables relocation of initrd to the end of available DDR before Linux kernel start-up as it is done in other architectures. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | | powerpc: hiddendragon: remove orphan boardMasahiro Yamada2014-05-30-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This board has been orphan for a while. (Emails to its maintainer have been bouncing.) Because MPC82xx family is old enough, nobody would pick up the maintainership on it. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denx <wd@denx.de>
* | | powerpc: mpc8260ads: remove orphan boardMasahiro Yamada2014-05-30-15/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This board has been orphan for a while. (Emails to its maintainer have been bouncing.) Because MPC82xx family is old enough, nobody would pick up the maintainership on it. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denx <wd@denx.de>
* | | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-05-30-5/+2331
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| * | ARM: at91sam9m10g45ek: enable mci0 supportWu, Josh2014-05-27-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Also we enable the mmc command in configuration file. As both CONFIG_CMD_MMC and CONFIG_CMD_USB use the CONFIG_DOS_PARTITION, so remove the redundant CONFIG_DOS_PARTITION definition. Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | ARM: at91sam9x5: define the AT91FAMILY and ARM926EJS in SoC headerWu, Josh2014-05-27-0/+3
| | | | | | | | | | | | | | | Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | ARM: at91: remove AT91X40 macro since it is not use any moreWu, Josh2014-05-27-2/+0
| | | | | | | | | | | | | | | | | | | | | The at91x40.h is not exist. So we remove it. Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | arm:at91: enable ROM loadable atmel imageAndreas Bießmann2014-05-27-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | For sama5d3xek we need to modify the SPL image for correct detection by ROM code. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Tested-by: Bo Shen <voice.shen@atmel.com>
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