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* split AU1X00 specific code from cmd_ide.cPavel Herrmann2012-10-17-1/+33
| | | | | | move special case of ide_swap_read() for AU1X00 SoC into SoC-specific directory. Signed-off-by: Pavel Herrmann <morpheus.ibis@gmail.com>
* split mpc8xx hooks from cmd_ide.cPavel Herrmann2012-10-17-0/+233
| | | | | | | | | | | | | move most of mpc8xx hooks from cmd_ide.c into ide_preinit() and newly created ide_init_postreset() (invoked after calling ide_reset after ide_preinit), some cleanup to make checkpatch happy, enable IDE init hooks in configs of affected boards. confusingly, these hooks are used by more than just mpc8xx-based boards, and therefore are placed in arch/ppc/lib/ note: checkpatch still emits warnings about using volatile Signed-off-by: Pavel Herrmann <morpheus.ibis@gmail.com>
* serial: Use default_serial_puts() in driversMarek Vasut2012-10-17-80/+10
| | | | | | | | | | Replace the in-place ad-hoc implementation of serial_puts() within the drivers with default_serial_puts() call. This cuts down on the code duplication quite a bit. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tom Rini <trini@ti.com>
* mpc82xx: Remove BMW board portStefan Roese2012-10-17-9/+4
| | | | | | | | | | | As the board seems to be unmaintained for some time, lets remove the support in mainline completely. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: James F. Dougherty <jfd@broadcom.com> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Marek Vasut <marex@denx.de>
* nds32: Change macro from BOARD_LATE_INIT to CONFIG_BOARD_LATE_INITNobuhiro Iwamatsu2012-10-17-1/+1
| | | | | | | | | | | With almost all the architecture and board BOARD_LATE_INIT does not use. CONFIG_BOARD_LATE_INIT is used instead. This changed CONFIG_BOARD_LATE_INIT from BOARD_LATE_INIT. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> CC: Macpaul Lin <macpaul@andestech.com> [trini: Fixup for context changes] Signed-off-by: Tom Rini <trini@ti.com>
* Merge branch 'agust@denx.de-next' of git://git.denx.de/u-boot-stagingTom Rini2012-10-15-0/+3
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| * bootstage: Store boot timings in device treeSimon Glass2012-10-02-0/+3
| | | | | | | | | | | | | | | | Add an option, CONFIG_BOOTSTAGE_FDT to pass boot timings to the kernel in the device tree, if available. To use this, you must have CONFIG_OF_LIBFDT defined. Signed-off-by: Simon Glass <sjg@chromium.org>
* | mx25: Clean up lowlevel_initBenoît Thébaudeau2012-10-15-22/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clean up mx25 lowlevel_init: - Add comments. - Do not use write32 repeatedly with the same value in order not to increase code size. - Make register values configurable. - Use macro parameters with default values instead of literal constants. - Use defined macros instead of duplicating code. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: John Rigby <jcrigby@gmail.com> Cc: Matthias Weisser <weisserm@arcor.de>
* | mx31: Fix PDR0_CSI_PODFBenoît Thébaudeau2012-10-15-2/+4
| | | | | | | | | | | | | | | | | | | | The CSI PODF bit-field used by the previous code for the i.MX31 CCM PDR0 register is actually composed of two bit-fields: one pre-divider and one post-divider. This patch fixes the CCM access macros and the code using them accordingly. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx35: Define MAX and AIPS registersBenoît Thébaudeau2012-10-15-1/+84
| | | | | | | | | | Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx31: Add more CCM access macrosBenoît Thébaudeau2012-10-15-0/+10
| | | | | | | | | | Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx5: Optimize lowlevel_init code sizeBenoît Thébaudeau2012-10-15-53/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Optimize mx5 lowlevel_init.S code size: - Compute values at compile time rather than at runtime where possible. - Assign r4 to hold the zero value rather than setting registers to 0 again and again. - Associate a function to setup_pll rather than expanding its large macro code multiple times. - Allocate constant values in section only if used. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Tested-by: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* | mx25: Fix eSDHC supportBenoît Thébaudeau2012-10-15-9/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MMC driver appropriate for the i.MX25 is fsl_esdhc, which has nothing to do with mxcmmc. Also, each eSDHC instance has a dedicated clock, so gd->sdhc_clk must be set accordingly. This is good for the case only a single SDHC instance is used (initialization made with fsl_esdhc_mmc_init()). A future patch will fix the multi-instance use case (initialization made directly with fsl_esdhc_initialize()). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Eric Bénard <eric@eukrea.com> Cc: Otavio Salvador <otavio@ossystems.com.br>
* | mx25: Define cpu_eth_init() only if neededBenoît Thébaudeau2012-10-15-4/+6
| | | | | | | | | | | | | | | | The FEC is the only SoC Ethernet support available on i.MX25, so define cpu_eth_init() only for it instead of returning a misleading success code. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx25: Clean up clocks APIBenoît Thébaudeau2012-10-15-9/+6
| | | | | | | | | | | | | | | | Use the standard mxc_get_clock() instead of exporting internal functions and using literal constant values. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx25 clocks: Fix MXC_FEC_CLKBenoît Thébaudeau2012-10-15-3/+2
| | | | | | | | | | | | | | | | | | | | mxc_get_clock(MXC_FEC_CLK) should return the IPG clock, not the AHB clock. Also, imx_get_fecclk() was correct but reimplemented the calculation of the IPG clock, so remove the duplicated code. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx25: Define more standard clocksBenoît Thébaudeau2012-10-15-0/+15
| | | | | | | | | | | | | | Define AHB, IPG and CSPI clocks. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx25: Clean up clock calculationsBenoît Thébaudeau2012-10-15-4/+4
| | | | | | | | | | | | | | | | Avoid possible overflow in clock calculations, and do not waste calls to lldiv() to divide simple ulongs. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx25: Fix decode_pllBenoît Thébaudeau2012-10-15-3/+6
| | | | | | | | | | | | | | | | The MFN bit-field of the PLL registers represents a signed value. See the reference manual. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx5/6 clocks: Fix SDHC clocksBenoît Thébaudeau2012-10-15-1/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i.MX5 eSDHC clocks were considered as coming from the IPG clock although they have dedicated clock paths. Also, on i.MX5/6, each SDHC instance has a dedicated clock, so gd->sdhc_clk must be set accordingly. This is good for the case only a single SDHC instance is used (initialization made with fsl_esdhc_mmc_init()). A future patch will fix the multi-instance use case (initialization made directly with fsl_esdhc_initialize()). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Eric Bénard <eric@eukrea.com> Cc: Otavio Salvador <otavio@ossystems.com.br>
* | mx51: Fix I2C clock ID checkBenoît Thébaudeau2012-10-15-1/+5
| | | | | | | | | | | | | | There are only 2 I²C instances on i.MX51, but 3 on i.MX53. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx5 clocks: Fix MXC_FEC_CLKBenoît Thébaudeau2012-10-15-3/+2
| | | | | | | | | | | | | | | | | | The FEC clock does not come from PLL1, but from the IPG clock. The previous code was even inconsistent with itself, returning the IPG clock as expected for imx_get_fecclk(), but the PLL1 clock for mxc_get_clock(MXC_FEC_CLK). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx5 clocks: Simplify imx_get_cspiclk()Benoît Thébaudeau2012-10-15-20/+3
| | | | | | | | | | | | | | | | | | The code handling the dividers was duplicated for each possible input clock, and this function can benefit from the newly introduced get_standard_pll_sel_clk() function instead of duplicating this mux handling code. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx5 clocks: Fix get_uart_clk()Benoît Thébaudeau2012-10-15-12/+24
| | | | | | | | | | | | | | | | | | | | | | | | This function returned 66500000 instead of the correct lp_apm clock frequency if the CCM.CSCMR1.uart_clk_sel mux is set to 3. This patch fixes this issue by introducing the get_standard_pll_sel_clk() function that will be used by future patches to handle identical muxes used by many other clocks. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx5 clocks: Fix get_ipg_per_clk()Benoît Thébaudeau2012-10-15-3/+7
| | | | | | | | | | | | | | | | | | | | | | This fixes the "IPG PERCLK" frequency printed by the clocks command. The issue was that get_ipg_per_clk() used periph_clk instead of lp_apm in the case CCM.CBCMR.perclk_lp_apm_sel is set. It also fixes I²C support. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx5 clocks: Fix get_periph_clk()Benoît Thébaudeau2012-10-15-20/+22
| | | | | | | | | | | | | | | | | | | | In the case periph_clk comes from periph_apm_clk, the latter is selected by the CCM.CBCMR.periph_apm_sel mux, which can source the lp_apm clock from its input ♯2. get_periph_clk() returned 0 instead of the lp_apm clock frequency in this case. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx5 clocks: Fix get_lp_apm()Benoît Thébaudeau2012-10-15-1/+38
| | | | | | | | | | | | | | | | | | | | | | | | If CCM.CCSR.lp_apm is set, the lp_apm clock is not necessarily 32768 Hz x 1024. In that case: - on i.MX51, this clock comes from the output of the FPM, - on i.MX53, this clock comes from the output of PLL4. This patch fixes the code accordingly. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx5 clocks: Add and use CCSR definitionsBenoît Thébaudeau2012-10-15-11/+46
| | | | | | | | | | | | | | This fixes config_pll_clk(), which used 0x20 instead of 0x200 for PLL4_CLOCK. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx51: Fix USB PHY clocksBenoît Thébaudeau2012-10-15-8/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i.MX51 has a single USB PHY clock, while the i.MX53 has two. These 3 clocks have different clock gate control bit-fields. The existing code was correct only for i.MX53, so this patch fixes the i.MX51 use case. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Jana Rapava <fermata7@gmail.com> Cc: Wolfgang Grandegger <wg@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il>
* | mx5: Fix clock gate valuesBenoît Thébaudeau2012-10-15-12/+18
| | | | | | | | | | | | | | | | | | The clock gate values are 2-bit bit-fields. Hence, setting or clearing only one of these bits like what was done is wrong and can lead to unpredictable behavior depending on the original value of these bit-fields. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx5: Use explicit clock gate namesBenoît Thébaudeau2012-10-15-11/+283
| | | | | | | | | | | | | | | | Use clock gate definitions having names showing clearly the gated clock instead of names giving only a register field index. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx5 clocks: CleanupBenoît Thébaudeau2012-10-15-152/+184
| | | | | | | | | | | | | | | | | | | | Clean up the i.MX5 clock driver: - Use readl() and writel() instead of their __raw_ counterparts. - Use the clr/setbits_le32() family of macros rather than expanding code. - Use accessor macros for bit-fields instead of _MASK and _OFFSET. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx5/6: Define default SoC input clock frequenciesBenoît Thébaudeau2012-10-15-42/+63
| | | | | | | | | | | | | | | | | | | | | | Define default SoC input clock frequencies for i.MX5/6 in order to get rid of duplicated definitions. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Jason Liu <r64343@freescale.com> Cc: Matt Sealey <matt@genesi-usa.com> Cc: Fabio Estevam <fabio.estevam@freescale.com>
* | imx: Use MXC_I2C_CLK in imx i2c driverMatthias Weisser2012-10-15-0/+8
| | | | | | | | | | | | | | | | i2c didn't work on imx25 due to missing MXC_IPG_PERCLK. Now using MXC_I2C_CLK on all imx systems using i2c. Signed-off-by: Matthias Weisser <weisserm@arcor.de> Acked-by: Stefano Babic <sbabic@denx.de>
* | mx25: add CPU revision 1.2Eric Benard2012-10-15-0/+4
| | | | | | | | | | | | | | | | tested on a MCIMX257CJM4A which now reports : CPU: Freescale i.MX25 rev1.2 at 399 MHz Signed-off-by: Eric Bénard <eric@eukrea.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
* | i.MX6: get rid of redundant struct src_regs (dupe of struct src)Eric Nelson2012-10-15-22/+1
| | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* | i.MX6: define struct iomuxc and IOMUX_GPR2 register bitfieldsEric Nelson2012-10-15-0/+73
| | | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | i.MX6: Add ANATOP_PFD_480 bitfield constantsEric Nelson2012-10-15-0/+24
| | | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | i.MX6: define IOMUX_GPR3 register bitfieldsEric Nelson2012-10-15-0/+48
| | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* | i.MX6: define bitfields for CHSCCDR registerEric Nelson2012-10-15-0/+4
| | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* | i.MX6: change register name for CCM_CHSCCDR to match ref. manualEric Nelson2012-10-15-1/+1
| | | | | | | | | | | | | | Register CCM_CHSCCDR (offset 0x34 in CCM) is named CCM_CHSCCDR in reference manual, but was named chscdr in struct mxc_ccm_reg. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* | i.MX6: provide functional names for CCM_CCGR0-CCGR6 bit fieldsEric Nelson2012-10-15-183/+185
| | | | | | | | | | | | | | | | | | | | | | | | | | Add meaningful constants for each clock channels and use them for enabling and disabling i.MX6 clocks. Includes an update to enable/disable the IPU1 clock in drivers/video/ipu_common to remove IMX5x register access when used on i.MX6 as discussed in V1: http://patchwork.ozlabs.org/patch/185129/ Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* | pxa: Add code to examine cpu model and revisionLukasz Dalek2012-10-15-2/+22
| | | | | | | | | | | | | | Add function which return CPU model and revision which can be used for cpu detection. Signed-off-by: Lukasz Dalek <luk0104@gmail.com>
* | tegra: nand: add board pinmuxLucas Stach2012-10-15-0/+1
| | | | | | | | | | | | | | | | Boards may require a different pinmux setup for NAND than the default one. Add a way to call into board specific code to set this up. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | tegra: clean up board include hellLucas Stach2012-10-15-27/+20
| | | | | | | | | | | | | | | | | | | | The prototypes used in board files were all scattered out, which lead to code duplication between SPL and normal U-Boot and some prototypes not actually being used. Consolidate this in a common board header. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | tegra: add funcmux entry for NAND attached to KBCLucas Stach2012-10-15-1/+19
| | | | | | | | | | | | | | | | Secondary config for the Flash attachment. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | tegra20: rework UART GPIO handlingLucas Stach2012-10-15-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename board provided gpio_config_uart() to gpio_early_init_uart() as it does the same thing as the equally called function provided by the uart-switch code. This allows to simply call this function in early board init whether or not we are building with CONFIG_UART_SWITCH defined. Also provide a weak symbol for this function, to avoid the need to provide this function for boards that don't need any fixup. This patch supersedes the earlier posted "tegra: convert gpio_config_uart to weak symbol". Build tested with MAKEALL -s tegra20 Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | tegra20: add clock_set_pllout functionLucas Stach2012-10-15-3/+67
| | | | | | | | | | | | | | | | | | | | | | Common practice on Tegra 2 boards is to use the pllp_out4 FO to generate the ULPI reference clock. For this to work we have to override the default hardware generated output divider. This function adds a clean way to do so. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | tegra20: complete periph_id enumLucas Stach2012-10-15-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Most Tegra boards output the ULPI reference clock on pad DEV2. Complete the periph_id enum so that we are able to enable this clock output circuit. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Tegra20: Move some include files to arch-tegra for sharing with Tegra30Tom Warren2012-10-15-467/+585
| | | | | | | | | | | | | | | | | | | | | | The move is pretty straight-forward. ap20.h and tegra20.h were renamed to ap.h and tegra.h. Some files remain in arch-tegra20 but 'include' a file in 'arch-tegra' with #defines & structs that will be common between T20 and T30 HW. HW-specific #defines, etc. stay in the 'arch-tegra20' 'root' file. All boards build OK w/MAKEALL -s tegra20. Checkpatch.pl runs clean. Seaboard works OK. Signed-off-by: Tom Warren <twarren@nvidia.com>
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