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* 83xx/pcie: fix build error for 83xx pcieRoy Zang2013-08-09-0/+2
| | | | | | | | | | | Fix the following build error caused by patch "powerpc/pcie: add PCIe version 3.x support": pcie.c:302:34: error: 'PCI_LTSSM' undeclared (first use in this function) pcie.c:303:15: error: 'PCI_LTSSM_L0' undeclared (first use in this function) Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/mpc8xxx: Fix TIMING_CFG_3[EXT_ACTTOPRE]James Yang2013-08-09-1/+1
| | | | | | | | The TIMING_CFG_3[EXT_ACTTOPRE] register field is 2 bits wide, but the mask omitted the LSB. This patch provides a 2-bit wide mask. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/85xx: Add C29x SoC supportMingkai Hu2013-08-09-0/+109
| | | | | | | | | | | | | | | The Freescale C29x family is a high performance crypto co-processor. It combines a single e500v2 core with necessary SEC engine. There're three SoC types(C291, C292, C293) with the following features: - 512K L2 Cache/SRAM and 512 KB platform SRAM - DDR3/DDR3L 32bit DDR controller - One PCI express (x1, x2, x4) Gen 2.0 Controller - Trust Architecture 2.0 - SEC6.0 engine Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Po Liu <Po.Liu@freescale.com>
* powerpc/pcie: remove PCIe version 3.x define for B4860 and B4420Zang Roy-R619112013-08-09-1/+0
| | | | | | B4860 and B4420 has PCIe version 2.4 IP instead of 3.x Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
* powerpc/pcie: add PCIe version 3.x supportZang Roy-R619112013-08-09-2/+34
| | | | | | | | | | | | | | | | | | | | | | | | | T4240 PCIe IP is version 3.0 and has some update comparing previous QorIQ products. 1. Move Freescale specific register define to arch/powerpc/include/asm/fsl_pci.h and update the register offset define for T4240. 2. add the status/control register define use status/control register to judge the link status 3. The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is RC or EP mode. This patch fixes the PCIe card link up issue on T4240QDS. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/rman: fix RMan support for t4240 and b4860Minghuan Lian2013-08-09-8/+8
| | | | | | | | | | | | 1. Add CONFIG_SYS_DPAA_RMAN macro to t4240 and b4860. 2. Decrease RMan liodn offset number. SET_RMAN_LIODN() is used to set liodn offset of RMan blocks 0-3. For t4240 and b4860, RMan liodn base is assigned to 922, the original offset number is too large that the liodn (base+offset 922+678 = 1600) is greater than 0x500 the maximum liodn number. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/asm: Move function declaration of 'serdes_get_prtcl' to fsl_serdes.hShaveta Leekha2013-08-09-1/+1
| | | | | | | It allows files not in the same path to use this function as required by B4 board file Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
* powerpc/mpc85xx: Add defines for serdes RSTCTL registerShaveta Leekha2013-08-09-1/+3
| | | | | | | | Also change the define name SRDS_RSTCTL_SDPD to SRDS_RSTCTL_SDEN, which stands for SerDes enable as mentioned in SerDes module guide Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
* board/bsc9132qds: Configure DSP DDR controllerPriyanka Jain2013-08-09-0/+6
| | | | | | | | | | | | | | BSC9132 SoC has two separate DDR controllers for PowerPC side and DSP side DDR. They are mapped to PowerPC and DSP CCSR space respectively. BSC9132QDS has two on-board MC34716EP DDR3 memory one connected to PowerPC and other to DSP side controller. Configure DSP DDR controller similar to PowerPC side DDR controller as memories are exactly similar. Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* board/bsc9132qds: Add DSP side tlb and lawsPriyanka Jain2013-08-09-1/+9
| | | | | | | | | | | | | | | BSC9132QDS is a Freescale Reference Design Board for BSC9132 SoC which is a integrated device that contains two powerpc e500v2 cores and two DSP starcores. To support DSP starcore -Creating LAW and TLB for DSP-CCSR space. -Creating LAW for DSP-core subsystem M2 and M3 memory -Creating LAW for 1GB DDR which is connected exclusively to DSP-cores Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* powerpc/srio-pcie-boot: Avoid the NOR_BOOT macro when boot from SRIO/PCIELiu Gang2013-08-09-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When a board (slave) boots from SRIO/PCIE, it would get the instructions from a remote board (master) by SRIO/PCIE interface, and the slave's u-boot image should be built with the SYS_TEXT_BASE=0xFFF80000; So the u-boot of the slave should avoid the NOR_BOOT branch at the booting stage. For example, when a P2041RDB boots from SRIO/PCIE, it will set TLB entry 15 from base address "CONFIG_SYS_MONITOR_BASE & 0xffc00000", and with the 4M size as the boot window in NOR_BOOT branch. Because the CONFIG_SYS_MONITOR_BASE = CONFIG_SYS_TEXT_BASE = 0xFFF80000, so the TLB entry will be from base address 0xffc00000 and with 4M size. Then the u-boot will set TLB entry 14 from base address "CONFIG_SYS_INIT_RAM_ADDR", and with the 16K size as the initial stack window. For the P2041RDB platform, the CONFIG_SYS_INIT_RAM_ADDR = 0xffd00000. So the TLB entry 14 and 15 will be in confliction. There will be right TLB entries configurations when avoid the NOR_BOOT branch and set the boot window from 0xfff00000 with 1M size space. Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
* powerpc/mpc85xx: Workaround for A-005812York Sun2013-08-09-0/+29
| | | | | | | | Erratum A-005812 Incorrect reservation clearing in Write Shadow mode can result in invalid atomic operations. For u-boot, this erratum only impacts SoCs running in write shadow mode. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/mpc8xxx: Add memory reset controlYork Sun2013-08-09-13/+102
| | | | | | | | | JEDEC spec requires the clocks to be stable before deasserting reset signal for RDIMMs. Clocks start when any chip select is enabled and clock control register is set. This patch also adds the interface to toggle memory reset signal if needed by the boards. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/mpc8xxx: Add x4 DDR device supportYork Sun2013-08-09-0/+13
| | | | | | | | | On selected platforms, x4 DDR devices can be supported. Using x4 devices may lower the performance, but generally they are available for higher density. Tested on MT36JSF2G72PZ-1G9E1 RDIMM. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/mpc8xxx: Set inactive csn_bnds to 0xffffffffYork Sun2013-08-09-3/+9
| | | | | | | | | | | | When chip select interleaving is enabled, cs0_bnds is used for address binding. Other csn_bnds are not used. When two controllers interleaving is enabled, cs0_bnds of both controllers are used, other csn_bnds are not. However, the unused csn_bnds may be used internally for calculating addresses for calibration. Setting those registers to 0 may confuse controllers in some cases. Instead, setting them to 0xffffffff together with normal LAWs will guarantee the address is not mapped to DDR. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/corenet: Move RCW print to cpu.cYork Sun2013-08-09-4/+19
| | | | | | | The RCW print is common for all corenet platforms. Not necessary to ducplicate in each board file. Signed-off-by: York Sun <yorksun@freescale.com>
* mpc85xx: Base emulator supportYork Sun2013-08-09-1/+19
| | | | | | | | | Prepare for emulator support for mpc85xx parts. Disable DDR training and skip wrlvl_cntl_2 and wrlvl_cntl_3 registers. These two registers improve stability but not supported by emulator. Add CONFIG_FSL_TBCLK_EXTRA_DIV for possible adjustment to time base. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/corenet: Move CONFIG_FSL_CORENET out of board header fileYork Sun2013-08-09-0/+5
| | | | | | | Move CONFIG_FSL_CORENET define to config_mpc85xx.h. It is not board specific feature and belongs to SoC header. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/t4: Correct LIODN assignment for SRIOLiu Gang2013-08-09-2/+3
| | | | | | | For T4 platform, the SRIO LIODN registers are in SRIO address space and not in GUTs. Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
* powerpc/b4860: Correct LIODN assignment for SRIOLiu Gang2013-08-09-2/+3
| | | | | | | For B4, the SRIO LIODN registers are in SRIO address space and not in GUTs. Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
* powerpc/srio: Update the SRIO LIODN registers and ID table macroLiu Gang2013-08-09-0/+23
| | | | | | | | | | | | For some PowerPC platforms, LIODN registers for SRIO ports are in SRIO register address space. So the ccsr_rio structure should be updated for those LIODN registers. In addition, add a new macro "SET_SRIO_LIODN_BASE" to create the SRIO LIODN ID table based on the SRIO LIODN register address. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* config: don't define CONFIG_ARCH_DEVICE_TREEStephen Warren2013-08-02-57/+0
| | | | | | | Now that nothing uses CONFIG_ARCH_DEVICE_TREE, stop defining it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* blackfin: Fix using gd->baudrate before setting its valueAxel Lin2013-07-31-2/+1
| | | | | | | | | | | | | | Current code uses gd->baudrate before setting its value. Besides, I got below build warning which is introduced by commit ddb5c5be "blackfin: add baudrate to bdinfo". board.c:235:3: warning: passing argument 1 of 'simple_strtoul' makes pointer from integer without a cast [enabled by default] include/vsprintf.h:27:7: note: expected 'const char *' but argument is of type 'unsigned int' This patch ensures we get the baudrate setting before using it. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
* blackfin: gpio: Use proper mask for comparing functionAxel Lin2013-07-31-5/+6
| | | | | | | | | | | The function return from P_FUNCT2MUX(per) takes 2 bits, however for BF537_FAMILY with offset != 1 the function is 1 bit. Also has small refactor for better readability. In portmux_setup(), it looks odd having "muxreg &= ~(3 << 1);" while in current code we do muxreg |= (function << offset);. Signed-off-by: Axel Lin <axel.lin@ingics.com>
* blackfin: gpio: Unreserve gpio in special_gpio_free()Axel Lin2013-07-31-2/+2
| | | | | | | In special_gpio_free(), call unreserve() rather than reserve() to release gpio. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
* Merge branch 'master' of git://git.denx.de/u-boot-nds32Tom Rini2013-07-25-23/+309
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| * nds32: Enable FPU if the version of CPU supportedken kuo2013-07-25-0/+52
| | | | | | | | | | | | | | | | | | Some version of Andes core support FPU coprocessor, if this is the case, and toolchain support FPU instruction set, we should enable it at low level initialization time. Signed-off-by: Kuan-Yu Kuo <ken.kuoky@gmail.com> Cc: Macpaul Lin <macpaul@gmail.com>
| * nds32: Update <asm/io.h> and <asm/setup.h> with SPDX license identifiersTom Rini2013-07-25-6/+2
| | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
| * nds32: Convert Makefiles to use COBJS-y styleken kuo2013-07-25-13/+16
| | | | | | | | | | Signed-off-by: Kuan-Yu Kuo <ken.kuoky@gmail.com> Cc: Macpaul Lin <macpaul@gmail.com>
| * nds32: ag101/ag102: Fix setting lastdec and now valuesAxel Lin2013-07-24-6/+8
| | | | | | | | | | | | | | | | | | | | The timer3 counter unit for lastdesc and now values are inconsistent in current code. The unit of "readl(&tmr->timer3_counter) / (CONFIG_SYS_CLK_FREQ / 2)" is second. However, CONFIG_SYS_HZ is defined as 1000 in board config file. This means the accuracy of "lastdec" and "now" should be in millisecond, thus fix the equation to set lastdec and now variables accordingly. Signed-off-by: Axel Lin <axel.lin@ingics.com>
| * nds32: Enable the function of passing parameters to Linuxken kuo2013-07-24-0/+192
| | | | | | | | | | | | | | | | | | Add a header file, setup.h, which copy from Linux source code, this file contain structures are used to pass initialisation parameters to Linux. Enable this function on adp-ag101/adp-ag101p target Signed-off-by: Kuan-Yu Kuo <ken.kuoky@gmail.com> Cc: Macpaul Lin <macpaul@gmail.com>
| * nds32: Enable two banks of SDRAM on Andes boardken kuo2013-07-24-1/+5
| | | | | | | | | | | | | | | | | | The original adp-ag101/adp-ag101p initialize only one bank(64MB) by default at boot time, but it is not enough for some application, so increasing to two banks(128M). Signed-off-by: Kuan-Yu Kuo <ken.kuoky@gmail.com> Cc: Macpaul Lin <macpaul@gmail.com>
| * nds32: introduce macros for bit manipulationGabor Juhos2013-07-24-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot does not compile for the adp-ag101 boards since commit f6c3b34697bf8bf05cb4e81c2fd3cadb9a98daea (mmc: update Faraday FTSDC010 for rw performance) The driver assumes that the bit manipulation macros are provided by all architectures. This is not the case for nds32 and it causes a build error like this: ftsdc010_mci.c: In function 'ftsdc010_clkset': ftsdc010_mci.c:118: warning: implicit declaration of function 'setbits_le32' ftsdc010_mci.c:123: warning: implicit declaration of function 'clrbits_le32' drivers/mmc/libmmc.o: In function `ftsdc010_request': /devel/u-boot.git/drivers/mmc/ftsdc010_mci.c:234: undefined reference to `setbits_le32' /devel/u-boot.git/drivers/mmc/ftsdc010_mci.c:243: undefined reference to `clrbits_le32' /devel/u-boot.git/drivers/mmc/ftsdc010_mci.c:234: undefined reference to `clrbits_le32' drivers/mmc/libmmc.o: In function `ftsdc010_clkset': /devel/u-boot.git/drivers/mmc/ftsdc010_mci.c:118: undefined reference to `clrbits_le32' /devel/u-boot.git/drivers/mmc/ftsdc010_mci.c:118: undefined reference to `clrbits_le32' /devel/u-boot.git/drivers/mmc/ftsdc010_mci.c:121: undefined reference to `setbits_le32' /devel/u-boot.git/drivers/mmc/ftsdc010_mci.c:123: undefined reference to `setbits_le32' /devel/u-boot.git/drivers/mmc/ftsdc010_mci.c:123: undefined reference to `setbits_le32' The patch adds bit manipulation macros for the nds32 architecture to avoid the errors. The macros are copied from the ARM implementation. Compile tested only. Cc: Kuo-Jung Su <dantesu@faraday-tech.com> Cc: Macpaul Lin <macpaul@andestech.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2013-07-25-45/+76
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflict over SPDX changes means that one change was effectively dropped as it was fixing typos in a removed hunk of text. Conflicts: arch/mips/cpu/mips64/start.S Signed-off-by: Tom Rini <trini@ti.com>
| * | MIPS: mips32/cache.S: use v1 register for indirect function callsGabor Juhos2013-07-24-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Synchronize the code with mips64/cache.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * | MIPS: mips32/cache.S: store cache line size in t8 registerGabor Juhos2013-07-24-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Synchronize the code with mips64/cache.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * | MIPS: mips32/cache.S: save return address in t9 registerGabor Juhos2013-07-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Synchronize the code with mips64/cache.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * | MIPS: xburst/start.S: rework relocation info checkGabor Juhos2013-07-24-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Make it similar to the code in mips{32,64}/start.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * | MIPS: xburst/start.S: use t8 register for dynamic relocationGabor Juhos2013-07-24-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | Synchronize the code with mips{32,64}/start.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * | MIPS: xburst/start.S: save gd in s0 registerGabor Juhos2013-07-24-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Synchronize the code with mips{32,64}/start.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * | MIPS: xburst/start.S: save relocation offset in s1 registerGabor Juhos2013-07-24-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | Synchronize the code with mips{32,64}/start.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * | MIPS: xburst/start.S: save relocation address in s2 registerGabor Juhos2013-07-24-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | Synchronize the code with mips{32,64}/start.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * | MIPS: mips32/start.S: rework relocation info checkGabor Juhos2013-07-24-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Make it similar to the code in mips64/start.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * | MIPS: mips32/start.S: use t8 register for dynamic relocationGabor Juhos2013-07-24-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | Synchronize the code with mips64/start.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * | MIPS: mips32/cache.S: remove superfluous register assignmentGabor Juhos2013-07-24-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The t4 register already holds the cache line size, and the value of the register is not changed in mips_init_icache. Get the cache line size value from t4 for mips_init_dcache as well and remove the superfluous assignment of t5 register. Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
| * | MIPS: mips64/interrupt.c: remove superfluous includeGabor Juhos2013-07-24-1/+0
| | | | | | | | | | | | | | | | | | | | | Nothing is used from asm/mipsregs.h. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * | MIPS: mips32/time.c: fix checkpatch errors/warningsGabor Juhos2013-07-24-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Checking mips32/time.c with checkpatch.pl shows this: arch/mips/cpu/mips32/time.c:30: WARNING: line over 80 characters arch/mips/cpu/mips32/time.c:57: ERROR: return is not a function, parentheses are not required total: 1 errors, 1 warnings, 0 checks, 85 lines checked Fix the code to make checkpatch.pl happy. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * | MIPS: qemu-malta: setup GT64120 registers as done by YAMONGabor Juhos2013-07-24-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the GT64120 register base to 0x1be00000 and setup PCI BAR registers as done by the original YAMON bootloader. This is needed for running Linux kernel. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * | MIPS: qemu-malta: enable flash supportGabor Juhos2013-07-24-0/+2
| | | | | | | | | | | | | | | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * | MIPS: qemu-malta: add reset supportGabor Juhos2013-07-24-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MIPS Malta board has a SOFTRES register. Writing a magic value into that register initiates a board reset. Use this feature to implement reset support. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
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