| Commit message (Collapse) | Author | Age | Lines |
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The POWER_DCLIMITS_NEGLIMIT_OFFSET bit in mx28 power supply block is
not called POWER_DCLIMITS_NETLIMIT_OFFSET, but POWER_DCLIMITS_NEGLIMIT_OFFSET.
Correct the name in the header file.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
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The POWER_MINPWR_VBG_OFF bit in mx28 power supply block is not called
POWER_MINPWR_FBG_OFF, but POWER_MINPWR_VBG_OFF. Correct the name in the
header file.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
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The mx5 lowlevel_init.S contains board-specific code based on the reference
design. Let's keep it since it avoids creating new lowlevel_init files and it
may be used by many boards. But add a config to make it optional in order not to
cause issues on boards not following this part of the reference design.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matt Sealey <matt@genesi-usa.com>
Acked-by: Stefano Babic <sbabic@denx.de>
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If a board does not enable CSPI, there is no need to show the CSPI clock
frequency as part of the 'clock' command.
Reported-by: Dirk Behme <dirk.behme@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Dirk Behme <dirk.behme@gmail.com>
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Print CSPI clock in 'clock' command.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
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Align SPI chip select naming with i.MX53 reference manual.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
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Some MXC SoCs like the i.MX35 have hosts located at unusual offsets, so prepare
to the introduction of i.MX35 support by defining the ehci-mxc hosts offsets at
SoC level.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
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The EHCI definitions in i.MX31's imx-regs.h are MXC-generic, so move them to
ehci-fsl.h so that all MXC SoCs can use them.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
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Add support for adjusting the L1 cache behavior by updating the MMU
configuration. The mmu_set_region_dcache_behaviour() function allows
drivers to make these changes after the MMU is set up.
It is implemented only for ARMv7 at present.
This is needed for LCD support, where we want to make the LCD frame buffer
write-through (or off) rather than write-back.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Add support for the LCD peripheral at the Tegra2 SOC level. A separate
LCD driver will use this functionality to configure the display.
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Mayuresh Kulkarni:
- changes to remove bitfields and clean up for submission
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass:
- simplify code, move clock control into here, clean-up
Signed-off-by: Tom Warren <twarren@nvidia.com>
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The pulse width/frequency modulation peripheral supports generating
a repeating pulse. It is useful for controlling LCD brightness.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Add LCD definitions and also a proposed binding for LCD displays.
The PWM is as per what will likely be committed to linux-next soon.
The displaymode binding comes from a proposal here:
http://lists.freedesktop.org/archives/dri-devel/2012-July/024875.html
The panel binding is new, and fills a need to specify the panel
timings and other tegra-specific information. Should a binding appear
that allows the pwm to handle this automatically, we can revisit
this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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This binding will apparently soon be in linux-next. Bring it in now
since we need to do something, and may as well try to target what
Linux will have.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Add support for a default pin mapping for display1.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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These two functions don't actually modify their arguments so add a const
keyword.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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This patch adds SPI driver for EXYNOS.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: jy0922.shim@samsung.com
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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Add base address definition for SPI device on Exynos.
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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Add api to calculate and set the clock for SPI channels
Signed-off-by: James Miller <jamesmiller@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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This patch adds pinmux support for SPI channels
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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This patch adds clock support for I2S
Signed-off-by: R. Chandrasekar <rcsekar@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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This patch adds base address for I2S
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Chander Kashyap <chander.kashyap@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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This patch adds pinmux support for I2S1
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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This patch adds the audio parameters required by the I2S to play the
predefined audio data.
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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This patch add I2S registers
Signed-off-by: R. Chandrasekar <rcsekar@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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arch_cpu_init() is removed from cpu level to SOC level for arm1176
in commit 4ea6d6b,the same is done for s3c64xx
Signed-off-by: Ashok Kumar Reddy <ashokkourla2000@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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Signed-off-by: Marek Vasut <marex@denx.de>
Cc: David Müller <d.mueller@elsoft.ch>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: U-Boot DM <u-boot-dm@lists.denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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Moved the common code to calculate pll clock rate to new function
exynos_get_pll_clk().
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
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Based upon single SoC there can be multiple variants.
This patch add support to match the complete product ID.
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
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This patch add pinmux settings for Exynos4 for mmc0 and mmc2
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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Now proper GPIO parts numbering is handled at Samsung devices.
This fix is necessary for code using GPIO located at other banks
than first.
Test HW:
- Exynos4210 - Trats
- S5PC110 - goni
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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enable_caches() did not enable icache if CONFIG_SYS_ICACHE_OFF was not defined
but CONFIG_SYS_DCACHE_OFF was.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
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Only the values used in the sabrelite board are
added currently. Add more as other boards use them.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
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Read memory setup registers to determine size
of available ram. This routine works for mx53/mx6x
I need this because when mx6solo called get_ram_size
with a too large maximum size, the system hanged.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
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Previously, the same value was returned for both mx6dl and mx6solo.
Check number of processors to differeniate.
Also, a freescale patch says that sololite has its cpu/rev
stored at 0x280 instead of 0x260.
I don't have a sololite to verify.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
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Microblaze platform can use CONFIG_OF_EMBED option
but also it is necessary to support boards
which don't want to use this option.
U-Boot doesn't compile dts/libdts.o for #undef CONFIG_OF_EMBED
case that's why it should be guarded by ifdef.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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The patch
"include/linux/byteorder: import latest endian definitions from linux"
(sha1: eef1cf2d5cf1cae5fb76713e912263dedf110aeb)
Introduced a lot of compilation failures with unknow types.
include/linux/byteorder/big_endian.h:45:1: error: unknown type name '__le64'
include/linux/byteorder/big_endian.h: In function '__cpu_to_le64p':
include/linux/byteorder/big_endian.h:47:18: error: '__le64' undeclared (first use in this function)
include/linux/byteorder/big_endian.h:47:18: note: each undeclared identifier is reported only once for each function it appears in
include/linux/byteorder/big_endian.h:47:25: error: expected ';' before '__swab64p'
include/linux/byteorder/big_endian.h: At top level:
include/linux/byteorder/big_endian.h:49:1: error: unknown type name '__le64'
include/linux/byteorder/big_endian.h:53:1: error: unknown type name '__le32'
include/linux/byteorder/big_endian.h: In function '__cpu_to_le32p':
include/linux/byteorder/big_endian.h:55:18: error: '__le32' undeclared (first use in this function)
include/linux/byteorder/big_endian.h:55:25: error: expected ';' before '__swab32p'
include/linux/byteorder/big_endian.h: At top level:
include/linux/byteorder/big_endian.h:57:1: error: unknown type name '__le32'
include/linux/byteorder/big_endian.h:61:1: error: unknown type name '__le16'
...
Removing asm/bitops.h solved this problem.
Signed-off-by: Michal Simek <monstr@monstr.eu>
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Flushing caches is necessary because of soft reset
which doesn't clear caches.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Reviewed-by: Marek Vasut <marex@denx.de>
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Just remove ancient code.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Stephan Linz <linz@li-pro.net>
Reviewed-by: Marek Vasut <marex@denx.de>
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ext2_find_next_zero_bit must be also static if __swab32 is also static.
Warning:
include/asm/bitops.h:369:22: warning: '__fswab32' is static but
used in inline function 'ext2_find_next_zero_bit'
which is not static [enabled by default]
Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Stephan Linz <linz@li-pro.net>
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Remove unused header
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
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Timer is initialized already in board_init_r function in
(common/spl/spl.c) No need to initialize it again
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
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When CONFIG_SYS_L2CACHE_OFF is defined we end up with a few warnings
currently. Re-order functions so that we don't have that anymore.
Signed-off-by: Tom Rini <trini@ti.com>
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Board can implement function setup_board_tags which is used for adding atags
Signed-off-by: Pali Rohár <pali.rohar@gmail.com>
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If configured to use UART{1,2,3,4,5} such as on the Beaglebone RS232
cape or the am335x_evm daughterboard, enable the required clocks for
the UART in use.
Signed-off-by: Andrew Bradford <andrew@bradfordembedded.com>
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Add back common.h header that was removed in previous patch so that
CONFIG_TEGRA can be evaluated correctly.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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