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* exynos: update tzpc to make it common for exynos4 and exynos5Inderpal Singh2013-06-04-18/+25
| | | | | | | | | | This requires that cpu_is_exynos4/5 should be made available before tzpc_init. Hence this patch also makes necessary changes to have cpu_info in spl and invokes arch_cpu_init before tzpc_init in low_level_init.S for smdk5250. Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org> Acked-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* exynos: move tzpc_init to armv7/exynosInderpal Singh2013-06-04-1/+77
| | | | | | | | | | | tzpc_init is common for all exynos5 boards, hence move it to armv7/exynos so that all other boards can use it. Also update the smdk5250 Makefile and config file. Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org> Acked-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos5: clock: Update the equation to calculate PLL output frequencyAkshay Saraswat2013-05-21-4/+2
| | | | | | | | | | | | | | According to the latest exynos5 user manual, the equation for calculating PLL output was changed to FOUT= MDIV x FIN/(PDIV x 2^SDIV) earlier it was FOUT= MDIV x FIN/(PDIV x 2^(SDIV -1)) So updating the clock code accordingly. Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* arm: at91: enable mci support for at91sam9g20ek.Wu, Josh2013-05-12-0/+4
| | | | | Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* arm: at91: add at91sam9n12ek board supportWu, Josh2013-05-12-2/+181
| | | | | | | | | | | | Add support for following features: - nand boot, with PMECC 2bit ECC for 512 bytes sector - SPI flash boot - SD card boot - LCD support Signed-off-by: Josh Wu <josh.wu@atmel.com> [fix -Wimplicit-function-declaration for at91_lcd_hw_init()] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* arm: at91: add at91sam9n12 register definitionWu, Josh2013-05-12-8/+32
| | | | | | | | Since at91sam9n12 is a subset of at91sam9x5, so put all at91sam9n12 definitions in at91sam9x5 head file. Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2013-05-11-206/+371
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| * ARM: OMAP: Add arch_cpu_init functionSRICHARAN R2013-05-10-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | The boot parameters passed from SPL to UBOOT must be saved as a part of uboot's gd data as early as possible, before we will inadvertently overwrite it. So adding a arch_cpu_init for the required Socs to save it. Signed-off-by: Sricharan R <r.sricharan@ti.com> [trini: Add igep0033 hunk] Signed-off-by: Tom Rini <trini@ti.com>
| * ARM: OMAP: Cleanup boot parameters usageSRICHARAN R2013-05-10-83/+32
| | | | | | | | | | | | | | | | | | | | | | The boot parameters are read from individual variables assigned for each of them. This been corrected and now they are stored as a part of the global data 'gd' structure. So read them from 'gd' instead. Signed-off-by: Sricharan R <r.sricharan@ti.com> [trini: Add igep0033 hunk] Signed-off-by: Tom Rini <trini@ti.com>
| * ARM: OMAP: Correct save_boot_params and replace with 'C' functionSRICHARAN R2013-05-10-7/+56
| | | | | | | | | | | | | | | | | | | | | | Currently save_boot_params saves the boot parameters passed from romcode. But this is not stored in a writable location consistently. So the current code would not work for a 'XIP' boot. Change this by saving the boot parameters in 'gd' which is always writable. Also add a 'C' function instead of an assembly code that is more readable. Signed-off-by: Sricharan R <r.sricharan@ti.com>
| * ARM: OMAP4/5: Make OMAPx_SRAM_SCRATCH_ defines commonSRICHARAN R2013-05-10-33/+24
| | | | | | | | | | | | | | | | These defines are same across OMAP4/5. So move them to omap_common.h. This is required for the patches that follow. Signed-off-by: Sricharan R <r.sricharan@ti.com>
| * ARM: OMAP: Make omap_boot_parameters common across socsSRICHARAN R2013-05-10-72/+49
| | | | | | | | | | | | | | | | omap_boot_parameters is same and defined for each soc. So move this to a common place to reuse it across socs. Signed-off-by: Sricharan R <r.sricharan@ti.com>
| * am33xx: Fix warning with CONFIG_DISPLAY_CPUINFOTom Rini2013-05-10-5/+1
| | | | | | | | | | | | | | | | The arm_freq and ddr_freq variables are unused, so remove. Fixup whitespace slightly while in here. Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Tom Rini <trini@ti.com>
| * davinci: handle CONFIG_SYS_CLE_MASK and CONFIG_SYS_ALE_MASKEric Benard2013-05-10-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | these variables are curently defined in several config files but the driver doesn't use them and defaults to hardcoded values in nand_defs.h It's interesting to be able to change this hardcoded valude when the hardware is not using the default adress signals to drive ALE and CLE and two configuration defines already exist for this purpose so use them. Signed-off-by: Eric Bénard <eric@eukrea.com>
| * da850: provide davinci_enable_uart0Eric Benard2013-05-10-0/+10
| | | | | | | | | | | | | | | | this is needed to bring UART0 out of reset but this function currently only exists for dm644x/355/365/646x when da850 (at least am1808 also need it). Signed-off-by: Eric Bénard <eric@eukrea.com>
| * ARM: OMAP5: Fix warm reset with USB cable connectedLokesh Vutla2013-05-10-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Warm reset on OMAP5 freezes when USB cable is connected. Fix requires PRM_RSTTIME.RSTTIME1 to be programmed with the time for which reset should be held low for the voltages and the oscillator to reach stable state. There are 3 parameters to be considered for calculating the time, which are mostly board and PMIC dependent. -1- Time taken by the Oscillator to shut + restart -2- PMIC OTP times -3- Voltage rail ramp times, which inturn depends on the PMIC slew rate and value of the voltage ramp needed. In order to keep the code in u-boot simple, have a way for boards to specify a pre computed time directly using the 'CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC' option. If boards fail to specify the time, use a default as specified by 'CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC' instead. Using the default value translates into some ~22ms and should work in all cases. However in order to avoid this large delay hiding other bugs, its recommended that all boards look at their respective data sheets and specify a pre computed and optimal value using 'CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC' In order to help future board additions to compute this config option value, add a README at doc/README.omap-reset-time which explains how to compute the value. Also update the toplevel README with the additional option and pointers to doc/README.omap-reset-time. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> [rnayak@ti.com: Updated changelog and added the README] Signed-off-by: Rajendra Nayak <rnayak@ti.com>
| * OMAP5: USB: hsusbtll_clkctrl has to be in hw_auto for USB to workLubomir Popov2013-05-10-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | USB TLL clocks do not support 'explicit_en', only 'hw_auto' control (R. Sricharan). cm_l3init_hsusbtll_clkctrl has to be moved to the clk_modules_hw_auto_essential[] array in order to make the clock work. This fix is needed (but not sufficient) for USB EHCI operation in U-Boot. Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
| * Add DDR3 support for IGEP COM AQUILA/CYGNUS.Enric Balletbo i Serra2013-05-10-0/+17
| | | | | | | | | | | | These boards uses Samsung K4B2G1646E-BIH9 a 2Gb E-die DDR3 SDRAM. Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
| * arm: omap: emif: Fix DDR3 init after warm resetLokesh Vutla2013-05-10-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EMIF supports a global warm reset mode, during which the EMIF keeps the SDRAM content. But if leveling is enabled at the time of warm reset for DDR3, the following steps needs to be done after warm reset: 1) Keep EMIF in self refresh mode. 2) Reset PHY to bring back the PHY to a known state. 3) Start Levelling procedure. Doing the same. And also enabling DLL lock and code output after warm reset. Tested on OMAP5432 ES2.0 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * OMAP5: I2C: Set I2C_BUS_MAX to 5 to enable I2C4 and I2C5Lubomir Popov2013-05-10-1/+1
| | | | | | | | | | | | | | | | | | | | | | I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms. In order to be able to select one of these buses however, I2C_BUS_MAX has to be set to 5; do this here. Please note that for working bus selection, a fix to the i2c driver is required as well (subject of a separate patch). Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
| * OMAP5: I2C: Add I2C4 and I2C5 basesLubomir Popov2013-05-10-0/+2
| | | | | | | | | | | | | | | | I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms. The I2C4 and I2C5 base addresses were however not defined; do this here. Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
| * OMAP5: I2C: Enable i2c5 clocksLubomir Popov2013-05-10-0/+1
| | | | | | | | | | | | | | I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms. The i2c5 clock was however not enabled; do this here. Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
| * am33xx: add pll and clock support for TI814x CPSWMatt Porter2013-05-10-2/+102
| | | | | | | | | | | | | | Enables required PLLs and clocks for CPSW on TI814x. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-05-11-3255/+4055
|\ \ | | | | | | | | | | | | | | | Conflicts: drivers/mtd/nand/mxc_nand_spl.c include/configs/m28evk.h
| * | arm: mxs: Add LCDIF registers for i.MX233Marek Vasut2013-05-06-9/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | Extend the regs-lcdif.h with registers for i.MX233. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| * | arm: mxs: Add LCDIF clock configuration functionMarek Vasut2013-05-06-0/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function turns on the LCDIF clock and configures it's frequency. The dividers settings are calculated within the function and the current implementation should be fast and accurate. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| * | arm: mxs: Preprocess u-boot.bd so they contain full pathMarek Vasut2013-05-06-4/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The u-boot-imx23.bd and u-boot-imx28.bd need to be preprocessed, otherwise they have issues with out-of-tree build where elftosb tool couldn't sometimes find the u-boot.bin and spl/u-boot-spl.bin . Preprocess these .bd files with sed and insert full path to u-boot.bin and spl/u-boot-spl.bin to prevent this issue. Moreover, to avoid adding more churn into main Makefile, move all this preprocessing and u-boot.sb generation into CPU directory instead. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
| * | arm: mx23: Fix VDDMEM misconfigurationMarek Vasut2013-05-06-20/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The VDDMEM ramped up in very weird way as it was horribly misconfigured. Instead of setting up VDDMEM in one swipe, let it rise slowly the same way as VDDD and VDDA in spl_power_init.c and then only clear ILIMIT before memory gets inited. This makes sure the VDDMEM rises sanely, not jumps up and down as it did till now. The VDDMEM prior to this change did this: 2V0____ .--------2V5 | `--' 0V____| The VDDMEM now does this: 2V0_____,-----------2V5 / 0V__| Moreover, VDDIO on MX23 uses 25mV steps while MX28 uses 50mV steps, fix this difference too. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| * | mxs: Explain why some mx23 DDR registers are not configuredFabio Estevam2013-05-06-0/+9
| | | | | | | | | | | | | | | | | | | | | Put an explanation in the source code as to why some DDR registers do not need to be configured. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | mx23: Operate DDR voltage supply at 2.5VFabio Estevam2013-05-06-2/+2
| | | | | | | | | | | | | | | | | | | | | After the recent fixes in the mx23 DDR setup, it is safe to operate DDR voltage at the recommended 2.5V voltage level again. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | imx: mx5: Remove legacy iomux supportBenoît Thébaudeau2013-05-05-1157/+1
| | | | | | | | | | | | | | | | | | | | | | | | Legacy iomux support is no longer needed now that all boards have been converted to iomux-v3. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Reviewed-by: Marek Vasut <marex@denx.de>
| * | imx: iomux-v3: Add iomux-mx53.hBenoît Thébaudeau2013-05-05-0/+1232
| | | | | | | | | | | | | | | | | | | | | | | | Allow usage of the imx-common/iomux-v3.h framework by including pad settings for the i.MX53. The content of the file is taken from Freescale's Linux kernel at commit 4ab3715, plus the required changes to make it work in U-Boot. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * | imx: iomux-v3: Add missing definitions to iomux-mx51.hBenoît Thébaudeau2013-05-05-27/+124
| | | | | | | | | | | | | | | | | | | | | | | | Add missing definitions that are required by future changes. By the way, make some cosmetic cleanup. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * | imx: iomux-mx51: Fix MX51_PAD_EIM_CS2__GPIO2_27Benoît Thébaudeau2013-05-05-1/+1
| | | | | | | | | | | | | | | | | | | | | In ALT1 mode, EIM_CS2 is GPIO2[27], not ESDHC1.CD. Hence, rename MX51_PAD_EIM_CS2__SD1_CD to MX51_PAD_EIM_CS2__GPIO2_27. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * | imx: mx35: Remove legacy iomux supportBenoît Thébaudeau2013-05-05-764/+0
| | | | | | | | | | | | | | | | | | | | | Legacy iomux support is no longer needed now that all boards have been converted to iomux-v3. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * | imx: iomux-v3: Add iomux-mx35.hBenoît Thébaudeau2013-05-05-1/+1277
| | | | | | | | | | | | | | | | | | | | | | | | Allow usage of the imx-common/iomux-v3.h framework by including pad settings for the i.MX35. The content of the file is taken from Linux kernel at commit 267dd34, plus the required changes to make it work in U-Boot. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * | imx: mx25: Remove legacy iomux supportBenoît Thébaudeau2013-05-05-570/+0
| | | | | | | | | | | | | | | | | | | | | Legacy iomux support is no longer needed now that all boards have been converted to iomux-v3. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * | imx: iomux-v3: Add iomux-mx25.hBenoît Thébaudeau2013-05-05-1/+550
| | | | | | | | | | | | | | | | | | | | | | | | Allow usage of the imx-common/iomux-v3.h framework by including pad settings for the i.MX25. The content of the file is taken from Linux kernel at commit 267dd34, plus the required changes to make it work in U-Boot. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * | arm: mx5: Add NAND clock handlingMarek Vasut2013-05-05-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Augment the MX5 clock code with function to enable and configure NFC clock. This is necessary to get NFC working on MX5. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com>
| * | arm: mx5: Add SPL support code to MX5Marek Vasut2013-05-05-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix minor adjustments needed to get SPL framework building on MX5. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com>
| * | arm: imx: Pack u-boot.bin into uImage for SPLMarek Vasut2013-05-05-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The U-Boot SPL can parse the uImage format and gather information from it about the payload. Make use of this and wrap u-boot.bin into uImage format. The benefit is the SPL will know the size of the payload instead of using fixed size of the payload defined at compile time. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com>
| * | mxs: spl_mem_init: Change EMI port priorityFabio Estevam2013-05-05-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | FSL bootlets code set the PORT_PRIORITY_ORDER field of register HW_EMI_CTRL as 0x2, which means: PORT0231 = 0x02 Priority Order: AXI0, AHB2, AHB3, AHB1 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | mxs: spl_mem_init: Skip the initialization of some DRAM_CTL registersFabio Estevam2013-05-05-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as per FSL bootlets code. mx23 Reference Manual mark HW_DRAM_CTL27 and HW_DRAM_CTL28 as "reserved". HW_DRAM_CTL8 is setup as the last element. So skip the initialization of these DRAM_CTL registers. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | mxs: spl_mem_init: Remove erroneous DDR settingFabio Estevam2013-05-05-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | On mx23 there is no 'DRAM init complete' in register HW_DRAM_CTL18. Remove this erroneous setting. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | mxs: spl_mem_init: Fix comment about start bitFabio Estevam2013-05-05-1/+1
| | | | | | | | | | | | | | | | | | Start bit is part of HW_DRAM_CTL8 register, so fix the comment. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | mx23: Fix pad voltage selection bitFabio Estevam2013-05-05-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On mx23 the pad voltage selection bit needs to be always '0', since '1' is a reserved value. For example: Pin 108, EMI_A06 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Fix the pad voltage definitions for the mx23 case. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
| * | tools: arm: imx: Implement BOOT_OFFSET command for imximageMarek Vasut2013-04-28-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement BOOT_OFFSET command for imximage. This command is parallel to current BOOT_FROM command, but allows more flexibility in configuring arbitrary image header offset. Also add an imximage.cfg with default offset values into arm/arch/imx-common/ so the board-specific imximage.cfg can include this file to avoid magic constants. The syntax of BOOT_OFFSET command is "BOOT_OFFSET <u32 offset>". Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Stefan Roese <sr@denx.de>
| * | imx: iomux-v3: Include PKE and PUE to pad control pull definitionsBenoît Thébaudeau2013-04-28-11/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PUE requires PKE to mean something, as do pull values with PUE, so do not compell users to explicitly use PKE and PUE everywhere. This is also what is done on Linux and what has already been done for i.MX51. By the way, remove some unused pad control definitions. There is no change of behavior. Note that SPI_PAD_CTRL was defined by several boards with a pull value, but without PKE or PUE, which means that no pull was actually enabled in the pad. This might be a bug in those boards, but this patch does not change the behavior, so it just removes the meaningless pull value from those definitions. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * | imx: iomux-v3: Restore Linux's NEW_PAD_CTRL() macroBenoît Thébaudeau2013-04-28-0/+3
| | | | | | | | | | | | | | | | | | This macro will be useful for future changes. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * | imx: iomux-v3: cosmetic: Reorganize definitionsBenoît Thébaudeau2013-04-28-14/+19
| | | | | | | | | | | | | | | | | | | | | Keep pad control definitions together, and organize definitions in a more legible way. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
generated by cgit v1.1 at 2024-11-18 22:22:48 +0000