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* lpc32xx: add Ethernet supportAlbert ARIBAUD \(3ADEV\)2015-04-10-0/+20
| | | | Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* Merge branch 'u-boot/master'Albert ARIBAUD2015-04-10-2737/+2173
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| * am33xx/ddr.c: Fix regression on DDR2 platformsTom Rini2015-04-07-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Back in fc46bae a "clean up" was introduced that intended to reconcile some of the AM335x codepaths based on how AM43xx operates. Unfortunately this introduced a regression on the DDR2 platforms. This was un-noticed on DDR3 (everything except for Beaglebone White) as we had already populated sdram_config correctly in sequence. This change brings us back to the older behavior and is fine on all platforms. Tested on Beaglebone White, Beaglebone Black and AM335x GP EVM Reported-by: Matt Ranostay <mranostay@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
| * dts: peach_pi: Add DT properties needed for displayAjay Kumar2015-04-06-0/+3
| | | | | | | | | | | | | | | | | | | | Add backlight enable GPIO, and delay needed for panel powerup via FIMD DT node. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * dts: peach_pit: Add SLP and RST GPIO properties in parade DT nodeAjay Kumar2015-04-06-0/+2
| | | | | | | | | | | | | | | | | | | | Now that parade driver supports reading SLP and RST GPIO from DT, specify the same in parade DT node. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * dts: exynos54xx: Add samsung, pwm-out-gpio property to FIMD nodeAjay Kumar2015-04-06-0/+1
| | | | | | | | | | | | | | | | | | | | Now that the exynos_fb driver supports handling backlight GPIO via DT, specify pwm output property via FIMD DT node. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos5: Fix rpll_sdiv to support both peach-pit and peach-pi panelsAjay Kumar2015-04-06-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The existing setting for rpll_sdiv generates 70.5Mhz RPLL video clock to drive 1366x768 panel on peach_pit. This clock rate is not sufficient to drive 1920x1080 panel on peach-pi. So, we adjust rpll_sdiv to 3 so that it generates 141Mhz pixel clock which can drive peach-pi LCD. This change doesn't break peach-pit LCD since 141/2=70.5Mhz, i.e FIMD divider at IP level will get set to 1(the required divider setting will be calculated and set by exynos_fimd_set_clock()) and hence peach-pit LCD still works fine. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * arm: exynos: add display clocks for Exynos5800Ajay Kumar2015-04-06-3/+65
| | | | | | | | | | | | | | | | | | | | Add get_lcd_clk and set_lcd_clk callbacks for Exynos5800 needed by exynos video driver. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos: Clock: Fix exynos5_get_periph_rate for I2C.Guillaume GARDET2015-04-06-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 2e82e9252695a612ab0cbf40fa0c7368515f6506 'Exynos: Clock: Cleanup soc_get_periph_rate' introduced a bug in I2C config. This patch makes cros_ec keyboard working again on Samsung Chromebook (snow). Changes in V2: reorder lines as requested by Joonyoung Shim. Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr> Cc: Akshay Saraswat <akshay.s@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Joonyoung Shim <jy0922.shim@samsung.com> Reviewed-by: Simon Glass <sjg@chroimum.org> Tested-by: Simon Glass <sjg@chroimum.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Merge git://git.denx.de/u-boot-arcTom Rini2015-04-03-529/+500
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| | * arc: add support for SLC (System Level Cache, AKA L2-cache)Alexey Brodkin2015-04-03-0/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARCv2 cores may have built-in SLC (System Level Cache, AKA L2-cache). This change adds functions required for controlling SLC: * slc_enable/disable * slc_flush/invalidate For now we just disable SLC to escape DMA coherency issues until either: * SLC flush/invalidate is supported in DMA APIin U-Boot * hardware DMA coherency is implemented (that might be board specific so probably we'll need to have a separate Kconfig option for controlling SLC explicitly) Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| | * board: Switch Abilis TB-100 board to Driver Model for serial portAlexey Brodkin2015-04-03-0/+25
| | | | | | | | | | | | | | | Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org>
| | * serial-arc: switch to DMAlexey Brodkin2015-04-03-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | Now when all infrastructure in ARC is ready for it let's switch ARC UART to driver model. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org>
| | * arc: minor fixes in KconfigAlexey Brodkin2015-04-03-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [1] Fix misspeling in ARC_CACHE_LINE_SHIFT dependency, now cache-line lenth selection is correctly enabled if either I$ or D$ are enabled. [2] Add dummy entry to target list to make sure target type is always mentioned in defconfig. Otherwise defconfig for the first target in the list will not have target name and later on with addition of the new target on top of the list in Kconfig will lead to corrupted configuration expanded from defconfig. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| | * arc: get rid of CONFIG_SYS_GENERIC_GLOBAL_DATAAlexey Brodkin2015-04-03-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As discussed on mailing list we're drifting away from CONFIG_SYS_GENERIC_GLOBAL_DATA in favour to use of board_init_f_mem() for global data. So do this for ARC architecture. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| | * arc: clean-up init procedureAlexey Brodkin2015-04-03-77/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intention behind this work was elimination of as much assembly-written code as it is possible. In case of ARC we already have relocation fix-up implemented in C so why don't we use C for U-Boot copying, .bss zeroing etc. It turned out x86 uses pretty similar approach so we re-used parts of code in "board_f.c" initially implemented for x86. Now assembly usage during init is limited to stack- and frame-pointer setup before and after relocation. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Simon Glass <sjg@chromium.org>
| | * arc: move low-level interrupt and exception handlers in a separate fileAlexey Brodkin2015-04-03-144/+152
| | | | | | | | | | | | | | | | | | | | | | | | This separation makes maintenance of code easier because those low-level interrupt- or exception handling routines are pretty static and usually require not much care while start-up code is a subject of modifications and enhancements. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| | * arc: merge common start-up code between ARC and ARCv2Alexey Brodkin2015-04-03-294/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Even though ARCompact and ARCv2 are not binary compatible most of assembly instructions are used in both. With this change we'll get rid of duplicate code. Still IVTs are implemented differently so we're keeping them in separate files. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| | * arc: cache - build invalidate_icache_all() and invalidate_dcache_all()Alexey Brodkin2015-04-03-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | always Make both invalidate_icache_all() and invalidate_dcache_all() available even if U-Boot is configured with CONFIG_SYS_DCACHE_OFF and/or CONFIG_SYS_ICACHE_OFF. This is useful because configuration of U-Boot may not match actual hardware features. Real board may have cache(s) but for some reason we may want to run U-Boot with cache(s) disabled (for example if some peripherals work improperly with existing drivers if data cache is enabled). So board may start with cache(s) enabled (that's the case for ARC cores with built-in caches) but early in U-Boot we disable cache(s) and make sure all contents of data cache gets flushed in RAM. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-04-03-22/+128
| |\ \ | | |/ | |/| | | | | | | | | | | | | Conflicts: board/armltd/vexpress64/vexpress64.c Signed-off-by: Tom Rini <trini@konsulko.com>
| | * tegra: pinmux: fix FUNCMUX_NDFLASH_KBC_8_BITLucas Stach2015-03-30-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Even the 8-bit case needs KBCB configured, as pin D7 is located in this pingroup. Please note that pingroup ATC seems to come out of reset with its config set to NAND so one needs to explicitly configure some other function to this group in order to avoid clashing settings which is outside the scope of this patch. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Tested-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * ARM: tegra: fix colibri_t20 machine typeMarcel Ziswiler2015-03-30-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A while ago I got Russell to change the machine type of our Colibri T20 from COLIBRI_TEGRA2 to COLIBRI_T20 which at least in parts is also reflected in his machine registry: http://www.arm.linux.org.uk/developer/machines/list.php?id=3323 For us it is really very beneficial to actually still be able to boot downstream L4T kernel with its working hardware accelerated graphics/multimedia stack albeit it being proprietary/closed-source. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * ARM: tegra: rename colibri_t20 board/configuration/device-treeMarcel Ziswiler2015-03-30-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In accordance with our other modules supported by U-Boot and as agreed upon for Apalis/Colibri T30 get rid of the carrier board in the board/ configuration/device-tree naming. While at it also bring the prompt more in line with our other products. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * ARM: tegra: enable MIPI PAD CTRL support for Tegra124Stephen Warren2015-03-30-0/+26
| | | | | | | | | | | | | | | | | | | | | This allows selection between CSI and DSI_B on the MIPI pads. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * ARM: tegra: pinctrl: add support for MIPI PAD control groupsStephen Warren2015-03-30-0/+73
| | | | | | | | | | | | | | | | | | | | | | | | Some pinmux controls are in a different register set. Add support for manipulating those in a similar way to existing pins/groups. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * ARM: tegra: pinctrl: minor cleanupStephen Warren2015-03-30-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move struct pmux_pingrp_desc type and tegra_soc_pingroups variable declaration together with other pin/mux level definitions. Now the whole file is grouped/ordered pin/mux-related then drvgrp-related definitions. Fix typo in ifdef comment. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * ARM: tegra: pinctrl: move Tegra210 code to the correct dirStephen Warren2015-03-30-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patches that added the Tegra210 pinctrl driver and renamed directories arch/arm/cpu/tegra{$soc}-common -> arch/arm/mach-tegra/tegra-${soc} crossed. Move the Tegra210 pinctrl driver to the correct location. This wasn't detected since Tegra210 support is in the process of being added, and isn't buildable yet. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2015-03-31-151/+142
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| | * | ARM: atmel: at91sam9n12ek: enable spl supportBo Shen2015-04-01-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable SPL support for at91sam9n12ek boards, now it supports boot up from NAND flash, serial flash. Signed-off-by: Bo Shen <voice.shen@atmel.com>
| | * | ARM: atmel: at91sam9x5ek: enable spl supportBo Shen2015-04-01-4/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable SPL support for at91sam9x5ek board. Now, it supports boot up from NAND flash and SPI flash. Signed-off-by: Bo Shen <voice.shen@atmel.com>
| | * | ARM: atmel: at91sam9m10g45ek: enable spl supportBo Shen2015-04-01-1/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Supports boot up from NAND flash with software ECC eanbled. And supports boot up from SD/MMC card with FAT file system. As the boot from SD/MMC card with FAT file system, the BSS segment is too big to fit into SRAM, so, use the lds to put it into SDRAM. Signed-off-by: Bo Shen <voice.shen@atmel.com>
| | * | ARM: atmel: arm926ejs: fix clock configurationBo Shen2015-04-01-26/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Config MCKR according to the datasheet sequence, or else it will cause the MCKR configuration failed. Remove timeout checking for clock configuration, if configure the clock failed, let the system hang while not run in wrong clock configuration. Signed-off-by: Bo Shen <voice.shen@atmel.com> Tested-by: Heiko Schocher <hs@denx.de>
| | * | spl_atmel.c: Switch s_init to board_init_fTom Rini2015-04-01-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To facilitate changing lowlevel_init to become s_init, move the current contents of s_init into board_init_f and add the rest of what board_init_f does here. In order to compile clean without CONFIG_SKIP_LOWLEVEL_INIT set, leave an empty stub of s_init(). It can be removed when lowlevel_init becomes s_init. Cc: Bo Shen <voice.shen@atmel.com> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Tested-by: Matt Porter <mporter@konsulko.com> on sama5d3_xplained Signed-off-by: Tom Rini <trini@ti.com> [rebased on current master, leave s_init() as empty stub] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| | * | ARM: atmel: armv7: switch to use common timer functionsBo Shen2015-04-01-61/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit 8dfafdd (Introduce common timer functions), add common timer functions, we can use them directly. Signed-off-by: Bo Shen <voice.shen@atmel.com> [rebase on current master] Sigend-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| | * | ARM: atmel: arm9: switch to use common timer functionsBo Shen2015-04-01-59/+18
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Bo Shen <voice.shen@atmel.com> [rebase on current master] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | | Merge branch 'master' of git://git.denx.de/u-boot-imxTom Rini2015-03-31-0/+52
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| | * | board/seco: Add mx6q-uq7 basic board supportBoris BREZILLON2015-03-23-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add basic SECO MX6Q/uQ7 board support (Ethernet, UART, SD are supported). It also adds a Kconfig skeleton to later add more SECO board (supporting SoC and board variants). Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * | ARM: iMX: define an IMX_CONFIG Kconfig optionBoris BREZILLON2015-03-23-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IMX_CONFIG is currently passed via the SYS_EXTRA_OPTIONS which is marked as deprecated. Add a new Kconfig file under arch/arm/imx-common and define the IMX_CONFIG Kconfig in there. Each board is supposed to provide a default value pointing to the appropriate imximage.cfg file. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * | ARM: mx6: move to a standard arch/board approachBoris BREZILLON2015-03-23-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale boards are currently all defined in arch/arm/Kconfig, which makes them hard to detect. Moreover the MX6 SoC variant (Q, D, DL, S, SL) selection is currently done via the SYS_EXTRA_OPTIONS option which marked as deprecated. Move to a more standard way to select sub-architecture and board by creating a Kconfig under arch/arm/cpu/armv7/mx6 and a new ARCH_MX6 option. Existing MX6 board definitions should be moved in this new Kconfig in choice menu, and new boards should be directly declared in this menu. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| * | | sunxi: use CONFIG_SYS_CLK_FREQ to set cpu clockIain Paton2015-03-29-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | make the CPU clock selectable via Kconfig this removes the sunxi specific CONFIG_CLK_FULL_SPEED defined in each soc header and replaces it's use in board/sunxi/board.c with CONFIG_SYS_CLK_FREQ from Kconfig which allows us to configure board specific frequency on boot Signed-off-by: Iain Paton <ipaton0@gmail.com> [hdegoede@redhat.com s/CONFIG_SYS_CLK_FREQ/CONFIG_TIMER_CLK_FREQ/ for the arch-timer clk speed on sun7i to fix mis-compile on sun7i] Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | sunxi: sun4i: improve cpu clock selection methodIain Paton2015-03-29-16/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clock_set_pll1 would pick the next highest available cpu clock speed if a value not in the pre defined table was selected. this potentially results in overclocking the soc. reverse the selection method so that we select the next lowest speed and add the missing 912Mhz setting that's requested by sun7i which also uses the sun4i clock code. Signed-off-by: Iain Paton <ipaton0@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | sunxi: musb: Fix some lo speed devices not working with musb hostHans de Goede2015-03-29-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The usb0 / otg phy on sunxi boards has a bug where it wrongly detects a high speed squelch on usb reset deassert when a lo speed device is plugged in. The android kernel has a work around for this in the form of temporary disabling the phy's squelch detection on reset deassert, this commit adds the same workaround to the u-boot sunxi musb code, thereby fixing various usb lo speed devices not working. Tested with a (before non working) usb keyboard and a usb 2.4 GHz wireless keyboard/mouse combo receiver. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | armv8: semihosting: delete external interfaceLinus Walleij2015-03-28-109/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that loading files using semihosting can be done using a command in standard scripts, and we have rewritten the boardfile and added it to the Vexpress64, let's delete the external interface to the semihosting file retrieveal and rely solely on these commands, and staticize them inside that file so the whole business is self-contained. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | armv8: semihosting: add a command to load semihosted imagesLinus Walleij2015-03-28-0/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of sprinkling custom code and calls over the Vexpress64 boardfile, create a command that loads images using semihosting just like we would load from flash memory of over the network, using a special command: smhload <image> <address> This will make it possible to remove some custom calls and code and make the boot easier. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | armv8: semihosting: do not inline trap callLinus Walleij2015-03-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The semihosting trap call does not like being inlined, probably because that will mean register reordering screwing up the return value in r0, so tag this function "noinline". Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | m68k: merge per-CPU config.mk into arch/m68k/MakefileMasahiro Yamada2015-03-28-101/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Collect CPU specific flags into the single place. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Angelo Dureghello <angelo@sysam.it>
| * | | m68k: mcf547x_8x: move CPU type to Kconfig and refactor config.mkMasahiro Yamada2015-03-28-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the CPU type config options from include/configs/*.h to arch/m68k/Kconfig and refactor the CPU flags select in arch/m68k/cpu/mcf547x_8x/config.mk. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Angelo Dureghello <angelo@sysam.it>
| * | | m68k: mcf523x: move CPU type to Kconfig and refactor config.mkMasahiro Yamada2015-03-28-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the CPU type config options from include/configs/M5235EVB.h to arch/m68k/Kconfig and refactor the CPU flags select in arch/m68k/cpu/mcf523x/config.mk. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Angelo Dureghello <angelo@sysam.it>
| * | | m68k: mcf5227x: move CPU type to Kconfig and refactor config.mkMasahiro Yamada2015-03-28-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the CPU type config options from include/configs/M52277EVB.h to arch/m68k/Kconfig and refactor the CPU flags select in arch/m68k/cpu/mcf5227x/config.mk. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Angelo Dureghello <angelo@sysam.it>
| * | | m68k: mcf5445x: move CPU type to Kconfig and refactor config.mkMasahiro Yamada2015-03-28-8/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit intends to stop grepping CPU type in arch/m68k/cpu/mcf5445x/config.mk. Move the CPU type config options from include/configs/*.h to arch/m68k/Kconfig and refactor the CPU flags select in arch/m68k/cpu/mcf5445x/config.mk. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Angelo Dureghello <angelo@sysam.it>
generated by cgit v1.1 at 2024-11-07 20:52:18 +0000