| Commit message (Collapse) | Author | Age | Lines |
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Add SION bit for all i2c pin mux settings.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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This patch is to support Bus Encryption Engine(BEE) for i.MX 6UL.
Supported feature:
1. SNVS key and soft key
2. CTR and ECB mode
3. Specify address region to bee.
Two commands are included:
bee init [key] [mode] [start] [end] - BEE block initial
"Example: bee init 1 1 0x80000000 0x80010000\n"
bee test [region]
"Example: bee test 1\n"
Mapping:
[0x10000000 - (0x10000000 + size - 1)] : [start - (start + size - 1)]
[0x30000000 - (0x30000000 + IRAM_SIZE - 1)] : [IRAM_BASE_ADDR -
(IRAM_BASE_ADDR + IRAM_SIZE - 1)]
Whatever start is, start - (start + size -1) will be fixed mapping to
0x10000000 - (0x10000000 + size - 1)
Since default AES region's protected size is SZ_512M, so
on mx6ul evk board, you can not simply run 'bee init', it will
overlap with uboot execution environment, you can use
'bee init 0 0 0x80000000 0x81000000'.
If want to use bee, Need to define CONFIG_CMD_BEE in board configuration
header file, since CONFIG_CMD_BEE default is not enabled.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Since there is another 9x9 package for mx6ul, modify the BSP names
of ddr3 arm2 board and evk board to add 14x14 package info.
Also modify the loaded dtb file to align with kernel.
After the change, the build target for mx6ul ddr3 arm2 board is:
mx6ul_14x14_ddr3_arm2_config
and the build target for mx6ul evk board is:
mx6ul_14x14_evk_config
Signed-off-by: Ye.Li <B37916@freescale.com>
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On mx7d 12x12 lpddr3 arm2 board, POR_B reset in uboot will fail stress
reset test, and hangs in rom code. Rom log buffer show thats wrong
hab_image_entry and runs into serial download mode. Also there is no
time delay reset circuit for this board.
We found when disable CONFIG_VIDEO, all seems fine. Actually,
only the following piece of code can make stress reset ok,
"
writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, ®s->hw_lcdif_ctrl1_clr);
while (--timeout) {
if (readl(®s->hw_lcdif_ctrl1) & LCDIF_CTRL1_VSYNC_EDGE_IRQ)
break;
udelay(1);
}
"
Here we use lcdif_power_down API which is better to shutdown lcdif same as
the way used in arch_preboot_os.
Implement reset_misc for mx7, since it does not hurt for others boards.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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On MX7D, boot rom can provide some boot information such as boot device,
arm freq, axi freq, etc. (see the structure below)
Offset Byte4 | Byte3 | Byte2 | Byte1
0x0 Reserved | Boot Device Type | Boot Device Instance | Reserved
0x4 ARM core frequency(in Hz)
0x8 AXI bus frequency(in Hz)
0x0C DDR frequency(in Hz)
0x10 GPT1 input clock frequency(in Hz)
0x14 Reserved
0x18
0x1C
The boot information can be accessed by get the pointer at 0x1E8. This patch
changes the u-boot to use the new approach. When manufacture boot, the info
recorded is the actual SD port, not the failed device.
Signed-off-by: Ye.Li <B37916@freescale.com>
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* Add mx7d_19x19_lpddr3_arm2 target board supprt
* Enable i2c, spinor, usb, usdhc, qspi, enet, uart
* Build targets
mx7d_19x19_lpddr3_arm2_defconfig
mx7d_19x19_lpddr3_arm2_eimnor_defconfig
- Set EIMNOR settings for Intel Sibley Asynchronous mode
- Set flash sector size for 256kb (erase block size)
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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The iomuxc structure has changed to add 0x4000 offset for i.MX6SX and UL,
so when using this structure to access gpr registers needs to change
the base address to IOMUXC_BASE_ADDR.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Get the Unique ID of the chip from the fuse TESTER0 and TESTER1.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Change MXC_CCM_CCGR6_I2C4_xx to MXC_CCM_CCGR6_I2C4_SERIAL_xx
Remove duplicated mxs_set_vadcclk
Correct enable_pll_video usage
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Add board code for mx6ul ddr3 arm2 board.
QSPI, USDHC, ENET, USB, VIDEO, SPINOR, EIMNOR
Add sd1, qspi and spinor boot support
DDR script is 1.02 version.
Signed-off-by: Fugang Duan <b38611@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Add BSP codes to support modules on the board:
I2C, SD/eMMC, NAND, QSPI, FEC1/FEC2, USB, LCDIF, 74LV, Serial
DDR version: 1.0
Build target: mx6ulevk_config
mx6ulevk_qspi1_config
Signed-off-by: Ye.Li <B37916@freescale.com>
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PAD_CTL_SPEED_LOW for mx6ul same with mx6sx.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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add i.MX6UL clock related settings/macros/apis
When using TFT43AB, its pixel size is 480x272 which needs a
slow pix clock. Without apply the test_div in PLL video, we can't
get the pix clock in the rate.
So change the LCDIF clock calculation to use the test_div.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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I2C4 support for i.MX
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Remove PCIe, xPU power, PL310 L2 Cache for MX6UL.
Update FEC MAC address, WDOG settings, USDHC clock rate.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Since the system counter driver will also be used by mx6ul, move
this timer driver to imx-common and rename it as syscounter.c
For mx6ul and mx7, configurations are used for choose the GPT timer
or system counter timer (default).
GPT timer: CONFIG_GPT_TIMER
System counter timer: CONFIG_SYSCOUNTER_TIMER
Signed-off-by: Ye.Li <B37916@freescale.com>
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Update imx registers base address for i.MX6UL
Signed-off-by: Ye.Li <B37916@freescale.com>
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Add i.MX6UL pins IOMUX file which defines the IOMUX settings for
choose.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Add MXC_CPU_MX6UL for i.MX6UL CPU type which is got at runtime.
The 0x64 is defined as i.MX6Ul CPU type value in RM, but the value
has been occupied by i.MX6D as a dummy CPU type.
So we also need change i.MX6D to a invalid value 0x67.
Signed-off-by: Ye.Li <B37916@freescale.com>
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We should align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN, otherwise
we may encounter errors,
"
NAND: ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0
ERROR: v7_dcache_inval_range - stop address is not aligned - 0xbdf1f4a0
ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0
"
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Update settings for PRE. Value for Saturation THR of PREx,
changed from 0x20 to 0x10 to make system more stable.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit 02e7090604e55d9690532294b02b499609d46e63)
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In i.MX7d platform, fec MDC root clock is ENET_AXI_ROOT_CLK, not
ipg clock, correct it.
Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked from commit 07105e18dd0899c47ef80d3fddecf3ef250d895a)
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Merge hab_caam_clock_enable and hab_caam_clock_disable into
one function
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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This problem is found when debugging QuadSPI. When "A" bit is enabled,
unaligned access will cause data abort exception. Actually, we do not
want this exception. So clear the align bit for MX6 SOCs.
Tested this code with android team colleague and did not find problem.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit aa76a7e472e34bc59554f9932d611b1047d24590)
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Since the following piece settings can not be in DCD table, we
add them in enable_ipu_clock.
"
setmem /32 0x00bb048c = 0x00000002 ## Bypass IPU1 QoS generator
setmem /32 0x00bb050c = 0x00000002 ## Bypass IPU2 QoS generator
setmem /32 0x00bb0690 = 0x00000200 ## Bandwidth THR for of PRE0
setmem /32 0x00bb0710 = 0x00000200 ## Bandwidth THR for of PRE1
setmem /32 0x00bb0790 = 0x00000200 ## Bandwidth THR for of PRE2
setmem /32 0x00bb0810 = 0x00000200 ## Bandwidth THR for of PRE3
setmem /32 0x00bb0694 = 0x00000020 ## Saturation THR for of PRE0
setmem /32 0x00bb0714 = 0x00000020 ## Saturation THR for of PRE1
setmem /32 0x00bb0794 = 0x00000020 ## Saturation THR for of PRE2
setmem /32 0x00bb0814 = 0x00000020 ## Saturation THR for of PRE
"
CONFIG_VIDEO_IPUV3 is always defined in mx6sabre_common.h,
the settings sure will effect.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit 61cec88a59ebf450dd1352d81e03b5aa842e1d71)
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The issue on the i.MX7D is that, there is one cache-able memory access
between the L1 and L2 cache flush by calling the flush_dache_all->
v7_maint_dcache_all() [Flush L1 and L2 cache) which written in the C code.
L1-cache-flush -> This will flush L1 cache to L2 cache in the end.
Cache-able memory access -> This will have the chance cause the L1 line-fill
with dirty data from L2 cache(L1 cache-line dirty,
L2 clean)
L2-cache-flush -> This will only flush L2 cache to L3, but still
some dirty data on the L1 cacheline.
After C & M bit clean, -> The dirty data on the L1 cache line lost, which will
cause memory coherent issue if that dirty cache line
has some useful data
The only problem here is: there is one cache-cable memory access between L1 and L2 cache flush.
This patch should works fine on the i.MX6 and i.MX7.
The second cache flush have zero impact on the i.MX6, but this is really need for
the i.MX7D platform due to the L1 line-fill during the first dcache_flush.
And the second flush will not bring in the L1 dirty cache line due to the C bit is
clear now, which means the dcache is disabled.
Acked-by: Jason Liu<r64343@freescale.com>
Reviewed-by: Jason Liu<r64343@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit f5d5f07fba936c4bb05c887de9d72fb75b3dc0f2)
(cherry picked from commit 86c784cf4c4b633d37a76de7d47155c08f75dc82)
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Use correct GPR address.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Add SION for i2c pin mux, otherwise will cause error.
Found this problem on mx6sxsabreauto board.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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is_soc_rev should be casted to signed int, otherwise
may incur errors when detecting cpu types.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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* Extend IOMUXC-LPSR IO pads configuration options
* Add alternative configuration modes for IO pads from
IOMUXC-LPSR
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
(cherry picked from commit ca20aa7ca0c21b9766e0c34cfec275aaab0f11e7)
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This EPDC/EPXP QoS setting is needed for EPDC stress test to pass.
This patch remove the #ifdef to make sure set_epdc_qos be called always.
Signed-off-by: Robby Cai <r63905@freescale.com>
(cherry picked from commit d2fb113740b2c67958862503dda2a40191ab0899)
(cherry picked from commit 581aa86581bb1178c5df4ad5298e5b85c53f1186)
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* Correct daisy chain settings for LPSR iomux controller
* Add IOMUX_LPSR_SEL_INPUT_OFS only when pad is identified
to be part of lpsr-iomuxc domain
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
(cherry picked from commit e4fd6550b3e5458aaf5049a7e6a12d6e4443c53a)
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* Add IMX7D iomuxc-lpsr I2C1 and I2C2 pad configuration settings
* Input select offset input_sel_ofs = 0x05xx + IOMUX_LPSR_SEL_INPUT_OFS
allows to access register in iomuxc controller for imx_iomux_v3_setup_pad
I2C daisy chaing configuration.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit bca65c5ee1099f99b880be325c9fa0a568ab88de)
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* For IOMUXC LPSR pads when daisy chain register needs to be set the
result offsets for sel_input register is incorrect as base address is
0x302C0000 and the passed offset does not resolve to the intended input
sel pad register; input sel base offset should start in 0x30330000.
* Add an addiotional fixed offset of 0x70000 to address the
input sel offset:
INPUT_SEL = 0x302C0000 + 0x70000 + sel_input_ofs.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 5d4612613eb2e85f1929d8cf5cb6aac6ba9e5fd7)
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Under very rare timing circumstances, transitioning into streaming
mode might create a data corruption. Present on Two or more processors
or 1 core with ACP, all revisions. This erratum can be worked round
by setting bit[22] of the undocumented Diagnostic Control Register to 1.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
(cherry picked from commit 70ad44e523680de67dd8b7a7505d7f27799980ee)
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Incorrect hab_rvt addresses were used for getting HAB functions.
Need to change to addresses in unified section.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 5ae1cb9d8e7cd7babd1d7ef7f2303664a4e15c26)
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is_mx6dqp should be only applied for MX6
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit d860559f7913f16f7cb248f7b44140e8c1aa3ee9)
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We should print "MX6QP Rev1.0", but not "MX6Q Rev2.0".
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit 64b2be69835af80e0dbc151175617942683a3167)
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Apply errata based on PL310 version instead of compile
time. Also set Prefetch offset to 15, since it improves
memcpy performance by 35%. Don't enable Incr double
Linefill enable since it adversely affects memcpy
performance by about 32MB/s and reads by 90MB/s. Tested
with 4K to 16MB sized src and dst aligned buffer.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
(cherry picked from commit 31751fa9cf29ef4056f49fe06a54700a89c9bdc5)
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To support lower clock frequency, needs to set post divider and
test divider in PLL_VIDEO. So update LCDIF clock settings function
to support this feature.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit b4d3b2a8eaf1ad1dc529ae2348d1646a2833b701)
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Ungate the EPDC clock at system up if the EPDC is enabled
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit f215632cb25d1076ab5c5465efdfad2212010d8d)
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Add the QoS settings function which is used for EPDC
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 725a3bbbe0a172a0f4619d99bc198b9367b9fc5d)
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The i.MX6QP has a PRG module, need to enable its clock for using
IPU.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Brown Oliver <B37094@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 089f399ea07db79d6bca8fdc08b442b59eb55feb)
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Since the i.MX6QP has fixed the issue in boot ROM, so remove the workaround
for i.MX6QP.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 96e13b57ead3ed00c3a32c5373c7a2a876947f99)
Conflicts:
arch/arm/cpu/armv7/mx6/hab.c
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Since i.MX6QP changes some CCM registers, so modify the clocks settings to
follow the hardware changes.
A new CONFIG_MX6QP is introduced here and is used for the CCM difference.
At default CONFIG_MX6Q is enabled along with the CONFIG_MX6QP.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 5e4d1537ce9a476c8404126350f05d8976c5aa35)
Conflicts:
arch/arm/cpu/armv7/mx6/clock.c
arch/arm/include/asm/arch-mx6/crm_regs.h
include/configs/mx6_common.h
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Since i.MX6DQP has fixed the L2 cache issue, enable the double line
fill feature to provide better performance.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit aa8a38edb67d4d1375d10bee9bf46557369fb5c4)
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Add new cpu type for i.MX6DQP and providing a dynamical
detecting function.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit ccf3b130d71cf3dd9a97d3bb424931bf6bd7e8c0)
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For APBH-DMA enabled case, we have to enable rawnand clock for mxs_dma_init.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 42f42939bbd8161ce283a6af326d0f313cc4c36c)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Update GPMI NAND driver and BCH head file with definitions for CONFIG_MX7
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 9c50677dac30085742ef216b9f2e19308e123d2b)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Update APBH-DMA driver and head files with definitions for CONFIG_MX7
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 07299056426f1f25aab51ab5531c4846d4c7560f)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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