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* sunxi: dram: Add 'await_bits_clear'/'await_bits_set' helper functionsSiarhei Siamashka2014-08-12-6/+22
| | | | | | | | | | | | The old 'await_completion' function is not sufficient, because in some cases we want to wait for bits to be cleared, and in the other cases we want to wait for bits to be set. So split the 'await_completion' into two new 'await_bits_clear' and 'await_bits_set' functions. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: dram: Do DDR3 reset in the same way on sun4i/sun5i/sun7iSiarhei Siamashka2014-08-12-11/+0
| | | | | | | | | | | The older differences were likely justified by the need to mitigate the CKE delay timing violations on sun4i/sun5i. The CKE problem is already resolved, so now we can use the sun7i variant of this code everywhere. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: dram: Remove broken impedance and ODT configuration codeSiarhei Siamashka2014-08-12-27/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can safely remove it, because none of the currently supported boards uses these features. The existing implementation had multiple problems: - unnecessary code duplication between sun4i/sun5i/sun7i - ZQ calibration was never initiated explicitly, and could be only triggered by setting the highest bit in the 'zq' parameter in the 'dram_para' struct (this was never actually done for any of the known Allwinner devices). - even if the ZQ calibration could be started, no attempts were made to wait for its completion, or checking whether the default automatically initiated ZQ calibration is still in progress - ODT was only ever enabled on sun4i, but not on sun5i/sun7i Additionally, SDR_IOCR was set to 0x00cc0000 only on sun4i. There are some hints in the Rockchip Linux kernel sources, indicating that these bits are related to the automatic I/O power down feature, which is poorly understood on sunxi hardware at the moment. Avoiding to set these bits on sun4i too does not seem to have any measurable/visible impact. The impedance and ODT configuration code will be re-introdeced in one of the next comits. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: dram: Fix CKE delay handling for sun4i/sun5iSiarhei Siamashka2014-08-12-7/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before driving the CKE pin (Clock Enable) high, the DDR3 spec requires to wait for additional 500 us after the RESET pin is de-asserted. The DRAM controller takes care of this delay by itself, using a configurable counter in the SDR_IDCR register. This works in the same way on sun4i/sun5i/sun7i hardware (even the default register value 0x00c80064 is identical). Except that the counter is ticking a bit slower on sun7i (3 DRAM clock cycles instead of 2), resulting in longer actual delays for the same settings. This patch configures the SDR_IDCR register for all sun4i/sun5i/sun7i SoC variants and not just for sun7i alone. Also an explicit udelay(500) is added immediately after DDR3 reset for extra safety. This is a duplicated functionality. But since we don't have perfect documentation, it may be reasonable to play safe. Half a millisecond boot time increase is not that significant. Boot time can be always optimized later. Preferebly by the people, who have the hardware equipment to check the actual signals on the RESET and CKE lines and verify all the timings. The old code did not configure the SDR_IDCR register for sun4i/sun5i, but performed the DDR3 reset very early for sun4i/sun5i. This resulted in a larger time gap between the DDR3 reset and the DDR3 initialization steps and reduced the chances of CKE delay timing violation to cause real troubles. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: dram: Respect the DDR3 reset timing requirementsSiarhei Siamashka2014-08-12-2/+7
| | | | | | | | | | | | | | The RESET pin needs to be kept low for at least 200 us according to the DDR3 spec. So just do it the right way. This issue did not cause any visible major problems earlier, because the DRAM RESET pin is usually already low after the board reset. And the time gap before reaching the sunxi u-boot DRAM initialization code appeared to be sufficient. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: dram: Remove broken super-standby remnantsSiarhei Siamashka2014-08-12-46/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | If the dram->ppwrsctl (SDR_DPCR) register has the lowest bit set to 1, this means that DRAM is currently in self-refresh mode and retaining the old data. Since we have no idea what to do in this situation yet, just set this register to 0 and initialize DRAM in the same way as on any normal reboot (discarding whatever was stored there). This part of code was apparently used by the Allwinner boot0 bootloader to handle resume from the so-called super-standby mode. But this particular code got somehow mangled on the way from the boot0 bootloader to the u-boot-sunxi bootloader and has no chance of doing anything even remotely sane. For example: 1. in the original boot0 code we had "mctl_write_w(SDR_DPCR, 0x16510000)" (write to the register) and in the u-boot it now looks like "setbits_le32(&dram->ppwrsctl, 0x16510000)" (set bits in the register) 2. in the original boot0 code it was issuing three commands "0x12, 0x17, 0x13" (Self-Refresh entry, Self-Refresh exit, Refresh), but in the u-boot they have become "0x12, 0x12, 0x13" (Self-Refresh entry, Self-Refresh entry, Refresh) Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: dram: Remove useless 'dramc_scan_dll_para()' functionSiarhei Siamashka2014-08-12-124/+1
| | | | | | | | | | | | | | | | | | | | The attempt to do DRAM parameters calibration in 'dramc_scan_dll_para()' function by trying different DLL adjustments and using the hardware DQS gate training result as a feedback is a great source of inspiration, but it just can't work properly the way it is implemented now. The fatal problem of this implementation is that the DQS gating window can be successfully found for almost every DLL delay adjustment setup that gets tried. Thus making it unable to see any real difference between 'good' and 'bad' settings. Also this code was supposed to be only activated by setting the highest bit in the 'dram_tpr3' variable of the 'dram_para' struct (per-board dram configuration). But none of the linux-sunxi devices has ever used it for real. Basically, this code is just a dead weight. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* Merge branch 'u-boot-sunxi/master' into 'u-boot-arm/master'Albert ARIBAUD2014-08-09-4/+185
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| * sunxi: HYP/non-sec: add sun7i PSCI backendMarc Zyngier2014-07-31-0/+165
| | | | | | | | | | | | | | | | | | So far, only supporting the CPU_ON method. Other functions can be added later. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Add CONFIG_MACPWR optionHans de Goede2014-07-31-0/+5
| | | | | | | | | | | | | | | | On some boards the ethernet-phy needs to be powered up through a gpio, add support for this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: add defines to control USB Host clocks/resetsRoman Byshko2014-07-31-0/+4
| | | | | | | | | | | | | | | | | | | | | | The commit adds three defines which will be used in the EHCI driver to enable USB clock and assert reset controllers of the corresponding PHYs. Signed-off-by: Roman Byshko <rbyshko@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * ahci: provide sunxi SATA driver using AHCI platform frameworkIan Campbell2014-07-31-4/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This enables the necessary clocks, in AHB0 and in PLL6_CFG. This is done for sun7i only since I don't have access to any other sunxi platforms with sata included. The PHY setup is derived from the Alwinner releases and Linux, but is mostly undocumented. The Allwinner AHCI controller also requires some magic (and, again, undocumented) DMA initialisation when starting a port. This is added under a suitable ifdef. This option is enabled for Cubieboard, Cubieboard2 and Cubietruck based on contents of Linux DTS files, including SATA power pin config taken from the DTS. All build tested, but runtime tested on Cubieboard2 and Cubietruck only. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-08-06-1/+17
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| * | powerpc: mpc85xx watchdog init added to init_funcBoschung, Rainer2014-08-01-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_WATCHDOG is defined the board initialization just performs a WATCHDOG_RESET, an initialization of the watchdog is not done. This has been modified fot the MPC85xx, the board initialization calls its watchdog initialitzation allowing for full watchdog configuration very early in the boot phase. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | mpc85xx: watchdog initialisation addedBoschung, Rainer2014-08-01-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Function to inititialize the cpu watchdog added. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> [York Sun: Add prototype in watchdog.h] Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc: macros for e500mc timer regs addedBoschung, Rainer2014-08-01-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For e500mc cores the watchdog timer period has to be set by means of a 6bit value, that defines the bit of the timebase counter used to signal a watchdog timer exception on its 0 to 1 transition. The macro used to set the watchdog period TCR_WP, was redefined for e500mc to support 6 WP setting. The parameter (x) given to the macro specifies the prescaling factor of the time base clock (fTB): watchdog_period = 1/fTB * 2^x Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | mpc85xx: fix interrupt init to not affect watchdogBoschung, Rainer2014-08-01-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | TCR watchdog bit are overwritten when dec interrupt is enabled. This has been fixed with this patch. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | Merge http://git.denx.de/u-boot-dmTom Rini2014-08-04-0/+14
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| * | | arm: Support pre-relocation malloc()Simon Glass2014-08-04-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | Add support for re-relocation malloc() in arm's start-up code. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | arm: Set up global data before board_init_f()Simon Glass2014-08-04-0/+11
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present arm defines CONFIG_SYS_GENERIC_GLOBAL_DATA, meaning that the global_data pointer is set up in board_init_f(). However it is actually set up before this, it just isn't zeroed. If we zero the global data before calling board_init_f() then we don't need to define CONFIG_SYS_GENERIC_GLOBAL_DATA. Make this change (on arm32 only) to simplify the init process. I don't have the ability to test aarch64 yet. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Tom Rini <trini@ti.com>
* | | mmc: s3c: Add SD driverMarek Vasut2014-08-01-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement SD driver for the S3C24xx family. This implementation is currently only capable of using the PIO transfers, DMA is not supported. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* | | arm: s3c: Unify the S3C24xx SDI structureMarek Vasut2014-08-01-11/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unify the register structure so they can be easily used across all of S3C24xx lineup. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* | | ARM: kirkwood: add mvsdio driverDrEagle2014-08-01-0/+10
|/ / | | | | | | | | | | | | | | | | This patch add Marvell kirkwood MVSDIO/MMC driver and enable it for Sheevaplugs and OpenRD boards. Signed-off-by: Gerald Kerma <drEagle@doukki.net> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* | powerpc: remove redundant CPU definitionMasahiro Yamada2014-07-30-12/+11
| | | | | | | | | | | | | | | | CONFIG_${CPU} is defined by Kconfig. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Stefan Roese <sr@denx.de>
* | kconfig: delete redundant CONFIG_${ARCH} definitionMasahiro Yamada2014-07-30-13/+11
| | | | | | | | | | | | | | CONFIG_${ARCH} is defined by Kconfig. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | kconfig: switch to KconfigMasahiro Yamada2014-07-30-15/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit enables Kconfig. Going forward, we use Kconfig for the board configuration. mkconfig will never be used. Nor will include/config.mk be generated. Kconfig must be adjusted for U-Boot because our situation is a little more complicated than Linux Kernel. We have to generate multiple boot images (Normal, SPL, TPL) from one source tree. Each image needs its own configuration input. Usage: Run "make <board>_defconfig" to do the board configuration. It will create the .config file and additionally spl/.config, tpl/.config if SPL, TPL is enabled, respectively. You can use "make config", "make menuconfig" etc. to create a new .config or modify the existing one. Use "make spl/config", "make spl/menuconfig" etc. for spl/.config and do likewise for tpl/.config file. The generic syntax of configuration targets for SPL, TPL is: <target_image>/<config_command> Here, <target_image> is either 'spl' or 'tpl' <config_command> is 'config', 'menuconfig', 'xconfig', etc. When the configuration is done, run "make". (Or "make <board>_defconfig all" will do the configuration and build in one time.) For futher information of how Kconfig works in U-Boot, please read the comment block of scripts/multiconfig.py. By the way, there is another item worth remarking here: coexistence of Kconfig and board herder files. Prior to Kconfig, we used C headers to define a set of configs. We expect a very long term to migrate from C headers to Kconfig. Two different infractructure must coexist in the interim. In our former configuration scheme, include/autoconf.mk was generated for use in makefiles. It is still generated under include/, spl/include/, tpl/include/ directory for the Normal, SPL, TPL image, respectively. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* | kconfig: add basic Kconfig filesMasahiro Yamada2014-07-30-0/+66
| | | | | | | | | | | | | | This commit adds more Kconfig files, which were written by hand. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* | kconfig: add board Kconfig and defconfig filesMasahiro Yamada2014-07-30-0/+2883
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds: - arch/${ARCH}/Kconfig provide a menu to select target boards - board/${VENDOR}/${BOARD}/Kconfig or board/${BOARD}/Kconfig set CONFIG macros to the appropriate values for each board - configs/${TARGET_BOARD}_defconfig default setting of each board (This commit was automatically generated by a conversion script based on boards.cfg) In Linux Kernel, defconfig files are located under arch/${ARCH}/configs/ directory. It works in Linux Kernel since ARCH is always given from the command line for cross compile. But in U-Boot, ARCH is not given from the command line. Which means we cannot know ARCH until the board configuration is done. That is why all the "*_defconfig" files should be gathered into a single directory ./configs/. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-07-29-692/+3167
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| * | ARM: HYP/non-sec: remove MIDR check to validate CBARMarc Zyngier2014-07-28-17/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Having a form of whitelist to check if we know of a CPU core and and obtain CBAR is a bit silly. It doesn't scale (how about A12, A17, as well as other I don't know about?), and is actually a property of the SoC, not the core. So either it works and everybody is happy, or it doesn't and the u-boot port to this SoC is providing the real address via a configuration option. The result of the above is that this code doesn't need to exist, is thus forcefully removed. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | ARM: HYP/non-sec/PSCI: emit DT nodesMarc Zyngier2014-07-28-2/+112
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Generate the PSCI node in the device tree. Also add a reserve section for the "secure" code that lives in in normal RAM, so that the kernel knows it'd better not trip on it. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | ARM: convert arch_fixup_memory_node to a generic FDT fixup functionMa Haijun2014-07-28-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some architecture needs extra device tree setup. Instead of adding yet another hook, convert arch_fixup_memory_node to be a generic FDT fixup function. [maz: collapsed 3 patches into one, rewrote commit message] Signed-off-by: Ma Haijun <mahaijuns@gmail.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | ARM: HYP/non-sec: add the option for a second-stage monitorMarc Zyngier2014-07-28-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow the switch to a second stage secure monitor just before switching to non-secure. This allows a resident piece of firmware to be active once the kernel has been entered (the u-boot monitor is dead anyway, its pages being reused). Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | ARM: HYP/non-sec: add generic ARMv7 PSCI codeMarc Zyngier2014-07-28-0/+141
| | | | | | | | | | | | | | | | | | | | | | | | | | | Implement core support for PSCI. As this is generic code, it doesn't implement anything really useful (all the functions are returning Not Implemented). Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | ARM: HYP/non-sec: allow relocation to secure RAMMarc Zyngier2014-07-28-140/+138
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current non-sec switching code suffers from one major issue: it cannot run in secure RAM, as a large part of u-boot still needs to be run while we're switched to non-secure. This patch reworks the whole HYP/non-secure strategy by: - making sure the secure code is the *last* thing u-boot executes before entering the payload - performing an exception return from secure mode directly into the payload - allowing the code to be dynamically relocated to secure RAM before switching to non-secure. This involves quite a bit of horrible code, specially as u-boot relocation is quite primitive. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | ARM: HYP/non-sec: add separate section for secure codeMarc Zyngier2014-07-28-1/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In anticipation of refactoring the HYP/non-secure code to run from secure RAM, add a new linker section that will contain that code. Nothing is using it just yet. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | ARM: add missing HYP mode constantMarc Zyngier2014-07-28-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to be able to use the various mode constants (far more readable than random hex values), add the missing HYP and A values. Also update arm/lib/interrupts.c to display HYP instead of an unknown value. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | ARM: non-sec: reset CNTVOFF to zeroMarc Zyngier2014-07-28-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before switching to non-secure, make sure that CNTVOFF is set to zero on all CPUs. Otherwise, kernel running in non-secure without HYP enabled (hence using virtual timers) may observe timers that are not synchronized, effectively seeing time going backward... Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | ARM: HYP/non-sec: add a barrier after setting SCR.NS==1Marc Zyngier2014-07-28-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | A CP15 instruction execution can be reordered, requiring an isb to be sure it is executed in program order. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | ARM: HYP/non-sec: move switch to non-sec to the last boot phaseMarc Zyngier2014-07-28-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Having the switch to non-secure in the "prep" phase is causing all kind of troubles, as that stage can be called multiple times. Instead, move the switch to non-secure to the last possible phase, when there is no turning back anymore. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2014-07-28-521/+813
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| | * | ARM: omap: clean redundant PISMO_xx macros used in OMAP3pekon gupta2014-07-25-23/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PISMO_xx macros were used to define 'Platform Independent Storage MOdule' related GPMC configurations. This patch - Replaces these OMAP3 specific macros with generic CONFIG_xx macros as provided by current u-boot infrastructure. - Removes unused redundant macros, which are no longer required after merging of common platform code in following commit commit a0a37183bd75e74608bc78c8d0e2a34454f95a91 ARM: omap: merge GPMC initialization code for all platform +-----------------+-----------------------------------------------------------+ | Macro | Reason for removal | +-----------------+-----------------------------------------------------------+ | PISMO1_NOR_BASE | duplicate of CONFIG_SYS_FLASH_BASE | +-----------------+-----------------------------------------------------------+ | PISMO1_NAND_BASE| duplicate of CONFIG_SYS_NAND_BASE | +-----------------+-----------------------------------------------------------+ | PISMO1_ONEN_BASE| duplicate of CONFIG_SYS_ONENAND_BASE | +-----------------+-----------------------------------------------------------+ | PISMO1_NAND_SIZE| GPMC accesses NAND device via I/O mapped registers so | | | configuring GPMC chip-select for smallest allowable | | | segment (GPMC_SIZE_16M) is enough. | +-----------------+-----------------------------------------------------------+ | PISMO1_ONEN_SIZE| OneNAND uses a fixed GPMC chip-select address-space of | | | 128MB (GPMC_SIZE_128M) | +-----------------+-----------------------------------------------------------+ +-----------------+-----------------------------------------------------------+ | PISMO1_NOR | Unused Macros | | PISMO1_NAND | | | PISMO2_CS0 | | | PISMO2_CS1 | | | PISMO1_ONENAND | | | PISMO2_NAND_CS0 | | | PISMO2_NAND_CS1 | | | PISMO1_NOR_BASE | | | PISMO1_NAND_BASE| | | PISMO2_CS0_BASE | | +-----------------+-----------------------------------------------------------+ Signed-off-by: Pekon Gupta <pekon@ti.com>
| | * | ARM: omap: fix GPMC address-map size for NAND and NOR devicespekon gupta2014-07-25-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes commit a0a37183bd75e74608bc78c8d0e2a34454f95a91 ARM: omap: merge GPMC initialization code for all platform 1) NAND device are not directly memory-mapped to CPU address-space, they are indirectly accessed via following GPMC registers: - GPMC_NAND_COMMAND_x - GPMC_NAND_ADDRESS_x - GPMC_NAND_DATA_x Therefore from CPU's point of view, NAND address-map can be limited to just above register addresses. But GPMC chip-select address-map can be configured in granularity of 16MB only. So this patch uses GPMC_SIZE_16M for all NAND devices. 2) NOR device are directly memory-mapped to CPU address-space, so its address-map size depends on actual addressable region in NOR FLASH device. So this patch uses CONFIG_SYS_FLASH_SIZE to derive GPMC chip-select address-map size configuration. Signed-off-by: Pekon Gupta <pekon@ti.com>
| | * | ARM: OMAP: Fix handling of errata i727Rajendra Nayak2014-07-25-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The errata is applicable on all OMAP4 (4430 and 4460/4470) and OMAP5 ES 1.0 devices. The current revision check erroneously implements this on all DRA7 varients and with DRA722 device (which has only 1 EMIF instance) infact causes an asynchronous abort and ends up masking it in CPSR, only to be uncovered once the kernel switches to userspace. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| | * | board: k2e-evm: add board supportHao Zhang2014-07-25-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds Keystone2 k2e_evm evaluation board support. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * | ARM: keystone2: spl: add K2E SoC supportKhoronzhuk, Ivan2014-07-25-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Keystone2 K2E SoC has slightly different spl pll settings then K2HK, so correct this. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * | ARM: keystone2: add MSMC cache coherency support for K2E SOCHao Zhang2014-07-25-8/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds Keystone2 K2E SOC specific code to support MSMC cache coherency. Also create header file for msmc to hold its API. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * | ARM: keystone2: clock: add K2E clock supportHao Zhang2014-07-25-5/+202
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds clock definitions and commands to support Keystone2 K2E SOC. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * | ARM: keystone2: add K2E SoC hardware definitionsHao Zhang2014-07-25-44/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds hardware definitions specific to Keystone II K2E device. It has a lot common definitions with k2hk SoC, so move them to common hardware.h. This is preparation patch for adding K2E SoC support. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * | ARM: keystone: clock: move K2HK SoC dependent code in separate fileKhoronzhuk, Ivan2014-07-25-145/+166
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch in general spit SoC type clock dependent code and general clock code. Before adding keystone II Edison k2e SoC which has slightly different dpll set, move k2hk dependent clock code to separate clock-k2hk.c file. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
generated by cgit v1.1 at 2024-10-22 09:30:58 +0000