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* arm bootm: Allow to pass board specified atagsPali Rohár2012-10-30-0/+9
| | | | | | Board can implement function setup_board_tags which is used for adding atags Signed-off-by: Pali Rohár <pali.rohar@gmail.com>
* am33xx: Enable UART{1,2,3,4,5} clocksAndrew Bradford2012-10-25-0/+35
| | | | | | | | If configured to use UART{1,2,3,4,5} such as on the Beaglebone RS232 cape or the am335x_evm daughterboard, enable the required clocks for the UART in use. Signed-off-by: Andrew Bradford <andrew@bradfordembedded.com>
* am33xx/ddr_defs.h: rename DDR2/DDR3 defines to their actual part numbersPeter Korsgaard2012-10-25-32/+32
| | | | | | So other parts can be added. Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
* am33xx: support board specific ddr settingsPeter Korsgaard2012-10-25-104/+15
| | | | | | | | | Move the hardcoded ddr2/ddr3 settings for the ti boards to board code, so other boards can use different types/timings. Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com> [trini: Make apply with rtc32k_enable() in the file] Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: move generic parts of pinmux handling out from board/ti/am335xPeter Korsgaard2012-10-25-0/+295
| | | | | | So they are available for other boards. Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
* am33xx/board: use cpu_mmc_init() for default mmc initializationPeter Korsgaard2012-10-25-2/+2
| | | | | | So platforms can override it with board_mmc_init() if needed. Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
* am33xx: move ti i2c baseboard header handling to board/ti/am335x/Peter Korsgaard2012-10-25-288/+0
| | | | | | | | | The i2c header is specific to ti(-derived) boards, and not generic for all am335x boards. Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com> [trini: Make re-apply with rtc32k_enable() applied] Signed-off-by: Tom Rini <trini@ti.com>
* am33xx/board.c: make wdtimer/uart_base staticPeter Korsgaard2012-10-25-2/+4
| | | | | | Only used here (and uart_base only for SPL). Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
* am33xx: Add SPI SPL as an optionTom Rini2012-10-25-0/+2
| | | | | | | Add the required config.mk logic for this SoC as well as the BOOT_DEVICE define. Finally, enable the options on the am335x_evm. Signed-off-by: Tom Rini <trini@ti.com>
* VIDEO: add macro to set LCD size for DSS driverStefano Babic2012-10-25-0/+1
| | | | | Signed-off-by: Stefano Babic <sbabic@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
* am335x: Enable RTC 32K OSC clockVaibhav Hiremath2012-10-25-1/+45
| | | | | | | | | | | | | | | | | In order to support low power state, you must source kernel system timers to persistent clock, available across suspend/resume. In case of AM335x device, the only source we have is, RTC32K, available in wakeup/always-on domain. Having said that, during validation it has been observed that, RTC clock need couple of seconds delay to stabilize the RTC OSC clock; and such a huge delay is not acceptable in kernel especially during early init and also it will impact quick/fast boot use-cases. So, RTC32k OSC enable dependency has been shifted to SPL/first-bootloader. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Enable DDR3 for DDR3 version of beagleboneJoel A Fernandes2012-10-23-2/+7
| | | | | | | | | DDR3 support is tested and working with beaglebone hardware. Include a check for this board type and configure DDR3. The timings and other configuration match EVM SK. Signed-off-by: Joel A Fernandes <joelagnel@ti.com> Acked-by: Jason Kridner <jdk@ti.com>
* arm: fdt: Relocate fdt along with other dataSimon Glass2012-10-19-0/+22
| | | | | | | | | | | Rather than leave the fdt down next to the code/data, we really should relocate it along with everything else. For CONFIG_OF_EMBED this happens automatically, but for CONFIG_OF_SEPARATE it does not. Add code to copy the fdt and point to the new copy after relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
* dm: Move s3c24xx USB driver to a proper placeMarek Vasut2012-10-18-2240/+0
| | | | | | | | | Signed-off-by: Marek Vasut <marex@denx.de> Cc: David Müller <d.mueller@elsoft.ch> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: U-Boot DM <u-boot-dm@lists.denx.de>
* dm: wdt: arm: Move tnetv107x into drivers/watchdog/Marek Vasut2012-10-18-181/+1
| | | | | | | | Signed-off-by: Marek Vasut <marex@denx.de> Cc: Oliver Brown <obrown@adventnetworks.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: U-Boot DM <u-boot-dm@lists.denx.de>
* Remove lh7a40x cpu and serial driverAlbert ARIBAUD2012-10-16-916/+0
| | | | | | | Since commit 957731ed (ARM: remove broken "lpd7a40x" boards), lh7a40x cpu and serial driver have become unused. Remove them. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* Merge branch 'agust@denx.de-next' of git://git.denx.de/u-boot-stagingTom Rini2012-10-15-0/+3
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| * bootstage: Store boot timings in device treeSimon Glass2012-10-02-0/+3
| | | | | | | | | | | | | | | | Add an option, CONFIG_BOOTSTAGE_FDT to pass boot timings to the kernel in the device tree, if available. To use this, you must have CONFIG_OF_LIBFDT defined. Signed-off-by: Simon Glass <sjg@chromium.org>
* | mx25: Clean up lowlevel_initBenoît Thébaudeau2012-10-15-22/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clean up mx25 lowlevel_init: - Add comments. - Do not use write32 repeatedly with the same value in order not to increase code size. - Make register values configurable. - Use macro parameters with default values instead of literal constants. - Use defined macros instead of duplicating code. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: John Rigby <jcrigby@gmail.com> Cc: Matthias Weisser <weisserm@arcor.de>
* | mx31: Fix PDR0_CSI_PODFBenoît Thébaudeau2012-10-15-2/+4
| | | | | | | | | | | | | | | | | | | | The CSI PODF bit-field used by the previous code for the i.MX31 CCM PDR0 register is actually composed of two bit-fields: one pre-divider and one post-divider. This patch fixes the CCM access macros and the code using them accordingly. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx35: Define MAX and AIPS registersBenoît Thébaudeau2012-10-15-1/+84
| | | | | | | | | | Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx31: Add more CCM access macrosBenoît Thébaudeau2012-10-15-0/+10
| | | | | | | | | | Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx5: Optimize lowlevel_init code sizeBenoît Thébaudeau2012-10-15-53/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Optimize mx5 lowlevel_init.S code size: - Compute values at compile time rather than at runtime where possible. - Assign r4 to hold the zero value rather than setting registers to 0 again and again. - Associate a function to setup_pll rather than expanding its large macro code multiple times. - Allocate constant values in section only if used. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Tested-by: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* | mx25: Fix eSDHC supportBenoît Thébaudeau2012-10-15-9/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MMC driver appropriate for the i.MX25 is fsl_esdhc, which has nothing to do with mxcmmc. Also, each eSDHC instance has a dedicated clock, so gd->sdhc_clk must be set accordingly. This is good for the case only a single SDHC instance is used (initialization made with fsl_esdhc_mmc_init()). A future patch will fix the multi-instance use case (initialization made directly with fsl_esdhc_initialize()). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Eric Bénard <eric@eukrea.com> Cc: Otavio Salvador <otavio@ossystems.com.br>
* | mx25: Define cpu_eth_init() only if neededBenoît Thébaudeau2012-10-15-4/+6
| | | | | | | | | | | | | | | | The FEC is the only SoC Ethernet support available on i.MX25, so define cpu_eth_init() only for it instead of returning a misleading success code. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx25: Clean up clocks APIBenoît Thébaudeau2012-10-15-9/+6
| | | | | | | | | | | | | | | | Use the standard mxc_get_clock() instead of exporting internal functions and using literal constant values. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx25 clocks: Fix MXC_FEC_CLKBenoît Thébaudeau2012-10-15-3/+2
| | | | | | | | | | | | | | | | | | | | mxc_get_clock(MXC_FEC_CLK) should return the IPG clock, not the AHB clock. Also, imx_get_fecclk() was correct but reimplemented the calculation of the IPG clock, so remove the duplicated code. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx25: Define more standard clocksBenoît Thébaudeau2012-10-15-0/+15
| | | | | | | | | | | | | | Define AHB, IPG and CSPI clocks. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx25: Clean up clock calculationsBenoît Thébaudeau2012-10-15-4/+4
| | | | | | | | | | | | | | | | Avoid possible overflow in clock calculations, and do not waste calls to lldiv() to divide simple ulongs. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx25: Fix decode_pllBenoît Thébaudeau2012-10-15-3/+6
| | | | | | | | | | | | | | | | The MFN bit-field of the PLL registers represents a signed value. See the reference manual. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx5/6 clocks: Fix SDHC clocksBenoît Thébaudeau2012-10-15-1/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i.MX5 eSDHC clocks were considered as coming from the IPG clock although they have dedicated clock paths. Also, on i.MX5/6, each SDHC instance has a dedicated clock, so gd->sdhc_clk must be set accordingly. This is good for the case only a single SDHC instance is used (initialization made with fsl_esdhc_mmc_init()). A future patch will fix the multi-instance use case (initialization made directly with fsl_esdhc_initialize()). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Eric Bénard <eric@eukrea.com> Cc: Otavio Salvador <otavio@ossystems.com.br>
* | mx51: Fix I2C clock ID checkBenoît Thébaudeau2012-10-15-1/+5
| | | | | | | | | | | | | | There are only 2 I²C instances on i.MX51, but 3 on i.MX53. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx5 clocks: Fix MXC_FEC_CLKBenoît Thébaudeau2012-10-15-3/+2
| | | | | | | | | | | | | | | | | | The FEC clock does not come from PLL1, but from the IPG clock. The previous code was even inconsistent with itself, returning the IPG clock as expected for imx_get_fecclk(), but the PLL1 clock for mxc_get_clock(MXC_FEC_CLK). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx5 clocks: Simplify imx_get_cspiclk()Benoît Thébaudeau2012-10-15-20/+3
| | | | | | | | | | | | | | | | | | The code handling the dividers was duplicated for each possible input clock, and this function can benefit from the newly introduced get_standard_pll_sel_clk() function instead of duplicating this mux handling code. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx5 clocks: Fix get_uart_clk()Benoît Thébaudeau2012-10-15-12/+24
| | | | | | | | | | | | | | | | | | | | | | | | This function returned 66500000 instead of the correct lp_apm clock frequency if the CCM.CSCMR1.uart_clk_sel mux is set to 3. This patch fixes this issue by introducing the get_standard_pll_sel_clk() function that will be used by future patches to handle identical muxes used by many other clocks. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx5 clocks: Fix get_ipg_per_clk()Benoît Thébaudeau2012-10-15-3/+7
| | | | | | | | | | | | | | | | | | | | | | This fixes the "IPG PERCLK" frequency printed by the clocks command. The issue was that get_ipg_per_clk() used periph_clk instead of lp_apm in the case CCM.CBCMR.perclk_lp_apm_sel is set. It also fixes I²C support. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx5 clocks: Fix get_periph_clk()Benoît Thébaudeau2012-10-15-20/+22
| | | | | | | | | | | | | | | | | | | | In the case periph_clk comes from periph_apm_clk, the latter is selected by the CCM.CBCMR.periph_apm_sel mux, which can source the lp_apm clock from its input ♯2. get_periph_clk() returned 0 instead of the lp_apm clock frequency in this case. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx5 clocks: Fix get_lp_apm()Benoît Thébaudeau2012-10-15-1/+38
| | | | | | | | | | | | | | | | | | | | | | | | If CCM.CCSR.lp_apm is set, the lp_apm clock is not necessarily 32768 Hz x 1024. In that case: - on i.MX51, this clock comes from the output of the FPM, - on i.MX53, this clock comes from the output of PLL4. This patch fixes the code accordingly. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx5 clocks: Add and use CCSR definitionsBenoît Thébaudeau2012-10-15-11/+46
| | | | | | | | | | | | | | This fixes config_pll_clk(), which used 0x20 instead of 0x200 for PLL4_CLOCK. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx51: Fix USB PHY clocksBenoît Thébaudeau2012-10-15-8/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i.MX51 has a single USB PHY clock, while the i.MX53 has two. These 3 clocks have different clock gate control bit-fields. The existing code was correct only for i.MX53, so this patch fixes the i.MX51 use case. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Jana Rapava <fermata7@gmail.com> Cc: Wolfgang Grandegger <wg@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il>
* | mx5: Fix clock gate valuesBenoît Thébaudeau2012-10-15-12/+18
| | | | | | | | | | | | | | | | | | The clock gate values are 2-bit bit-fields. Hence, setting or clearing only one of these bits like what was done is wrong and can lead to unpredictable behavior depending on the original value of these bit-fields. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx5: Use explicit clock gate namesBenoît Thébaudeau2012-10-15-11/+283
| | | | | | | | | | | | | | | | Use clock gate definitions having names showing clearly the gated clock instead of names giving only a register field index. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx5 clocks: CleanupBenoît Thébaudeau2012-10-15-152/+184
| | | | | | | | | | | | | | | | | | | | Clean up the i.MX5 clock driver: - Use readl() and writel() instead of their __raw_ counterparts. - Use the clr/setbits_le32() family of macros rather than expanding code. - Use accessor macros for bit-fields instead of _MASK and _OFFSET. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | mx5/6: Define default SoC input clock frequenciesBenoît Thébaudeau2012-10-15-42/+63
| | | | | | | | | | | | | | | | | | | | | | Define default SoC input clock frequencies for i.MX5/6 in order to get rid of duplicated definitions. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Jason Liu <r64343@freescale.com> Cc: Matt Sealey <matt@genesi-usa.com> Cc: Fabio Estevam <fabio.estevam@freescale.com>
* | imx: Use MXC_I2C_CLK in imx i2c driverMatthias Weisser2012-10-15-0/+8
| | | | | | | | | | | | | | | | i2c didn't work on imx25 due to missing MXC_IPG_PERCLK. Now using MXC_I2C_CLK on all imx systems using i2c. Signed-off-by: Matthias Weisser <weisserm@arcor.de> Acked-by: Stefano Babic <sbabic@denx.de>
* | mx25: add CPU revision 1.2Eric Benard2012-10-15-0/+4
| | | | | | | | | | | | | | | | tested on a MCIMX257CJM4A which now reports : CPU: Freescale i.MX25 rev1.2 at 399 MHz Signed-off-by: Eric Bénard <eric@eukrea.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
* | i.MX6: get rid of redundant struct src_regs (dupe of struct src)Eric Nelson2012-10-15-22/+1
| | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* | i.MX6: define struct iomuxc and IOMUX_GPR2 register bitfieldsEric Nelson2012-10-15-0/+73
| | | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | i.MX6: Add ANATOP_PFD_480 bitfield constantsEric Nelson2012-10-15-0/+24
| | | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | i.MX6: define IOMUX_GPR3 register bitfieldsEric Nelson2012-10-15-0/+48
| | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
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