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* MIPS: Au1x00: Move all Au1x00 specific code to separate subdirectoryDaniel Schwierzeck2011-04-02-2/+69
| | | | | | | | | Au1x00 is a SoC and its specific code should reside in an own SoC subdirectory. Also add -mtune=4kc flag for CPU optimization. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Thomas Lange <thomas@corelatus.se> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
* MIPS: IncaIP: Move all IncaIP specific code to separate subdirectoryDaniel Schwierzeck2011-04-02-2/+70
| | | | | | | | | IncaIP is a SoC and its specific code should reside in an own SoC subdirectory. Also add -mtune=4kc flag for CPU optimization. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Wolfgang Denk <wd@denx.de> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
* MIPS: Optimize the setup of CPU optimization flagsDaniel Schwierzeck2011-04-02-7/+8
| | | | | | | | | | | | | | | | | The current MIPS CPU config.mk code always expects a MIPS 4kc core. This is not appropiate for other CPUs and SoCs. Replace the current MIPSFLAGS code by cc-option macro and use -march=mips32r2 as default optimization level for all MIPS32 CPUs. Note: Since commit f62fb99941c625605aa16a0097b396a5c16d2c88 all toolchains with binutils prior to v2.16 are not working anymore. As agreed with Shinya Kuribayashi the support for those toolchains will be dropped officially with this patch. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Wolfgang Denk <wd@denx.de> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
* MIPS: Move content of arch/mips/cpu to arch/mips/cpu/mips32Daniel Schwierzeck2011-04-02-0/+0
| | | | | | | | | | | | | | | | | All current CPUs and SoCs are based on MIPS32 arch. The complete code resides in the global arch/mips/cpu directory. This is not suitable if other MIPS architectures like MIPS64 or Octeon should be supported in the future. To achieve this the current CPU code is moved to its own mips32 subdirectory. All MIPS32 boards have to use mips32 as config switch in board.cfg. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Thomas Lange <thomas@corelatus.se> Cc: Vlad Lungu <vlad.lungu@windriver.com> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
* MIPS: Purple: Remove Purple supportDaniel Schwierzeck2011-04-02-140/+0
| | | | | | | | The Purple SoC and eval board are not actively maintained since years. This patch removes the support completely as aggreed with Wolfgang Denk. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Wolfgang Denk <wd@denx.de> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
* powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCsPrabhakar Kushwaha2011-03-29-1/+52
| | | | | | | | | | The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Enable various errata on P1022/P1013 SoCsJiang Yutang2011-03-28-0/+6
| | | | | | | | | | Enable workaround for errata ELBC A001, ESDHC 111 & SATA A001 on P1022/P1013 SoCs. Also updated P1022DS config to properly enable CONFIG_FSL_SATA_V2. Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Coding Style cleanup: remove trailing empty linesWolfgang Denk2011-03-27-2/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2011-03-27-141/+406
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| * ARMV7: S5P: Fixed register offset in mmc.hChander Kashyap2011-03-27-4/+6
| | | | | | | | | | | | | | | | | | | | | | The MMC registers are accessed through struct s5p_mmc member variables. MMC controller "control4" register offset is set to 0x8C as per data sheet. The size of struct s5p_mmc is also corrected. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * S5P: timer: replace bss variable by gdMinkyu Kang2011-03-27-15/+12
| | | | | | | | | | | | | | | | | | | | | | | | Use the global data instead of bss variable, replace as follow. count_value -> removed timestamp -> tbl lastdec -> lastinc Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Albert ARIBAUD <albert.aribaud@free.fr>
| * S5P: timer: Use pwm functionsMinkyu Kang2011-03-27-58/+7
| | | | | | | | | | | | Use pwm functions for timer that is PWM timer 4. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * ARM: S5P: pwm driver supportDonghwa Lee2011-03-27-0/+228
| | | | | | | | | | | | | | | | This is common pwm driver of S5P. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * SMDK6400: Disable LED function in start.s on the nand bootingseedshope2011-03-27-0/+2
| | | | | | | | | | | | | | | | | | | | Since nand boot have some limit for the first 4KB, We only disable the LED function to reduce the code space. At the same time, Fix the compile error for LED function undefined in the compile time of nand_spl. Signed-off-by: Zhong Hongbo <bocui107@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * arm: fix incorrect monitor protection region in FLASHPo-Yu Chuang2011-03-27-1/+88
| | | | | | | | | | | | | | | | | | | | | | Monitor protection region in FLASH did not cover .rel.dyn and .dynsym sections, because it uses __bss_start to compute monitor_flash_len. Use _end instead. Add _end to linker scripts for end of u-boot image Add _end_ofs to all the start.S. Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
| * rename _end to __bss_end__Po-Yu Chuang2011-03-27-82/+82
| | | | | | | | | | | | | | Currently, _end is used for end of BSS section. We want _end to mean end of u-boot image, so we rename _end to __bss_end__ first. Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
* | powerpc/mpc8xxx: fix workaround for errata DDR111 and DDR134York Sun2011-03-24-0/+41
| | | | | | | | | | | | | | | | The fix for errata workaround is to avoid covering physical address 0xff000000 to 0xffffffff during the implementation. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/mpc8xxx: disable rcw_en bit for non-DDR3York Sun2011-03-24-0/+2
| | | | | | | | | | | | | | | | rcw_en bit is only available for DDR3 controllers. It is a reserved bit on DDR1 and DDR2 controllers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/mpc8xxx: fix recognition of DIMMs with ECC and Address ParityYork Sun2011-03-24-1/+6
|/ | | | | | | | To recognize DIMMs with ECC capability by testing ECC bit only. Not to be confused by Address Parity bit. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Introduce a new linker flag LDFLAGS_FINALHaiying Wang2011-03-22-5/+5
| | | | | | | | | | | | | | | commit 8aba9dceebb14144e07d19593111ee3a999c37fc Divides variable of linker flags to LDFLAGS-u-boot and LDFLAGS breaks the usage of --gc-section to build nand_spl. We still need linker option --gc-section for every uboot image, not only the main one. LDFLAGS_FINAL passes the --gc-sections to each uboot image. To get the proper linker flags, we use LDFLAGS and LDFLAGS_FINAL to replace PLATFORM_LDFLAGS in the Makefile of each nand_spl board. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-shWolfgang Denk2011-03-21-4/+10
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| * sh: Add KEEP order to start.o sectionNobuhiro Iwamatsu2011-03-16-3/+3
| | | | | | | | | | | | | | | | The start.o section is changed by --gc-section option of ld. Of this using KEEP order, therefore, evade this problem. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: Add handling of CONFIG_SYS_NO_FLASH for board.cNobuhiro Iwamatsu2011-03-16-1/+7
| | | | | | | | | | | | | | | | | | Some board of SH does not have flash memoy. This revises it to initialize Flash when CONFIG_SYS_NO_FLASH is not defined. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | powerpc/85xx: Fix synchronization of timebase on MP bootKumar Gala2011-03-15-0/+9
|/ | | | | | | | | | | There is a small ordering issue in the master core in that we need to make sure the disabling of the timebase in the SoC is visible before we set the value to 0. We can simply just read back the value to synchronizatize the write, before we set TB to 0. Reported-by: Dan Hettena Tested-by: Dan Hettena Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc8[5/6]xx: Ensure POST word does not get resetJohn Schmoller2011-03-13-0/+32
| | | | | | | | | | | | The POST word is stored in a spare register in the PIC on MPC8[5/6]xx processors. When interrupt_init() is called, this register gets reset which resulted in all POST_RAM POSTs not being ran due to the corrupted POST word. To resolve this, store off POST word before the PIC is reset, and restore it after the PIC has been initialized. Signed-off-by: John Schmoller <jschmoller@xes-inc.com> Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Fix plat_mp_up() disabling of BPTR for CoreNet PlatformsEd Swarthout2011-03-05-2/+2
| | | | | | | | Copying directly from ECM/PQ3 is not correct for how CoreNet based platforms handle boot page translation. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registersYork Sun2011-03-05-6/+14
| | | | | | | | | The write recovery time of both registers should match. Since mode register doesn't support cycles of 9,11,13,15, we should use next higher number for both registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ARM: Update mach-typesSandeep Paulraj2011-02-21-15/+1276
| | | | | | | This commit updates the mach-types based on the latest in linus's head Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* arm1136 relocation: Fix calculation of board_init_rFabio Estevam2011-02-21-1/+1
| | | | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* arm1136: Fix NAND bootFabio Estevam2011-02-21-12/+4
| | | | | | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com> Tested-by: Magnus Lilja <lilja.magnus@gmail.com>
* arm: get_sp() should always be compiledPo-Yu Chuang2011-02-21-3/+1
| | | | | | | | | | | | get_sp() was incorrectly excluded if none of CONFIG_SETUP_MEMORY_TAGS CONFIG_CMDLINE_TAG CONFIG_INITRD_TAG CONFIG_SERIAL_TAG CONFIG_REVISION_TAG were defined. Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
* mvmfp: add MFP configuration support for PANTHEONLei Wen2011-02-21-0/+41
| | | | | | | This patch adds the Multiple Function Pin configuration support for Marvell PANTHEON SoCs Signed-off-by: Lei Wen <leiwen@marvell.com>
* ARM: Add Support for Marvell Pantheon Familiy SoCsLei Wen2011-02-21-0/+641
| | | | | | | | | | | | | Pantheon Family processors are highly integrated SoCs based on Sheeva_88SV331x-v5 PJ1 cpu core. Ref: http://www.marvell.com/products/processors/communications/marvell_pantheon_910_920_pb.pdf SoC versions Supported: 1) PANTHEON920 (TD) 2) PANTHEON910 (TTC) Signed-off-by: Lei Wen <leiwen@marvell.com>
* mv: seperate kirkwood and armada from common settingLei Wen2011-02-21-0/+189
| | | | | | | | | | | | | Since there are lots of difference between kirkwood and armada series, it is better to seperate them but still keep the most common file shared by all marvell platform in the mv-common configure file. This patch move the kirkwood only driver definitoin in mv-common to the <soc_name>/config.h. This patch is tested with compilation for armada100 and guruplug. Signed-off-by: Lei Wen <leiwen@marvell.com>
* ARM: fix write*() I/O accessorsWolfgang Denk2011-02-21-3/+3
| | | | | | | | | | | | | | | | | | | Commit 3c0659b "ARM: Avoid compiler optimization for readb, writeb and friends." introduced I/O accessors with memory barriers. Unfortunately the new write*() accessors introduced a bug: The problem is that the argument "v" gets evaluated twice. This breaks code like used here (from "drivers/net/dnet.c"): for (i = 0; i < wrsz; i++) writel(*bufp++, &dnet->regs->TX_DATA_FIFO); Use auxiliary variables to avoid such problems. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Albert Aribaud <albert.aribaud@free.fr> Cc: Alexander Holler <holler@ahsoftware.de> Cc: Dirk Behme <dirk.behme@googlemail.com>
* arm relocation: Fix calculation of board_init_rAlexander Stein2011-02-21-1/+1
| | | | Signed-off-by: Alexander Stein <alexander.stein@informatik.tu-chemnitz.de>
* arm: Tegra2: Add basic NVIDIA Tegra2 SoC supportTom Warren2011-02-21-0/+861
| | | | Signed-off-by: Tom Warren <twarren@nvidia.com>
* microblaze: Fix msr handling in interrupt_handlerMichal Simek2011-02-15-18/+1
| | | | | | | Fix ancient code which worked with MSR in a bad way. Use rtid instruction which enable IRQs and jump. Signed-off-by: Michal Simek <monstr@monstr.eu>
* microblaze: Fix systems with MSR=0Michal Simek2011-02-15-1/+1
| | | | | | | | u-boot BSP generates XILINX_USE_MSR_INSTR macro even for system with MSR=0. That's why explicitly check that MSR=1. Signed-off-by: Michal Simek <monstr@monstr.eu>
* sc520: Release CAR and enable cachingGraeme Russ2011-02-12-5/+11
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* x86: Convert board_init_f to use an init_sequenceGraeme Russ2011-02-12-41/+29
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* x86: Rearrange function calls in board_init_fGraeme Russ2011-02-12-8/+8
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* x86: Split board_init_f() into init_fnc_t compatible functionsGraeme Russ2011-02-12-49/+74
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* x86: Fix incorrect usage of relocation offsetGraeme Russ2011-02-12-6/+6
| | | | | x86 has always used relocation offset in the opposite sense to the ELF standard - Fix this
* x86: Move console initialisation into board_init_fGraeme Russ2011-02-12-3/+12
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* x86: Move test for cold boot into init functionsGraeme Russ2011-02-12-13/+11
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* x86: Move call to dram_init_f into board_init_fGraeme Russ2011-02-12-3/+4
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* x86: Defer setup of final stackGraeme Russ2011-02-12-17/+33
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* sc520: Move RAM sizing code from asm to CGraeme Russ2011-02-12-755/+610
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* x86: Use Cache-As-RAM for initial stackGraeme Russ2011-02-12-21/+115
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