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* powerpc/mpc8548: Add workaround for erratum NMG_DDR120Kumar Gala2011-10-03-0/+25
| | | | | | | | | | | | Erratum NMG_DDR120 (DDR19 in MPC8548 errata document) applies to some early version silicons. The default settings of the DDR IO receiver biasing may not work at cold temperature. When a failure occurs, a DDR input latches an incorrect value. The workaround will set the receiver to an acceptable bias point. Signed-off-by: Gong Chen Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/p4080: Add support for secure boot flowRuchika Gupta2011-10-03-3/+118
| | | | | | | | | | | | | | | | | | | | | | | | | Pre u-boot Flow: 1. User loads the u-boot image in flash 2. PBL/Configuration word is used to create LAW for Flash at 0xc0000000 (Please note that ISBC expects all these addresses, images to be validated, entry point etc within 0 - 3.5G range) 3. ISBC validates the u-boot image, and passes control to u-boot at 0xcffffffc. Changes in u-boot: 1. Temporarily map CONFIG_SYS_MONITOR_BASE to the 1M CONFIG_SYS_PBI_FLASH_WINDOW in AS=1. (The CONFIG_SYS_PBI_FLASH_WINDOW is the address map for the flash created by PBL/configuration word within 0 - 3.5G memory range. The u-boot image at this address has been validated by ISBC code) 2. Remove TLB entries for 0 - 3.5G created by ISBC code 3. Remove the LAW entry for the CONFIG_SYS_PBI_FLASH_WINDOW created by PBL/configuration word after switch to AS = 1 Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com> Acked-by: Wood Scott-B07421 <B07421@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driverYork Sun2011-09-29-17/+234
| | | | | | | | | | | | | | | | | Unified DDR driver is maintained for better performance, robustness and bug fixes. Upgrading to use unified DDR driver for MPC83xx takes advantage of overall improvement. It requires changes for board files to customize platform-dependent parameters. To utilize the unified DDR driver, a board needs to define CONFIG_FSL_DDRx in the header file. No more boards will be accepted without such definition. Note: the workaround for erratum DDR6 for the very old MPC834x Rev 1.0/1.1 and MPC8360 Rev 1.1/1.2 parts is not migrated to unified driver. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Add DDR2 to unified DDR driverYork Sun2011-09-29-17/+235
| | | | | | | | | | | | DDR2 has different ODT table and values. Adding table according to Samsung application note. Fix additive latency calculation to avoid interger underflow. Also converted typedef dynamic_odt_t to struct dynamic_odt. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Fix picos_to_mclk() and get_memory_clk_period_ps()York Sun2011-09-29-15/+11
| | | | | | | Reduce the calculation error to 1ps. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Add SPD EEPROM address for single controller 2 slotsYork Sun2011-09-29-4/+7
| | | | | | | The two slots on the same controller have different addresses. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_enYork Sun2011-09-29-9/+14
| | | | | | | | Check second DIMM slot in case the first one is empty. Honor DQS enable option for SDRAM mode register. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Move DDR RCW overriding to common codeYork Sun2011-09-29-0/+15
| | | | | | | | DDR RCW varies at different speeds. It is common for all platform. Move it out from corenet_ds. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Extend CWL tableYork Sun2011-09-29-2/+16
| | | | | | | Extend CAS write Latency (CWL) table to comply with DDR3 spec Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Cleanup how SVR_MAJ() is defined on MPC8536Kumar Gala2011-09-29-3/+4
| | | | | | | | The MPC8536 seems to use only 3 bits for the major revision field in the SVR rather than the 4 bits used by all other processors. The most significant bit is used as a mfg code on MPC8536. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add networking support to P1023RDSRoy Zang2011-09-29-0/+4
| | | | | | | | | | | | | | | | | The P1023 has two 1G ethernet controllers the first can run in SGMII, RGMII, or RMII. The second can only do SGMII & RGMII. We need to setup a for SoC & board registers based on our various configuration for ethernet to function properly on the board. Removed CONFIG_SYS_FMAN_FW as its not used anywhere. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add support for FMan ethernet in Independent modeKumar Gala2011-09-29-12/+741
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Frame Manager (FMan) on QorIQ SoCs with DPAA (datapath acceleration architecture) is the ethernet contoller block. Normally it is utilized via Queue Manager (Qman) and Buffer Manager (Bman). However for boot usage the FMan supports a mode similar to QE or CPM ethernet collers called Independent mode. Additionally the FMan block supports multiple 1g and 10g interfaces as a single entity in the system rather than each controller being managed uniquely. This means we have to initialize all of Fman regardless of the number of interfaces we utilize. Different SoCs support different combinations of the number of FMan as well as the number of 1g & 10g interfaces support per Fman. We add support for the following SoCs: * P1023 - 1 Fman, 2x1g * P4080 - 2 Fman, each Fman has 4x1g and 1x10g * P204x/P3041/P5020 - 1 Fman, 5x1g, 1x10g Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Dai Haruki <dai.haruki@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mp: add support for discontiguous coresTimur Tabi2011-09-29-26/+61
| | | | | | | | | | Some SOCs have discontiguously-numbered cores, and so we can't determine the valid core numbers via the FRR register any more. We define CPU_TYPE_ENTRY_MASK to specify a discontiguous core mask, and helper functions to process the mask and enumerate over the set of valid cores. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fdt: Rename fdt_create_phandle to fdt_set_phandleKumar Gala2011-09-29-1/+1
| | | | | | | | The old fdt_create_phandle didn't actually create a phandle it just set one. We'll introduce a new helper that actually does creation. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Gerald Van Baren <vanbaren@cideas.com>
* powerpc/85xx: Fix compile warnings/errors if CONFIG_SYS_DPAA_FMAN isn't setKumar Gala2011-09-29-1/+8
| | | | | | | | Add ifdef protection around fman specific code related to device tree clock setup. If we dont have CONFIG_SYS_DPAA_FMAN defined we shouldn't be executing this code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010)Poonam Aggrwal2011-09-29-0/+95
| | | | | | | | | | | | | | | | | | Issue: Address masking doesn't work properly. When sum of the base address, defined by BA, and memory bank size, defined by AM, exceeds 4GB (0xffff_ffff) then AMASKn[AM] doesn't mask CSPRn[BA] bits. Impact: This will impact booting when we are reprogramming CSPR0(BA) and AMASK0(AMASK) while executing from NOR Flash. Workaround: Re-programming of CSPR(BA) and AMASK is done while not executing from NOR Flash. The code which programs the BA and AMASK is executed from L2-SRAM. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/P1010: Add workaround for erratum P1010-A003549 (related to IFC)Poonam Aggrwal2011-09-29-0/+17
| | | | | | | | | | | | | | | Issue: Peripheral connected to IFC_CS3 may hamper booting from IFC. Impact: Boot from IFC may not be successful if IFC_CS3 is used. Workaround: If IFC_CS3 is used, gate IFC_CS3 while booting from NAND or NOR. Also Software should select IFC_CS3 using PMUXCR[26:27] = 0x01. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_ifc: Add the workaround for erratum IFC-A002769 (enable on P1010)Poonam Aggrwal2011-09-29-0/+10
| | | | | | | | | | | | | | | Issue: The NOR-FCM does not support access to unaligned addresses for 16 bit port size Impact: When 16 bit port size is used, accesses not aligned to 16 bit address boundary will result in incorrect data Workaround: The workaround is to switch to GPCM mode for NOR Flash access. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Expanding the window of CCSRBAR in AS=1 from 4k to 1MPoonam Aggrwal2011-09-29-3/+4
| | | | | | | | | | | For an IFC Erratum (A-003399) we will need to access IFC registers in cpu_init_early_f() so expand the TLB covering CCSR to 1M. Since we need a TLB to cover 1M we move to using TLB1 array for all the early mappings so we can cover various sizes beyond 4k. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* nand: Freescale Integrated Flash Controller NAND supportDipen Dudhat2011-09-29-7/+27
| | | | | | | | | | | | | | | Add NAND support (including spl) on IFC, such as is found on the p1010. Note that using hardware ECC on IFC with small-page NAND (which is what comes on the p1010rdb reference board) means there will be insufficient OOB space for JFFS2, since IFC does not support 1-bit ECC. UBI should work, as it does not use OOB for anything but ECC. When hardware ECC is not enabled in CSOR, software ECC is now used. Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> [scottwood@freescale.com: ECC rework and misc fixes] Signed-off-by: Scott Wood <scottwood@freescale.com>
* powerpc/85xx: relocate CCSR before creating the initial RAM areaTimur Tabi2011-09-29-58/+234
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before main memory (DDR) is initialized, the on-chip L1 cache is used as a memory area for the stack and the global data (gd_t) structure. This is called the initial RAM area, or initram. The L1 cache is locked and the TLBs point to a non-existent address (so that there's no chance it will overlap main memory or any device). The L1 cache is also configured not to write out to memory or the L2 cache, so everything stays in the L1 cache. One of the things we might do while running out of initram is relocate CCSR. On reset, CCSR is typically located at some high 32-bit address, like 0xfe000000, and this may not be the best place for CCSR. For example, on 36-bit systems, CCSR is relocated to 0xffe000000, near the top of 36-bit memory space. On some future Freescale SOCs, the L1 cache will be forced to write to the backing store, so we can no longer have the TLBs point to non-existent address. Instead, we will point the TLBs to an unused area in CCSR. In order for this technique to work, CCSR needs to be relocated before the initram memory is enabled. Unlike the original CCSR relocation code in cpu_init_early_f(), the TLBs we create now for relocating CCSR are deleted after the relocation is finished. cpu_init_early_f() will still need to create a TLB for CCSR (at the new location) for normal U-Boot purposes. This is done to keep the impact to existing U-Boot code minimal and to better isolate the CCSR relocation code. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macrosTimur Tabi2011-09-29-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW macros, which contain the high and low portions of CONFIG_SYS_CCSRBAR_PHYS. This is necessary for the assembly-language code that relocates CCSR, since the assembler does not understand 64-bit constants. CONFIG_SYS_CCSRBAR_PHYS is automatically defined from the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW macros, so it should not be defined in a board header file. Similarly, CONFIG_SYS_CCSRBAR_DEFAULT is defined for each SOC in config_mpc85xx.h, so it should also not be defined in the board header file. CONFIG_SYS_CCSR_DO_NOT_RELOCATE is a "short-cut" macro that guarantees that CONFIG_SYS_CCSRBAR_PHYS is set to the same value as CONFIG_SYS_CCSRBAR_DEFAULT, and so CCSR will not be relocated. Since CONFIG_SYS_CCSRBAR_DEFAULT is locked to a fixed value, multi-stage U-Boot builds (e.g. NAND) are required to relocate CCSR only during the last stage (i.e. the "real" U-Boot). All other stages should define CONFIG_SYS_CCSR_DO_NOT_RELOCATE to ensure that CCSR is not relocated. README is updated with descriptions of all the CONFIG_SYS_CCSRBAR_xxx macros. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Enable internal USB UTMI PHY on p204x/p3041/p50x0Kumar Gala2011-09-29-0/+5
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add ULPI and UTMI USB Phy support for P1010/P1014Ramneek Mehresh2011-09-29-0/+2
| | | | | | | | | | | | | Add UTMI and ULPI PHY support for USB controller on qoriq series of processors with internal UTMI PHY implemented, for example P1010/P1014 - Use both getenv() and hwconfig to get USB phy type till getenv() is depricated - Introduce CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY to specify if soc has internal UTMI phy Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Acked-by: Remy Bohmer <linux@bohmer.net> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc4xx: Flush dcache after DDR2 autocalibration with caches onStefan Roese2011-09-19-0/+7
| | | | | | | | Flush the dcache before removing the TLB with caches enabled. Otherwise this might lead to problems later on, e.g. while booting Linux (as seen on ICON-440SPe). Signed-off-by: Stefan Roese <sr@denx.de>
* Fix incorrect array size of phy settings for 405EXWeirich, Bernhard2011-09-19-1/+1
| | | | | | | | Change bd_t->bi_phy* arrays from 1 to 2 for PPC405EX since 405EX has 2 ethernet interfaces. Signed-off-by: Bernhard Weirich <bernhard.weirich@riedel.net> Signed-off-by: Stefan Roese <sr@denx.de>
* led: remove camel casing of led identifiers globallyJason Kridner2011-09-13-47/+47
| | | | | | | | | | | | | | | Result of running the following command to address Wolfgang's comment about camel case: for file in `find . | grep '\.[chS]$'`; do perl -i -pe 's/(green|yellow|red|blue)_LED_(on|off)/$1_led_$2/g' $file; done Discussion: http://patchwork.ozlabs.org/patch/84988/ Signed-off-by: Jason Kridner <jkridner@beagleboard.org> Signed-off-by: Joel A Fernandes <agnel.joel@gmail.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap4: IO settingsAneesh V2011-09-13-45/+105
| | | | | | | | Tuning some IO settings for better performance and power. And consolidate all such IO settings at one place. Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap4: make SDRAM init work for ES1.0 siliconAneesh V2011-09-13-54/+22
| | | | | | | | | | | | SDRAM init was not working on ES1.0 due to a programming error. A pointer that was passed by value to a function was set in function emif_get_device_details(), but the effect wouldn't be seen in the calling function. The issue came out while testing for ES1.0 because ES1.0 doesn't have any SDRAM chips connected to CS1 Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap: gpio: generic changes after changing APISanjeev Premi2011-09-13-2/+3
| | | | | | | | This patch contains the generic changes required after change to generic API in the previous patch. Signed-off-by: Sanjeev Premi <premi@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap: gpio: Use generic APISanjeev Premi2011-09-13-46/+82
| | | | | | | | | | | | | | | Convert all OMAP specific functions to use the common API definitions in include/asm/gpio.h. In the process, made few additional changes: - Use -EINVAL consistently. -1 was used in many places. - Removed one-liner static functions that were used only once. Replaced the content as necessary. - Combines implementation of functions omap_get_gpio_dataout() and omap_get_gpio_datain(). To do so, new static function _get_gpio_direction() was added. Signed-off-by: Sanjeev Premi <premi@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* ARMV7: OMAP3: Add 37xx ESx revision numbers.Howard D. Gray2011-09-12-1/+22
| | | | | | | | OMAP3: Add 37xx ESx revision numbers. Signed-off-by: Michael Jones <michael.jones@matrix-vision.de> Signed-off-by: Howard D. Gray <howard.gray@matrix-vision.de> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* OMAP: Add function to get state of a GPIO outputJoel A Fernandes2011-09-12-0/+22
| | | | | | | | Read directly from OMAP_GPIO_DATAOUT to get the output state of the GPIO pin Signed-off-by: Joel A Fernandes <agnel.joel@gmail.com> Signed-off-by: Jason Kridner <jkridner@beagleboard.org> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* Minor coding style cleanup.Wolfgang Denk2011-09-11-5/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* tegra2: fix warning: "assert" redefinedWolfgang Denk2011-09-10-8/+0
| | | | | | | | | | | | Commit 21726a7 "Add assert() for debug assertions" caused build warnings for all tegra2 based boards: clock.c:36:1: warning: "assert" redefined In file included from clock.c:29: include/common.h:144:1: warning: this is the location of the previous definition Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Simon Glass <sjg@chromium.org>
* KS8695: move TIMER_ definitions before code useGreg Ungerer2011-09-10-8/+8
| | | | | | | | | | | | | Move the TIMER_ definitions before they are used in KS8695 timer.c code. Fixes: timer.c: In function ‘timer_init’: timer.c:37: error: ‘TIMER_COUNT’ undeclared (first use in this function) timer.c:37: error: (Each undeclared identifier is reported only once timer.c:37: error: for each function it appears in.) timer.c:38: error: ‘TIMER_PULSE’ undeclared (first use in this function) Signed-off-by: Greg Ungerer <greg.ungerer@opengear.com>
* PXA: FIX: Deep-sleep return address in stored in PSPRMarek Vasut2011-09-07-1/+1
| | | | | | FIX for a typo-bug: The address is stored in PSPR, not PSSR. Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
* MX31: fix missing mxc_get_clk() callStefano Babic2011-09-07-0/+2
| | | | | | Add missing case to be used in common MXC code. Signed-off-by: Stefano Babic <sbabic@denx.de>
* omap24xx: fix 'reset_timer_masked' declaration errorWolfgang Denk2011-09-07-11/+9
| | | | | | | | | | | | | Commit 17659d7 "Timer: Remove reset_timer_masked()" introduced a static declaration for reset_timer_masked() which causes build errors: timer.c:45: error: static declaration of 'reset_timer_masked' follows non-static declaration include/asm/u-boot-arm.h:70: error: previous declaration of 'reset_timer_masked' was here Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Graeme Russ <graeme.russ@gmail.com> Cc: Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Sandeep Paulraj <s-paulraj@ti.com>
* ARM: remove broken "impa7" board.Wolfgang Denk2011-09-07-104/+5
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Marius Gröger <mag@sysgo.de>
* ARM: remove broken "ep7312" board.Wolfgang Denk2011-09-07-12/+8
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Marius Gröger <mag@sysgo.de>
* Makefile : fix generation of cpu related asm-offsets.hStefano Babic2011-09-07-12/+2
| | | | | | | | | | | commit 0edf8b5b2fa0d210ebc4d6da0fd1aceeb7e44e47 breaks building on a different directory with the O= parameter. The patch wil fix this issue, generating always asm-offsets.h before the other targets. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Matthias Weisser <weisserm@arcor.de> CC: Wolfgang Denk <wd@denx.de>
* Flush cache after the OS image is loaded into the memory.Diana CRACIUN2011-09-05-14/+6
| | | | | | | | | | | | | | | | Since we are loading an executable image into memory we need flush it out of the cache to possible maintain coherence on CPUs with split instruction and data caches. We do this for other executable image loading command. On PowerPC once we do this we no longer need to explicitly flush the dcache on multi-core systems in the BOOTM_STATE_OS_PREP phase. We now treat the BOOTM_STATE_OS_PREP as a no-op to maintain backwards compatibility with the bootm subcommand. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Diana CRACIUN <Diana.Craciun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of git://git.denx.de/u-boot-coldfireWolfgang Denk2011-09-04-35/+12
|\ | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-coldfire: ColdFire:Clean up the CONFIG_STANDALONE_LOAD_ADDR usage ColdFire:Add mb for 5253 dram initialization ColdFire:Define the DM9000 byteswap for M5253 board. ColdFire:Update the env settings for several boards. ColdFire:disable the NFS define for 52277 board. ColdFire:Update the timer_init since it was unified. ColdFire: Cleanup for partial linking and --gc-sections ColdFire: Update compile flags for each CPUs ColdFire:Fix the configuration broken for some boards.
| * ColdFire:Clean up the CONFIG_STANDALONE_LOAD_ADDR usageJason Jin2011-09-04-2/+1
| | | | | | | | | | | | Remove the additional linker options for CONFIG_STANDALONE_LOAD_ADDR Signed-off-by: Jason Jin <Jason.jin@freescale.com>
| * ColdFire:Add mb for 5253 dram initializationJason Jin2011-09-04-0/+2
| | | | | | | | | | | | | | | | The dram initialization sequence should be in order. This patch add mb for the dram intialization code to make sure the compiler do not disorder the code. Signed-off-by: Jason Jin <Jason.jin@freescale.com>
| * ColdFire:Update the timer_init since it was unified.Jason Jin2011-09-04-4/+7
| | | | | | | | Signed-off-by: Jason Jin <Jason.jin@freescale.com>
| * ColdFire: Cleanup for partial linking and --gc-sectionsJason Jin2011-09-04-0/+2
| | | | | | | | | | | | | | | | Introduce the --gc-sections for ColdFire platform and clean up the corresponding lds file. Signed-off-by: TsiChung Liew <tsicliew@gmail.com> Signed-off-by: Jason Jin <Jason.jin@freescale.com>
| * ColdFire: Update compile flags for each CPUsJason Jin2011-09-04-29/+0
| | | | | | | | | | | | | | Remove compiler version check for gcc 4.1 in config.mk. Signed-off-by: TsiChung Liew <tsicliew@gmail.com> Signed-off-by: Jason Jin <Jason.jin@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2011-09-04-468/+1532
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-arm: (145 commits) beagleboard: enable HUB power on all variants of the BeagleBoard dm3730: enable dpll5 ehci-hcd: Allow cleanups to happen gracefully on a timeout. OMAP3: Add DSS driver for OMAP3 led: Remove state-saving of led for toggle functionality and add toggle option to led command led: Fixed setting of STATUS_LED_BIT1 when led_name is 'all' led: correct off/on locations in structure led: added cmd_led to Makefile BeagleBoard: fix LED 0/1 in driver Corrected LED name match finding avoiding extraneous Usage printouts BeagleBoard: config: updated default configuration BeagleBoard: config: Enabled multibus support for I2C in configuration BeagleBoard: config: add optargs/buddy/camera BeagleBoard: config: increase command-line functionality BeagleBoard: config: make mtest run BeagleBoard: config: enable DSS BeagleBoard: config: enable asix driver and dhcp BeagleBoard: config: enable networking BeagleBoard: config: decrease bootdelay to 2 seconds BeagleBoard: config: use uImage.beagle for tftp BeagleBoard: config: hardcode MAC for onboard SMSC BeagleBoard: config: load kernel from MMC ext, not FAT BeagleBoard: Configure DVI/S-video BeagleBoard: Added userbutton command BeagleBoard: turn off clocks in ehci_stop USB: Remove __attribute__ ((packed)) for struct ehci_hccr and ehci_hcor beagleboard: add support for xM revision C beagle: pass expansionboard name in bootargs OMAP: Remove omapfb.debug=y from Beagle and Overo env settings OMAP3 Beagle Pin Mux initialization glitch fix da850: modifications for Logic PD Rev.3 AM18xx EVM da850: fix the channel number for EMAC teardown init da850: add support for Spectrum Digital AM18xx EVM da850: add support to wake up DSP during board init da850: modify the U-Boot prompt string da850: add NOR boot mode support da8xx: add support for multiple PLL controllers da850: indicate cache usage disable in config file dm365: modify boot prompt from dm365 to dm36x dm365: disable cache usage due to coherency issues dm6446: disable cache usage due to coherency issues OMAP3: Remove legacy mmc driver devkit8000: Use generic MMC driver TI OMAP3 SDP3430: Use generic MMC driver AM3517 CraneBoard: Use generic MMC driver OMAP3: pandora: Use generic MMC driver OMAP3: Zoom2: Use generic MMC driver OMAP3: Zoom1: Use generic MMC driver OMAP3: DIG297: Use generic MMC driver OMAP3: CM-T35: Use generic MMC driver am3517evm: Use generic MMC driver omap3evm: Use generic MMC driver omap3:clock: check cpu_family before enabling clks for IVA & CAM omap3:clock: configure GFX clock to 200MHz for AM/DM37x OMAP3/4: Increase console I/O buffer size PXA: vpac270: Remove re-defined CONFIG_SYS_TEXT_BASE PXA: Fix CSB226, fix monitor length PXA: Fix Lubbock, remove redundant parenthesis armv7: cache: remove flush on un-aligned invalidate armv7: stronger barrier for cache-maintenance operations omap: enable caches at system start-up arm: do not force d-cache enable on all boards ORIGEN: Add MMC SPL support ARMV7: Add support for Samsung ORIGEN board i2c:gpio:s5p: Enable I2C GPIO on the GONI target i2c:gpio:s5p: I2C GPIO Software implementation (via soft_i2c) Tegra2: Use clock and pinmux functions to simplify code Tegra2: Add additional pin multiplexing features Tegra2: Add more clock support Tegra2: Add microsecond timer function ARM: remove broken "at91rm9200dk" board ARM: remove broken "m501sk" board ARM: remove broken "kb9202" board ARM: remove broken "csb637" board ARM: remove broken "cmc_pu2" board ARM: remove broken "at91cap9adk" board ARM: remove broken "voiceblue" board ARM: remove broken "smdk2400" board ARM: remove broken "sbc2410x" board ARM: remove broken "netstar" board ARM: remove broken "mx1fs2" board ARM: remove broken "lpd7a40x" boards ARM: remove broken "edb93xx" boards ARM: remove broken "B2" board ARM: remove broken "armadillo" board ARM: remove broken "assabet" board ARM: versatile: drop warnings IMX: scb9328: drop warnings MX31: imx31_litekit: make use of GPIO framework MX31: mx31ads: make use of GPIO framework MX5: mx51evk: make use of GPIO framework MX35: mx35pdk: make use of GPIO framework MX5: mx53loco: make use of GPIO framework MX5: mx53evk: make use of GPIO framework MX5: vision2: make use of GPIO framework MX5: mx53smd: make use of GPIO framework MX5: mx53ard: make use of GPIO framework MX25: zmx25: make use of GPIO framework MX5: efikamx: make use of GPIO framework MX31: QONG: make use of GPIO framework MX35: make use of GPIO framework for MX35 processor MX5: make use of GPIO framework for MX5 processor MX31: make use of GPIO framework for MX31 processor MX25: make use of GPIO framework for MX25 processor IMX: uniform GPIO interface using GPIO framework MX: MX35 / MX5: uniform clock command with powerpc MX35: MX35PDK: support additional RAM on CSD1 mx53: ddr3: Update DD3 initialization ARM: MX51: PLL errata workaround ARM: versatilepb : drop warnings due to double definitions omap4: increase SRAM budget to fix build error omap4: fix build warning due to signed unsigned comparison mkimage: Fix 'Unknown OMAP image type - 5' omap: fix gpio related build breaks gpio:samsung: s5p_ suffix add for GPIO functions (C210_universal) SMDKV310: MMC SPL: Remove unwanted dummy functions SMDKV310: Fix undefined reference error SMDKV310: Fix build error for smdkv310 board gpio:samsung s5p_ suffix add for GPIO functions mmc: S5P: Support DMA restarts at buffer boundaries SMDKV310: Fix host compilation of mkv310_image arm: fix bd pointer dereference prior initialization arm, lib/board.c: use gd->ram_size instead of bd->bi_memsize mx5: Remove CONFIG_L2_OFF and CONFIG_SYS_L2CACHE_OFF MX31: removed warnings due to clock.h integrator: convert to new build system integratorcp: make the board compile integratorap: remove hardcoded 32MB memory cmdline ...
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