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* powerpc/85xx: Add P1023RDB board supportChunhe Lan2013-06-20-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | P1023RDB Specification: ----------------------- Memory subsystem: 512MB DDR3 (Fixed DDR on board) 64MB NOR flash 128MB NAND flash Ethernet: eTSEC1: Connected to Atheros AR8035 GETH PHY eTSEC2: Connected to Atheros AR8035 GETH PHY PCIe: Three mini-PCIe slots USB: Two USB2.0 Type A ports I2C: AT24C08 8K Board EEPROM (8 bit address) Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx:Disable Debug TLB entry before init_tlbsPrabhakar Kushwaha2013-06-20-0/+4
| | | | | | | | | init_tlbs() initialize all the TLB entries required for the system. So disable DEBUG TLB entry before TLB entries initialization. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc: mpc85xx/mpc86xx: Fix off-by-one boundary checking with ARRAY_SIZEAxel Lin2013-06-20-25/+25
| | | | | | | | If a variable is used as array subscript, it's valid value range is 0 ... ARRAY_SIZE -1. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: modify the functionality clear_bss and aligning the end ↵Ying Zhang2013-06-20-1/+3
| | | | | | | | | | | | | | | | | | | | address of the BSS There will clear the BSS in the function clear_bss(), the reset address of the BSS started from the __bss_start, and increased by four-byte increments, finally stoped depending on the address is equal to the _bss_end. If the end address __bss_end is not alignment to 4byte, it will be an infinite loop. 1. The reset action stoped depending on the reset address is greater than or equal the end address of the BSS. 2. The end address of the BSS should be 4byte aligned. Because the reset unit is 4 Bytes. This patch is on top of the patch "powerpc/mpc85xx: support application without resetvec segment in the linker script". Signed-off-by: Ying Zhang <b40530@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: support application without resetvec segment in the linker ↵Ying Zhang2013-06-20-0/+22
| | | | | | | | | | | | | | | | script For SD/SPI 2-stage bootloader, the On-Chip Rom code loads the SPL into L2 SRAM, then jump to it to begin execution. After that, the SPL loads the final uboot image into DDR, then jump to it to begin execution. The segment .resetvec in the SPL and in final U-boot is useless. So, add new symbols CONFIG_SYS_MPC85XX_NO_RESETVEC for this application. If CONFIG_SYS_MPC85XX_NO_RESETVEC is set, the segment .resetvec is excluded and the segment .bootpg is placed in the previous 4K of the segment .text. Signed-off-by: Ying Zhang <b40530@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: work around erratum A-006593Scott Wood2013-06-20-0/+8
| | | | | | | | | | | | Erratum A-006593 is "Atomic store may report failure but still allow the store data to be visible". The workaround is: "Set CoreNet Platform Cache register CPCHDBCR0 bit 21 to 1'b1. This may have a small impact on synthetic write bandwidth benchmarks but should have a negligible impact on real code." Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* fsl_ifc: add support for different IFC bank countMingkai Hu2013-06-20-32/+125
| | | | | | | | | | | | Calculate reserved fields according to IFC bank count 1. Move csor_ext register behind csor register and fix res offset 2. Move ifc bank count to config_mpc85xx.h to support 8 bank count 3. Guard fsl_ifc.h with CONFIG_FSL_IFC macro to eliminate the compile error on some devices that does not have IFC controller. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/t4qds: Slave module for boot from SRIO and PCIELiu Gang2013-06-20-0/+1
| | | | | | | | | | | | | | | | | | | | | When a T4 board boots from SRIO or PCIE, it needs to finish these processes: 1. Set all the cores in holdoff status. 2. Set the boot location to one PCIE or SRIO interface by RCW. 3. Set a specific TLB entry for the boot process. 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. 5. Set a specific TLB entry in order to fetch ucode and ENV from master. 6. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 7. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/b4860qds: Slave module for boot from SRIO and PCIELiu Gang2013-06-20-0/+1
| | | | | | | | | | | | | | | | | | | | | | When a b4860qds board boots from SRIO or PCIE, it needs to finish these processes: 1. Set all the cores in holdoff status. 2. Set the boot location to one PCIE or SRIO interface by RCW. 3. Set a specific TLB entry for the boot process. 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. 5. Set a specific TLB entry in order to fetch ucode and ENV from master. 6. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 7. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/boot: Change the macro of Boot from SRIO and PCIE master moduleLiu Gang2013-06-20-7/+3
| | | | | | | | | | | | | | | | | Currently, the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" can enable the master module of Boot from SRIO and PCIE on a platform. But this is not a silicon feature, it's just a specific booting mode based on the SRIO and PCIE interfaces. So it's inappropriate to put the macro into the file arch/powerpc/include/asm/config_mpc85xx.h. Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to "CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros in configuration header file of each board which can support the master module of Boot from SRIO and PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* 85xx: Change case of MPC85XX_PORBMSR_ROMLOC_SHIFTAndy Fleming2013-06-20-1/+1
| | | | | | | All the other constants use lowercase 'x' in "MPC85xx", so we duplicate that here. Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc: Use lower case for the core namesFabio Estevam2013-06-20-5/+5
| | | | | | | | | | | | | | | | | | Freescale documentation presents the PowerPC core names in lower case, such as "e300", "e500", "e600", etc. Change the upper case occurrences into lower case so that the core names reported in U-boot can match the ones from the documentation. While at it also fix a checkpatch error: ERROR: space prohibited before that close parenthesis ')' #53: FILE: arch/powerpc/cpu/mpc86xx/cpu.c:81: + printf("e600 Core %d", (msscr0 & 0x20) ? 1 : 0 ); Reported-by: Heinz Wrobel <heinz.wrobel@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/BSC9132: Add IFC bank countYork Sun2013-06-20-0/+1
| | | | | | | BSC9132 has 3 IFC banks. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* board/bsc9131rdb: Add DSP side tlb and lawsPriyanka Jain2013-06-20-0/+7
| | | | | | | | | | | | | | | BSC9131RDB is a Freescale Reference Design Board for BSC9131 SoC which is a integrated device that contains one powerpc e500v2 core and one DSP starcore. To support DSP starcore -Creating LAW and TLB for DSP-CCSR space. -Creating LAW for DSP-core subsystem M2 memory Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: new SPL support for IFC NANDPrabhakar Kushwaha2013-06-20-1/+1
| | | | | | | | | | | | | | Linker script is not able find start.o binary. So add its absolute path in u-boot-spl.lds. This change is similar to u-boot-nand.lds common/Makefile: Avoid compiling unnecssary files fsl_ifc_spl.c : It is is responsible for reading u-boot binary from NAND flash and copying into DDR. It also transfer control from NAND SPL to u-boot image present in DDR. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx:No NOR boot, do not compile IFC errata A003399Prabhakar Kushwaha2013-06-20-4/+4
| | | | | | | | IFC errata A003399 is valid for IFC NOR boot i.e.if no on-board NOR flash or no NOR boot, do not compile its workaround. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: explicit cast the SDRAM size to type phys_size_tMingkai Hu2013-06-20-1/+1
| | | | | | | | | | To avoid sign extension problem, use explicit casting to cast the SDRAM size to type phys_size_t, or else, if the SDRAM size is 2G(0x80000000), it will be extended to 0xffffffff80000000 when phys_size_t is type 'unsigned long long'. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* 85xx: Change clock-frequency compatible to 2.0Andy Fleming2013-06-20-1/+1
| | | | | | | | | Accidentally applied an earlier version of the patch, which set the compatible to "fsl,qoriq-clockgen-2", lacking the final ".0". Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-06-13-1192/+2327
|\ | | | | | | | | | | | | | | | | Small conflict over DRA7XX updates and adding SRAM_SCRATCH_SPACE_ADDR Conflicts: arch/arm/include/asm/arch-omap5/omap.h Signed-off-by: Tom Rini <trini@ti.com>
| * arm: pxa: config option for PXA270 turbo modeSergey Yanovich2013-06-12-1/+1
| | | | | | | | | | | | | | | | PXA270 CPU has turbo mode. The mode is 2.5 times faster than the default run mode. Activating the mode early significantly speeds up boot process. Signed-off-by: Sergey Yanovich <ynvich@gmail.com>
| * cosmetic: arm: fix comments in arch/arm/lib/crt0.SMasahiro Yamada2013-06-10-2/+2
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * arm: da830: moved pinmux configurations to the arch treeVishwanathrao Badarkhe, Manish2013-06-10-1/+166
| | | | | | | | | | | | | | | | | | | | Move pinmux configurations for the DA830 SoCs from board file to the arch tree so that it can be used for all da830 based devices. Also, avoids duplicate pinmuxing in case of NAND. Signed-off-by: Vishwanathrao Badarkhe, Manish <manishv.b@ti.com> Reviewed-by: Tom Rini <trini@ti.com> Acked-by: Christian Riesch <christian.riesch@omicron.at>
| * OMAP5: Enable access to auxclk registersLubomir Popov2013-06-10-0/+30
| | | | | | | | | | | | | | | | | | | | auxclk0 and auxclk1 are utilized on some OMAP5 boards. Define the infrastructure needed for accessing them without using magic numbers. Also remove unrelated TPS62361 defines from clocks.h Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
| * arm: Remove OMAP2420H4 and all omap24xx supportTom Rini2013-06-10-951/+1
| | | | | | | | | | | | | | | | | | The omap2420H4 was the only mainline omap24xx board. Prior to being fixed by Jon Hunter in time for v2013.04 it had been functionally broken for a very long time. Remove this board as there's not been interest in it in U-Boot for quite a long time. Signed-off-by: Tom Rini <trini@ti.com>
| * ARM: DRA7xx: EMIF: Change settings required for EVM boardSricharan R2013-06-10-31/+220
| | | | | | | | | | | | | | | | | | | | | | DRA7 EVM board has the below configuration. Adding the settings for the same here. 2Gb_1_35V_DDR3L part * 2 on EMIF1 2Gb_1_35V_DDR3L part * 4 on EMIF2 Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * ARM: DRA7xx: clocks: Update PLL valuesLokesh Vutla2013-06-10-46/+71
| | | | | | | | | | | | | | | | | | | | | | Update PLL values. SYS_CLKSEL value for 20MHz is changed to 2. In other platforms SYS_CLKSEL value 2 represents reserved. But in sys_clk array ind 1 is used for 13Mhz. Since other platforms are not using 13Mhz, reusing index 1 for 20MHz. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sricharan R <r.sricharan@ti.com>
| * ARM: DRA7xx: Update pinmux dataLokesh Vutla2013-06-10-2/+5
| | | | | | | | | | | | | | Updating pinmux data as specified in the latest DM Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Balaji T K <balajitk@ti.com>
| * mmc: omap_hsmmc: Update pbias programmingBalaji T K2013-06-10-1/+1
| | | | | | | | | | | | | | Update pbias programming sequence for OMAP5 ES2.0/DRA7 Signed-off-by: Balaji T K <balajitk@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * ARM: DRA7xx: Correct SRAM END addressSricharan R2013-06-10-5/+6
| | | | | | | | | | | | | | | | NON SECURE SRAM is 512KB in DRA7xx devices. So fixing it here. Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * ARM: DRA7xx: Correct the SYS_CLK to 20MHZSricharan R2013-06-10-0/+13
| | | | | | | | | | | | | | | | | | | | The sys_clk on the dra evm board is 20MHZ. Changing the configuration for the same. And also moving V_SCLK, V_OSCK defines to arch/clock.h for OMAP4+ boards. Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * ARM: DRA7xx: Do not enable srcomp for DRA7xx Soc'sLokesh Vutla2013-06-10-0/+11
| | | | | | | | | | | | | | | | Slew rate compensation cells are not present for DRA7xx Soc's. So return from function srcomp_enable() if soc is not OMAP54xx. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * ARM: OMAP5: DRA7xx: support class 0 optimized voltagesNishanth Menon2013-06-10-12/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | DRA752 now uses AVS Class 0 voltages which are voltages in efuse. This means that we can now use the optimized voltages which are stored as mV values in efuse and program PMIC accordingly. This allows us to go with higher OPP as needed in the system without the need for implementing complex AVS logic. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * ARM: DRA7xx: clocks: Fixing i2c_init for PMICLokesh Vutla2013-06-10-2/+1
| | | | | | | | | | | | | | | | In DRA7xx Soc's voltage scaling is done using GPI2C. So i2c_init should happen before scaling. I2C driver uses __udelay which needs timer to be initialized. So moving timer_init just before voltage scaling. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * ARM: DRA7xx: power Add support for tps659038 PMICLokesh Vutla2013-06-10-1/+80
| | | | | | | | | | | | | | | | TPS659038 is the power IC used in DRA7XX boards. Adding support for this and also adding pmic data for DRA7XX boards. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * ARM: DRA7xx: Add control id code for DRA7xxLokesh Vutla2013-06-10-2/+9
| | | | | | | | | | | | | | | | The registers that are used for device identification are changed from OMAP5 to DRA7xx. Using the correct registers for DRA7xx. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * ARM: OMAP4+: pmic: Make generic bus init and write functionsLokesh Vutla2013-06-10-8/+33
| | | | | | | | | | | | | | | | | | | | Voltage scaling can be done in two ways: -> Using SR I2C -> Using GP I2C In order to support both, have a function pointer in pmic_data so that we can call as per our requirement. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * ARM: OMAP2+: Rename asm/arch/clocks.h asm/arch/clock.hLokesh Vutla2013-06-10-9/+9
| | | | | | | | | | | | | | To be consistent with other ARM platforms, renaming asm/arch-omap*/clocks.h to asm/arch-omap*/clock.h Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * ARM: OMAP5: clocks: Do not enable sgx clocksSricharan R2013-06-10-6/+0
| | | | | | | | | | | | | | | | SGX clocks should be enabled only for OMAP5 ES1.0. So this can be removed. Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * ARM: OMAP4+: Cleanup header filesLokesh Vutla2013-06-10-121/+7
| | | | | | | | | | | | | | After having the u-boot clean up series, there are many definitions that are unused in header files. Removing all those unused ones. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * OMAP5: Fix bug in omap5_es1_prcm structLubomir Popov2013-06-10-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The newly introduced function setup_warmreset_time(), called from within prcm_init(), tries to write to the prm_rsttime OMAP5 register. The struct member holding this register's address is however initialized for OMAP5 ES2.0 only. On ES1.0 devices this uninitialized value causes a second (warm) reset at startup. Add .prm_rsttime address init to the ES1.0 struct. Signed-off-by: Lubomir Popov <lpopov@mm-sol.com> Acked-by: Tom Rini <trini@ti.com>
| * OMAP5: add ABB setup for MPU voltage domainAndrii Tseglytskyi2013-06-10-0/+16
| | | | | | | | | | | | | | | | Patch adds a call of abb_setup() function, and proper registers definitions needed for ABB setup sequence. ABB is initialized for MPU voltage domain. Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
| * OMAP3+: introduce generic ABB supportAndrii Tseglytskyi2013-06-10-0/+256
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adaptive Body Biasing (ABB) modulates transistor bias voltages dynamically in order to optimize switching speed versus leakage. Adaptive Body-Bias ldos are present for some voltage domains starting with OMAP3630. There are three modes of operation: * Bypass - the default, it just follows the vdd voltage * Foward Body-Bias - applies voltage bias to increase transistor performance at the cost of power. Used to operate safely at high OPPs. * Reverse Body-Bias - applies voltage bias to decrease leakage and save power. Used to save power at lower OPPs. Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com> Acked-by: Nishanth Menon <nm@ti.com>
| * Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-06-08-4/+1300
| |\ | | | | | | | | | | | | Conflicts: drivers/serial/Makefile
| | * arm: mxs: Fix vectoring table craftingMarek Vasut2013-06-03-3/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The vectoring table has to be placed at 0x0, but U-Boot on MX23/MX28 starts from RAM, so the vectoring table at 0x0 is not present. Craft code that will be placed at 0x0 and will redirect interrupt vectoring to proper location of the U-Boot in RAM. Signed-off-by: Marek Vasut <marex@denx.de> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * arm: vf610: Add Vybrid VF610 CPU supportAlison Wang2013-06-03-0/+1253
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds generic codes to support Freescale's Vybrid VF610 CPU. It aligns Vybrid VF610 platform with i.MX platform. As there are some differences between VF610 and i.MX platforms, the specific codes are in the arch/arm/cpu/armv7/vf610 directory. Signed-off-by: Alison Wang <b18965@freescale.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| | * arm: vf610: Add IOMUX support for Vybrid VF610Alison Wang2013-06-03-1/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the IOMUX support for Vybrid VF610 platform. There is a little difference for IOMUXC module between VF610 and i.MX platform, the muxmode and pad configuration share one 32bit register on VF610, but they are two independent registers on I.MX platform. A CONFIG_IOMUX_SHARE_CONFIG_REG was introduced to fit this difference. Signed-off-by: Alison Wang <b18965@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * | ARM: tegra: only enable SCU on Tegra20Tom Warren2013-06-06-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The non-SPL build of U-Boot on Tegra only runs on a single CPU, and hence there is no need to enable the SCU when running U-Boot. If an SMP OS is booted, and it needs the SCU enabled, it will enable the SCU itself. U-Boot doing so is redundant. The one exception is Tegra20, where an enabled SCU is required for some aspects of PCIe to work correctly. Some Tegra SoCs contain CPUs without a software-controlled SCU. In this case, attempting to turn it on actively causes problems. This is the case for Tegra114. For example, when running Linux, the first (or at least some very early) user-space process will trigger the following kernel message: Unhandled fault: imprecise external abort (0x406) at 0x00000000 This is typically accompanied by that process receving a fatal signal, and exiting. Since this process is usually pid 1, this causes total system boot failure. Signed-off-by: Tom Warren <twarren@nvidia.com> [swarren, fleshed out description, ported to upstream chipid APIs] Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | powerpc: fix 8xx and 82xx type-punning warnings with GCC 4.7Scott Wood2013-06-11-21/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | C99's strict aliasing rules are insane to use in low-level code such as a bootloader, but as Wolfgang has rejected -fno-strict-aliasing in the past, add a union so that 16-bit accesses can be performed. Compile-tested only. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de>
* | | MIPS: asm/errno.h: switch to asm-generic/errno.hDaniel Schwierzeck2013-06-08-143/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes several warnings like In file included from ./u-boot/include/linux/mtd/mtd.h:13:0, from env_onenand.c:37: ./u-boot/build/vct_platinumavc_onenand_small/include2/asm/errno.h:52:0: warning: "ENOMSG" redefined [enabled by default] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | | MIPS: fix __raw_* IO accessorsGabor Juhos2013-06-08-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The purpose of the __raw* IO accessors is to provide IO access in native-endian order. However in the current MIPS implementation, the 16 and 32 bit variants of the __raw accessors are swapping the values on big-endian systems if the CONFIG_SWAP_IO_SPACE option is enabled. The patch changes the IO accessor macros to fix this broken behaviour. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
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