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* arm: dra7xx: Add board files for DRA7XX socsLokesh Vutla2013-03-11-9/+349
| | | | | | | | | | | | | | Adding new board files for DRA7XX socs. The pad registers layout is changed completely from OMAP5 So introducing the new structure here and also adding the minimal data. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishant Kamat <nskamat@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com> [trini: Adapt omap_mmc_init call for last 2 params] Signed-off-by: Tom Rini <trini@ti.com>
* arm: dra7xx: Add DDR related data for DRA752 ES1.0Lokesh Vutla2013-03-11-6/+42
| | | | | | | | | | DRA752 uses DDR3. Populating the corresponding structures with DDR3 data. Writing into MA registers if only MA is present in that soc. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* arm: dra7xx: Add control module changesLokesh Vutla2013-03-11-2/+85
| | | | | | | | | | Control module register addresses are changed from OMAP5 to DRA7XX socs. So adding the necessary changes for the same. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* arm: dra7xx: clock: Add the dplls dataLokesh Vutla2013-03-11-8/+94
| | | | | | | | | | | | A new DPLL DDR is added in DRA7XX socs. Now clocks to EMIF CD is from DPLL DDR. So DPLL DDR should be locked before initializing RAM. Also adding other dpll data which are different from OMAP5 ES2.0. SYS_CLK running at 20MHz is introduced in DRA7xx socs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* arm: dra7xx: clock: Add the prcm changesLokesh Vutla2013-03-11-8/+252
| | | | | | | | PRCM register addresses are changed from OMAP5 ES2.0 to DRA7XX. So adding the necessary register changes for DRA7XX socs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com>
* ARM: OMAP5: srcomp: enable slew rate compensation cells after powerupLokesh Vutla2013-03-11-1/+152
| | | | | | | | | | | | | | After power-up SRCOMP cells are by-passed by default in OMAP5. Software has to enable these SRCOMP sells. For ES2: All 5 SRCOMP cells needs to be enabled. For ES1: Only 4 SRCOMP cells in core power domain are enabled. The 1 in wkup domain is not enabled because smart i/os of wkup domain work with default compensation code. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com> Cc: Tom Rini <trini@ti.com>
* ARM: OMAP5: Add DDR changes required for OMAP543X ES2.0 SOCsLokesh Vutla2013-03-11-2/+94
| | | | | | | | | | | | | Add pre calculated timing settings of LPDDR2 and DDR3 memories present in OMAP5430 and OMAP5432 ES2.0 versions. Also adding the DDR pad io settings required for OMAP543X SOCs here. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com> Cc: Tom Rini <trini@ti.com>
* ARM: OMAP4/5: clocks: Add the required OPP settings as per the latest addendumSRICHARAN R2013-03-11-189/+254
| | | | | | | | | | | | | | | | | Change OPP settings as per the latest 0.5 version of addendum for OMAP5430 ES2.0. omap4/hw_data.c is touched here to add dummy dividers. While here correcting OPP_NOM mpu, core frequency for OMAP4430 ES2.x Note that OMAP5430 ES1.0 support is still kept alive and would be removed in a cleanup later. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Nishanth Menon <nm@ti.com>
* ARM: OMAP5: clock: Add the prcm register changes required for ES2.0SRICHARAN R2013-03-11-0/+292
| | | | | | | | | | | PRCM register addresses are changed from ES1.0 to ES2.0 due to PER power domain getting moved to CORE power domain. So adding the nessecary register changes for the same. Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com> Cc: Tom Rini <trini@ti.com>
* ARM: OMAP5: Add silicon id support for ES2.0 revision.SRICHARAN R2013-03-11-11/+21
| | | | | | | | | Adding the CPU detection suport for OMAP5430 and OMAP5432 ES2.0 SOCs. Signed-off-by: R Sricharan <r.sricharan@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Nishanth Menon <nm@ti.com>
* ARM: OMAP5: Clean up iosettings codeLokesh Vutla2013-03-11-44/+78
| | | | | | | | | | | There is some code duplication in the ddr io settings code. This is avoided by moving the data to a Soc specific place and letting the code generic. This avoids unnessecary code addition for future socs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* ARM: OMAP4+: Make control module register structure genericLokesh Vutla2013-03-11-191/+259
| | | | | | | | | | | | A seperate omap_sys_ctrl_regs structure is defined for omap4 & 5. If there is any change in control module for any of the ES versions, a new structure needs to be created. In order to remove this dependency, making the register structure generic for all the omap4+ boards. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* ARM: OMAP4+: Cleanup emif specific filesLokesh Vutla2013-03-11-85/+108
| | | | | | | | | | | | Removing the duplicated code in ddr3 initialization. Also creating structure for lpddr2 mode registers to avoid unnessecary revision checks. These change reduces code addition for future Socs. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* ARM: OMAP4+: Clean up the pmic codeSRICHARAN R2013-03-11-260/+198
| | | | | | | | | | The pmic code is duplicated for OMAP 4 and 5. Instead move the data to Soc specific place and share the code. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* ARM: OMAP4+: Cleanup the clocks layerSRICHARAN R2013-03-11-895/+869
| | | | | | | | | | | | | | | Currently there is quite a lot of code which is duplicated in the clocks code for OMAP 4 and 5 Socs. Avoiding this here by moving the clocks data to a SOC specific place and the sharing the common code. This helps in addition of a new Soc with minimal changes. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* ARM: OMAP4+: Change the PRCM structure prototype common for all SocsSRICHARAN R2013-03-11-1205/+1312
| | | | | | | | | | | | The current PRCM structure prototype directly matches the hardware register layout. So there is a need to change this for every new silicon revision which has register space changes. Avoiding this by making the prototye generic and populating the register addresses seperately for all Socs. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: OMAP4+: emif: Detect SDRAM from SDRAM config registerLokesh Vutla2013-03-11-7/+28
| | | | | | | | | | | Now SDRAM initialization is done on the basis of omap revision. Instead this should be done on basis of SDRAM type read from EMIF_SDRAM_CONFIG register. This will be helpful to avoid unnessecary cpu checks for new boards Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* Allow AM33xx boards to setup GPMC chipselects.Mark Jackson2013-03-11-0/+2
| | | | | | | | | | | | | | | | Expose the enable_gpmc_cs_config() function so AM33xx based boards can register GPMC chip selects. Changes in V4: - Fix checkpatch errors (TAB -> space mangling) Changes in V3: - Fix line wrapping Changes in V2: - Indicate this is for AM33xx (not OMAP2) Signed-off-by: Mark Jackson <mpfj@newflow.co.uk> Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
* OMAP3: Initialize gpmc if SPL_ONENAND_SUPPORT is enabled.Enric Balletbo i Serra2013-03-11-1/+1
| | | | | | In order to use SPL boot from OneNAND we should initialize the gpmc. Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
* SPL: ONENAND: Fix some ONENAND related defines.Enric Balletbo i Serra2013-03-08-5/+5
| | | | | | | | Some ONENAND related defines use the term ONE_NAND instead of ONENAND, as the technology name is ONENAND this patch replaces all these defines. Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
* omap3: allow dynamic selection of gfx_formatNikita Kiryanov2013-03-08-0/+1
| | | | | | | | | | | | | | | | | Currently, omap3_dss_panel_config() sets gfx_format to a value that is hardcoded in the code. This forces anyone who wants to use a different gfx_format to make adjustments after calling omap3_dss_panel_config(). This could be avoided if the value of gfx_format were parameterized as input for omap3_dss_panel_config(). Make gfx_format a field in struct panel_config, and update existing structs to set this field to the value that was originally hard coded. Cc: Wolfgang Denk <wd@denx.de> Cc: Jeroen Hofstee <jeroen@myspectrum.nl> Cc: Tom Rini <trini@ti.com> Cc: Anatolij Gustschin <agust@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
* omap3: add useful dss definesNikita Kiryanov2013-03-08-0/+30
| | | | | | | | | | | | Add useful omap3 dss defines for: polarity, TFT data lines, lcd display type, gfx burst size, and gfx format Cc: Anatolij Gustschin <agust@denx.de> Cc: Jeroen Hofstee <jeroen@myspectrum.nl> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
* omap_hsmmc: add driver check for write protectionNikita Kiryanov2013-03-08-7/+8
| | | | | | | | Add check for write protection in omap mmc driver. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il> Reviewed-by: Tom Rini <trini@ti.com>
* omap_hsmmc: implement driver check for card detectionNikita Kiryanov2013-03-08-7/+7
| | | | | | | Implement driver check for card detection. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
* omap: consolidate common mmc definitionsNikita Kiryanov2013-03-08-551/+175
| | | | | | | | | The various mmc_host_def.h files are almost identical. Reduce code duplication by moving the similar definitions to a common header file. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
* am33xx: Update DDR3 EMIF configuration sequenceTom Rini2013-03-08-3/+9
| | | | | | | | | | Based on http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips we need to re-work our sequence in config_sdram slightly to match what the TRM describes as the correct sequence. In our current (incorrect) sequence some edge cases may fail to initalize correctly. Signed-off-by: Tom Rini <trini@ti.com>
* Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2013-02-21-0/+8
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| * am33xx: support for booting via usbethIlya Yanok2013-02-18-0/+4
| | | | | | | | | | | | | | | | This patch adds BOOT_DEVICE define for USB booting and fixes spl_board_init function to call arch_misc_init (this is the place there musb is initialized). Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
| * da8xx: Add the missing pinmux for da830 to the gpio driverTomas Novotny2013-02-18-0/+4
| | | | | | | | | | | | | | | | | | The pinmux was generated from linux/arch/arm/mach-davinci/da830.c as of kernel version 3.7.5. If the driver is used for the da850, then SoC variant must be specified by CONFIG_SOC_DA850. Signed-off-by: Tomas Novotny <tomas@novotny.cz> Cc: Tom Rini <trini@ti.com>
* | Merge 'u-boot-microblaze/mainline/arm' into 'u-boot-arm/master'Albert ARIBAUD2013-02-21-1/+206
|\ \ | |/ |/| | | | | | | | | | | This pulls the three following ZYNQ commits into ARM master: 7dca54f8: xilinx: zynq: Enable DCC and create new zynq_dcc board 59c651f4: arm: zynq: Add SLCR support with system reset 00ed3458: arm: zynq: Add lowlevel initialization to C
| * arm: zynq: Add lowlevel initialization to CMichal Simek2013-02-07-2/+70
| | | | | | | | | | | | | | Do lowlevel initialization directly in C. Zynq do not require to do it in asm. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm: zynq: Add SLCR support with system resetMichal Simek2013-02-07-0/+137
| | | | | | | | | | | | | | | | | | The patch provides slcr base address initialization support and a support to reset the cpu through slcr driver, hence removed the reset_cpu() from board.c. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge branch 'fixes' of git://git.denx.de/u-boot-mipsTom Rini2013-02-15-8/+0
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| * | MIPS: board.c: remove manual relocation of env_name_specDaniel Schwierzeck2013-02-15-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | Remove the manual relocation of env_name_spec. This has been missed in the previous patch series for introducing dynamic relocation on MIPS. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | | x86: Remove unused real mode codeSimon Glass2013-02-14-1794/+0
| | | | | | | | | | | | | | | | | | | | | This code is pretty old and we want to support only 32-bit systems now. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Graeme Russ <graeme.russ@gmail.com>
* | | x86: Rename CONFIG_NO_X86_RESET_VECTOR to CONFIG_X86_RESET_VECTORSimon Glass2013-02-14-3/+3
| | | | | | | | | | | | | | | | | | | | | Invert the polarity of this option to simplify the Makefile logic. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Gabe Black <gabeblack@chromium.org>
* | | x86: Remove sc520 cpuSimon Glass2013-02-14-1591/+0
|/ / | | | | | | | | | | | | | | This x86 CPU variant is no longer required as the boards that use it have been removed. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Graeme Russ <graeme.russ@gmail.com>
* | Merge branch 'next' of git://git.denx.de/u-boot-mipsTom Rini2013-02-12-253/+268
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| * | MIPS: add dynamic relocation supportGabor Juhos2013-02-12-12/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code handles relocation entries with the following relocation types only: mips32: R_MIPS_REL32 mips64: R_MIPS_REL+R_MIPS_64 xburst: R_MIPS_REL32 Other relocation entries are skipped without processing. The code must be extended if other relocation types must be supported. Add -pie to LDFLAGS_FINAL to generate the .rel.dyn fixup table, which will be applied to the relocated image before transferring control to it. The CONFIG_NEEDS_MANUAL_RELOC is not needed after the patch, so remove that as well. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | MIPS: u-boot.lds: add relocation specific sectionsGabor Juhos2013-02-12-1/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This section contain the table needed for dynamic relocation. Also provide symbols for the relocation code to access the table. Discard all sections which are not needed in the final ELF binary and U-Boot image. Section .dynsym cannot be discarded or GNU ld crashes otherwise. This section will be stripped by GNU objcpy in a later patch. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | MIPS: start.S: use symbol __image_copy_end for U-Boot image relocationDaniel Schwierzeck2013-02-12-19/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use the newly introduced symbol __image_copy_end as end address for relocation of U-Boot image. This is needed for dynamic relocation added in later patches. This patch obsoletes the symbols uboot_end and uboot_end_data which are removed. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | MIPS: start.S: optimize BSS initializationDaniel Schwierzeck2013-02-12-28/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Get the start and end address for clearing BSS from the newly introduced symbols __bss_start and __bss_end. After GOT is relocated, those symbols are already pointing to the correct addresses. Also optimize the loop by moving the address incrementation to the delay slot to avoid the initial sub instruction. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | MIPS: board.c: switch to new symbols __bss_end and __image_copy_endDaniel Schwierzeck2013-02-12-2/+3
| | | | | | | | | | | | | | | | | | | | | Use the newly introduced symbols __image_copy_end and __bss_end for setting up the memory area for the relocated U-Boot. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | MIPS: u-boot.lds: introduce symbol __image_copy_endDaniel Schwierzeck2013-02-12-0/+8
| | | | | | | | | | | | | | | | | | | | | This symbol is used in later patches as end address for relocation of the U-Boot image into RAM. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | MIPS: u-boot.lds: merge all BSS sections and introduce symbols __bss_[start|end]Daniel Schwierzeck2013-02-12-5/+18
| | | | | | | | | | | | | | | | | | | | | These symbols are used in later patches for as addresses for clearing the BSS area in the relocated U-Boot image. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | MIPS: compute num_got_entries from .got section's sizeGabor Juhos2013-02-12-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The '__got_start' and '__got_end' symbols are used only in the linker script to compute the value of the 'num_got_entries' symbol. Remove the symbols and use the SIZEOF(.got) command to get the size of the .got section. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| * | MIPS: start.S: unify and simplify reset vector handlingDaniel Schwierzeck2013-02-12-176/+57
| | | | | | | | | | | | | | | | | | Adopt reset vector handling from Yamon. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | MIPS: start.S: remove obsolete 64 bit handling in setup_c0_statusDaniel Schwierzeck2013-02-12-9/+1
| | | | | | | | | | | | Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | MIPS: xburst: fix broken access to global_dataDaniel Schwierzeck2013-02-12-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix access to global_data which is broken since commits: commit 035cbe99cd2fd4adf9d7fd95aeebb5f814e37eb9 Author: Simon Glass <sjg@chromium.org> Date: Thu Dec 13 20:49:08 2012 +0000 mips: Move per_clk and dev_clk to arch_global_data Move these field into arch_global_data and tidy up. The other CONFIG_JZSOC fields are used by various architectures, so just remove the #ifdef bracketing for these. Signed-off-by: Simon Glass <sjg@chromium.org> commit 582601da2f90b1850aa19f7820b1623c79b3dac6 Author: Simon Glass <sjg@chromium.org> Date: Thu Dec 13 20:48:35 2012 +0000 arm: Move lastinc to arch_global_data Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org> commit 66ee69234795c0596f84b25f06b7fbc2e8ed214c Author: Simon Glass <sjg@chromium.org> Date: Thu Dec 13 20:48:34 2012 +0000 arm: Move tbl to arch_global_data Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
* | | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-02-12-1219/+9426
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