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* imx: mx5: lowlevel_init: Simplify codeBenoît Thébaudeau2013-04-12-6/+2
| | | | | | | Don't use several instructions to build constant values. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Stefano Babic <sbabic@denx.de>
* OMAP3/4/5/AM33xx: Correct logic for checking FAT or RAW MMCTom Rini2013-04-08-3/+17
| | | | | | | | | | | | | | | In the case of booting from certain peripherals, such as UART, we must not see what the device descriptor says for RAW or FAT mode because in addition to being nonsensical, it leads to a hang. This is why we have a test currently for the boot mode being within range. The problem however is that on some platforms we get MMC2_2 as the boot mode and not the defined value for MMC2, and in others we get the value for MMC2_2. This is required to fix eMMC booting on omap5_uevm. Tested on am335x_evm (UART, NAND, SD), omap3_beagle (NAND, SD on classic, SD only on xM rev C5) and omap5_uevm (SD, eMMC). Signed-off-by: Tom Rini <trini@ti.com>
* arm: omap4: Fix SDRAM AUTO DETECTIONLokesh Vutla2013-04-08-18/+16
| | | | | | | | | | | | | | Commit "8602114 omap: emif: configure emif only when required" breaks SDRAM_AUTO_DETECTION. The issue is dmm_init() depends on emif_sizes[](SDRAM Auto detection) done in do_sdram_init(). The above commit moves dmm_init() above do_sdram_init() because of which dmm_init() uses uninitialized emif_sizes[]. So instead of using global emif_sizes[], get sdram details locally and calculate emif sizes. Reported-by: Michael Cashwell <mboards@prograde.net> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* OMAP: Fix copy-paste bug that did not enable UART4 clockLubomir Popov2013-04-08-2/+2
| | | | | | | | | | | V2 fixes line wrap issue of the patch itself. UART3 was enabled twice instead of UART4. One more cosmetic change in a comment on EMIF clock. Signed-off-by: Lubomir Popov <lpopov@mm-sol.com> Reviewed-by: R Sricharan <r.sricharan@ti.com>
* omap2420-h4: Fix get_timer() and CONFIG_SYS_HZHunter, Jon2013-04-08-2/+6
| | | | | | | The function get_timer() should return time in ms and CONFIG_SYS_HZ should be set to 1000 by default. Fix both of these items. Signed-off-by: Jon Hunter <jon-hunter@ti.com>
* omap2420-h4: Fix booting from NOR flashHunter, Jon2013-04-08-3/+3
| | | | | | | | | | | | | | | | The omap2420-h4 board is using a RAM based address as the linker location for code. This is causing several problems when attempting to run the latest u-boot code base on this board from flash. Update the default linker location for code to be in NOR flash. Please note that OMAP maps the NOR flash to address 0x08000000 by default and so use this as the default address for the NOR flash. Also remove legacy code that attempts to calculate where in flash the sdata structure, that holds the memory interface configuration data, is located. By changing the default linker location for code to flash this is no longer necessary. Signed-off-by: Jon Hunter <jon-hunter@ti.com>
* omap_gpmc: change nandecc commandAndreas Bießmann2013-04-08-10/+25
| | | | | | | | | | | | | With uppcoming BCH support on OMAP devices we need to decide between differnt algorithms when switching the ECC engine. Currently we support 1-bit hammign and 8-bit BCH on HW backend. In order to switch between differnet ECC algorithms we need to change the interface of omap_nand_switch_ecc() also. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Tom Rini <trini@ti.com> Cc: Thomas Weber <thomas.weber.linux@googlemail.com>
* omap3/omap_gpmc.h: add ooblayout for BCH8 as in kernelAndreas Bießmann2013-04-08-0/+17
| | | | | | | | | | | | This patch adds BCH8 ooblayout for NAND as provided by 0e618ef0a6a33cf7ef96c2c824402088dd8ef48c in linux kernel. This Layout is currently only provided for 64 byte OOB. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Tom Rini <trini@ti.com> Cc: Ilya Yanok <ilya.yanok@cogentembedded.com> Cc: Scott Wood <scottwood@freescale.com> Reviewed-by: Tom Rini <trini@ti.com>
* asm/omap_gpmc.h: consolidate common definesAndreas Bießmann2013-04-08-115/+89
| | | | | | | | | | | | | arch/arm/include/asm/arch-am33xx/omap_gpmc.h and arch/arm/include/asm/arch-omap3/omap_gpmc.h are almost the same, consolidate the common parts into a new header. Introduce a new asm/omap_gpmc.h which defines the command part and pulls in the architecture specific one. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Tom Rini <trini@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* omap3/cpu.h: add BCH supportAndreas Bießmann2013-04-08-0/+6
| | | | | | | | | | This patch adds the BCH result registers to register mapping for OMAP3 gpmc. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Tom Rini <trini@ti.com> Cc: Ilya Yanok <ilya.yanok@cogentembedded.com> Cc: Scott Wood <scottwood@freescale.com> Reviewed-by: Tom Rini <trini@ti.com>
* am335x: Enable MMC1 clockTom Rini2013-04-08-0/+5
| | | | | | | | We must not assume ROM has enabled the clock for MMC1. Reported-by: Koen Kooi <koen@dominion.thruhere.net> Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
* Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2013-04-04-110/+296
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| * exynos: change indentation of defines in cpu.hMinkyu Kang2013-04-04-3/+3
| | | | | | | | | | | | Fix the indentation of some defines by tab. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos: pwm: Remove dead code of function exynos5_get_pwm_clkAkshay Saraswat2013-04-01-21/+0
| | | | | | | | | | | | | | | | | | As we shall now be using clock_get_periph_rate function. We find no reason for keeping code in function exynos5_get_pwm_clk. Hence, removing it. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos: pwm: Use generic api to get pwm clk freqPadmavathi Venna2013-04-01-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Use generic api to get the pwm clock frequency Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Build and boot U-boot with this patch, backlight works properly. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos: clock: Add generic api to get the clk freqPadmavathi Venna2013-04-01-0/+159
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add generic api to get the frequency of the required peripherial. This API gets the source clock frequency and returns the required frequency by dividing with first and second dividers based on the requirement. Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Build and boot U-boot with this patch, backlight works properly. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos: Add peripherial id for pwmPadmavathi Venna2013-04-01-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add peripherial id for pwm inorder to support generic api to get the clk frequency Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Build and boot U-boot with this patch, backlight works properly. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos: Tidy up the pwm_config function in the exynos pwm driverGabe Black2013-04-01-16/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some small fixes in the exynos pwm driver: 1. NS_IN_HZ is non-sensical since these are not compatible units. This constant actually describes the number of nanoseconds in a second. Renamed it to NS_IN_SEC. Also dropped the unnecessary parenthesis. 2. The variable "period" is not used to hold a period, it's used to hold a frequency. Renamed it to "frequency". 3. tcmp is an unsigned value, so (tcmp < 0) will never be true and the if which checks that condition will never execute. Also, there should be no problem if the pwm never switches, so there's no reason to subtract one from tcmp and therefore no reason to compare it against zero. Removed both ifs. If they weren't removed, tcmp should be a signed value. 4. Add a check for a 0 period. Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Build and boot U-boot with this patch, backlight works properly. Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos: Avoid a divide by zero by specifying a non-zero period for pwm 4Gabe Black2013-04-01-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pwm_config function in the exynos pwm driver divides by its period period parameter. A function was calling pwm_config with a 0ns period and a 0ns duty cycle. That doesn't actually make any sense physically, and results in a divide by zero in the driver. This change changes the parameters to be a 100000ns period and duty cycle. Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Build and boot U-boot with this patch, backlight works properly. Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos: pwm: Fix two bugs in the exynos pwm configuration codeGabe Black2013-04-01-10/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | First, the "div" value was being used incorrectly to compute the frequency of the PWM timer. The value passed in is a constant which reflects the value that would be found in a configuration register, 0 to 4. That should correspond to a scaling factor of 1, 2, 4, 8, or 16, 1 << div, but div + 1 was being used instead. Second, the reset value of the timers were being calculated to give an overall frequency, thrown out, and set to a maximum value. This was done so that PWM 4 could be used as the system clock by counting down from a high value, but it was applied indiscriminantly. It should at most be applied only to PWM 4. This change also takes the opportunity to tidy up the pwm_init function. Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Build and boot U-boot with this patch, backlight works properly. Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos: Add timer_get_us functionChe-Liang Chiou2013-04-01-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | timer_get_us returns the time in microseconds since a certain reference point of history. However, it does not guarantee to return an accurate time after a long period; instead, it wraps around (that is, the reference point is reset to some other point of history) after some periods. The frequency of wrapping around is about an hour (or 2^32 microseconds). Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos: Change get_timer() to work correctlySimon Glass2013-04-01-62/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present get_timer() does not return sane values. It should count up smoothly in milliscond intervals. We can change the PWM to count down at 1MHz, providing a resolution of 1us and a range of about an hour between required get_timer() calls. Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos: Add hardware accelerated SHA256 and SHA1Akshay Saraswat2013-03-29-0/+4
| | | | | | | | | | | | | | | | SHA-256 and SHA-1 accelerated using ACE hardware. Signed-off-by: ARUN MANKUZHI <arun.m@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
| * EXYNOS5: Add device node for DPAjay Kumar2013-03-27-0/+7
| | | | | | | | | | | | | | Add DT node and bindings documentaion for DP. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * EXYNOS5: Add device node for FIMDAjay Kumar2013-03-27-0/+6
| | | | | | | | | | | | | | Add DT node and bindings documentation for FIMD. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * video: exynos_dp: Remove callbacks from the driverAjay Kumar2013-03-27-1/+0
| | | | | | | | | | | | | | | | | | Replaced the functionality of callbacks by using a standard set of functions. Instead of implementing and hooking up a callback, put the same code in one of the standard set of functions by overriding it. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * EXYNOS5: Add L2 Cache Support.Rajeshwari Shinde2013-03-27-0/+36
| | | | | | | | | | | | | | | | | | This patch set adds L2 Cache Support to EXYNOS. Signed-off-by: Arun Mankuzhi <arun.m@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-04-04-28/+69
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| * | mx6: Fix get_board_rev() for the mx6 solo caseFabio Estevam2013-04-03-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When booting a Freescale kernel 3.0.35 on a Wandboard solo, the get_board_rev() returns 0x62xxx, which is not a value understood by the VPU (Video Processing Unit) library in the kernel and causes the video playback to fail. The expected values for get_board_rev are: 0x63xxx: For mx6quad/dual 0x61xxx: For mx6dual-lite/solo So adjust get_board_rev() accordingly and make it as weak function, so that we do not need to define it in every mx6 board file. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Eric Nelson <eric.nelson@boundarydevices.com>
| * | Add initial support for Wandboard dual lite and solo.Fabio Estevam2013-03-20-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Wandboard is a development board that has two variants: one version based on mx6 dual lite and another one based on mx6 solo. For more details about Wandboard, please refer to: http://www.wandboard.org/ Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | i.MX6: Add hdmidet command to detect attached HDMI monitorEric Nelson2013-03-20-0/+38
| | | | | | | | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * | imx-common: timer: fix 32-bit overflowKnut Wohlrab2013-03-20-19/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i.MX6 common timer uses the 32-bit variable tbl (time base lower) to record the overflow of the 32-bit counter. I.e. if the counter overflows, the variable tbl does overflow, too. To capture this overflow, use the variable tbu (time base upper), too. Return the combined value of tbl and tbu. lastinc is unused then, remove it. Signed-off-by: Knut Wohlrab <knut.wohlrab@de.bosch.com> Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * | mxs: spl_mem_init: Align DDR2 init with FSL bootlets sourceFabio Estevam2013-03-20-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the following kernel hang happens when loading a 2.6.35 kernel from Freeescale on a mx28evk board: RPC: Registered tcp transport module. RPC: Registered tcp NFSv4.1 backchannel transport module. Bus freq driver module loaded IMX usb wakeup probe usb h1 wakeup device is registered mxs_cpu_init: cpufreq init finished ... Loading the same kernel using the bootlets from the imx-bootlets-src-10.12.01 package, the hang does not occur. Comparing the DDR2 initialization from the bootlets code against the U-boot one, we can notice some mismatches, and after applying the same initialization into U-boot the 2.6.35 kernel can boot normally. Also tested with 'mtest' command, which runs succesfully. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br> Tested-by: Marek Vasut <marex@denx.de>
* | | ARM: bcm2835: fix get_timer() to return msStephen Warren2013-04-04-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Apparently, CONFIG_SYS_HZ must be 1000. Change this, and fix the timer driver to conform to this. Have the timer implementation export a custom API get_timer_us() for use by the BCM2835 MMC API, which needs us resolution for a HW workaround. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* | | Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-03-28-572/+2439
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/spi/tegra20_sflash.c include/fdtdec.h lib/fdtdec.c
| * | | armv7: do not relocate _start twiceVincent Stehlé2013-03-28-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The _start symbol is already relocated, so do not add the relocation the second time in c_runtime_cpu_setup. This fixes e.g. the abort exception handling path, which ended in double fault due to bad address in VBAR. Signed-off-by: Vincent Stehlé <v-stehle@ti.com> Reported-by: Lubomir Popov <lpopov@mm-sol.com>
| * | | ARM: mmu: Set domain permissions to client accessR Sricharan2013-03-28-0/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'XN' execute never bit is set in the pagetables. This will prevent speculative prefetches to non executable regions. But the domain permissions are set as master in the DACR register. So the pagetable attribute for 'XN' is not effective. Change the permissions to client. This fixes lot of speculative prefetch aborts seen on OMAP5 secure devices. Signed-off-by: R Sricharan <r.sricharan@ti.com> Tested-by: Vincent Stehle <v-stehle@ti.com> Cc: Vincent Stehle <v-stehle@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
| * | | ARM: mmu: Introduce weak dram_bank_setup functionR Sricharan2013-03-28-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce a weak version of dram_bank_setup function to allow a platform specific function. This is used in the subsequent patch to setup dram region without 'XN' attribute in order to enable the region under client permissions. Signed-off-by: R Sricharan <r.sricharan@ti.com> Cc: Vincent Stehle <v-stehle@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
| * | | ARM: cache: declare set_section_dcacheVincent Stehlé2013-03-28-0/+1
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | We declare the set_section_dcache function globally in the cache header, for later use by e.g. machine specific code. Signed-off-by: Vincent Stehlé <v-stehle <at> ti.com> Cc: Tom Rini <trini <at> ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
| * | Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'Albert ARIBAUD2013-03-26-207/+271
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| | * | Tegra114: Dalmore: Add SDIO3 pad config to pinctrl_config tableTom Warren2013-03-25-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SDIO1 (the SD-card slot on Dalmore) needs to have its pads setup before the MMC driver is added. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * | Tegra114: fdt: Add SDMMC (sdhci) nodes for T114 boards (Dalmore for now)Tom Warren2013-03-25-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Took these values directly from the kernel dts files. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * | tegra114: add SPI driverAllen Martin2013-03-25-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add driver for tegra114 SPI controller. This controller is not compatible with either the tegra20 or tegra30 controllers, so it requires a new driver. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * | tegra114: fdt: add SPI blocksAllen Martin2013-03-25-0/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add nodes for t114 SPI controller hardware Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * | tegra114: fdt: add apbdma blockAllen Martin2013-03-25-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add node for apbdma controller hardware. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * | spi: add common fdt SPI driver interfaceAllen Martin2013-03-25-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a common interface to fdt based SPI drivers. Each driver is represented by a table entry in fdt_spi_drivers[]. If there are multiple SPI drivers in the table, the first driver to return success from spi_init() will be registered as the SPI driver. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * | tegra: spi: pull register structs out of headersAllen Martin2013-03-25-99/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move register structs from headers into .c files and use common name. This is in preparation of making common fdt front end for SPI drivers. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * | tegra: spi: rename tegra SPI driversAllen Martin2013-03-25-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename tegra SPI drivers to tegra20_flash and tegra20_slink in preparation for commonization and addition of tegra114_spi. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * | tegra: remove support for UART SPI switchAllen Martin2013-03-25-48/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This feature was only used for tegra20 seaboard that had a pinmux conflict on the SPI pins. These boards were never manufactured, so remove this support to clean up SPI driver. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * | | Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2013-03-26-1/+134
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generated by cgit v1.1 at 2024-11-08 06:59:56 +0000