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* arm: socfpga: dts: socrates: Add spi1/2 aliases needed DM SPI probingStefan Roese2014-12-06-0/+2
| | | | | | | | | | | | | Without this alias, DM based probing does not work. So lets add this alias to get the bus numbering correct for the Designware SPI controllers. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* arm: socfpga: dts: Add spi0/1 dts nodes for the Designware master SPI devicesStefan Roese2014-12-06-0/+28
| | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* arm: socfpga: dts: Add spi0 alias for Cadence QSPI driverStefan Roese2014-12-06-0/+4
| | | | | | | | | | | | | | Without this alias, DM based probing does not work. So lets add this alias to get the bus numbering correct. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* arm: socfpga: dts: Add Cadence QSPI DT node to socfpga.dtsiStefan Roese2014-12-06-0/+35
| | | | | | | | | | | | | | This DT node is taken from the Rocketboard.org Linux repsitory. And is needed to enable (configure) the Cadence DM SPI driver. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* arm: socfpga: dts: Move to SPDX license identifiersStefan Roese2014-12-06-36/+3
| | | | | | | | | | | | | | | | The socfpga dts files are copied from the Rocketboards.org repository. In U-Boot we usually replace the full-blown license header text with the SPDX license identifiers. Lets do this for these new dts files as well. I just forgot to do this while adding the DT support for socfpga. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com>
* Merge branch 'sandbox' of git://git.denx.de/u-boot-x86Tom Rini2014-12-04-1/+3
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| * sandbox: Fix warnings in cpu.c and os.cSimon Glass2014-11-26-1/+3
| | | | | | | | | | | | | | | | | | | | | | This fixes the following two problems: cppcheck reports: [arch/sandbox/cpu/start.c:132]: (error) Uninitialized variable: err [arch/sandbox/cpu/os.c:371]: (error) Memory leak: fname Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Wolfgang Denk <wd@denx.de>
* | Merge git://git.denx.de/u-boot-x86Tom Rini2014-12-01-116/+4623
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| * | x86: dts: Add video information to the device treeSimon Glass2014-11-25-0/+13
| | | | | | | | | | | | | | | | | | This provides panel timing information needed by the video driver. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Add initial video device init for Intel GMASimon Glass2014-11-25-1/+927
| | | | | | | | | | | | | | | | | | | | | | | | | | | Intel's Graphics Media Accelerator (GMA) is a generic name for a wide range of video devices. Add code to set up the hardware on ivybridge. Part of the init happens in native code, part of it happens in a 16-bit option ROM for those nostalgic for the 1970s. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Add support for running option ROMs nativelySimon Glass2014-11-25-0/+946
| | | | | | | | | | | | | | | | | | | | | | | | On x86 machines we can use an emulator to run option ROMS as with other architectures. But with some additional effort (mostly due to the 16-bit nature of option ROMs) we can run them natively. Add support for this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Add vesa mode configuration optionsSimon Glass2014-11-25-0/+149
| | | | | | | | | | | | | | | | | | Add Kconfig options to allow selection of a vesa mode on x86 machines. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Add GDT descriptors for option ROMsSimon Glass2014-11-25-22/+18
| | | | | | | | | | | | | | | | | | | | | Option ROMs require a few additional descriptors. Add these, and remove the enum since we now have to access several descriptors from assembler. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: ivybridge: Add northbridge init functionsSimon Glass2014-11-25-1/+207
| | | | | | | | | | | | | | | | | | Add init for the northbridge, another part of the platform controller hub. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Drop some msr functions that we don't supportSimon Glass2014-11-25-11/+0
| | | | | | | | | | | | | | | | | | These are not available in U-Boot as yet, so drop them. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Add init for model 206AX CPUSimon Glass2014-11-25-0/+526
| | | | | | | | | | | | | | | | | | Add the setup code for the CPU so that it can be used at full speed. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Add LAPIC setup codeSimon Glass2014-11-25-2/+181
| | | | | | | | | | | | | | | | | | | | | Add code to set up the Local Advanced Peripheral Interrupt Controller. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Drop old CONFIG_INTEL_CORE_ARCH codeSimon Glass2014-11-25-28/+0
| | | | | | | | | | | | | | | | | | | | | This is no-longer used, so drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Refactor interrupt_init()Bin Meng2014-11-25-14/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename interrupt_init() in arch/x86/lib/pcat_interrupts.c to i8259_init() and create a new interrupt_init() in arch/x86/cpu/interrupt.c to call i8259_init() followed by a call to cpu_init_interrupts(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * | x86: Remove cpu_init_r() for x86Bin Meng2014-11-25-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since cpu_init_interrupts() was moved out of cpu_init_r(), it is useless to keep cpu_init_r() for x86, thus remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * | x86: Call cpu_init_interrupts() from interrupt_init()Bin Meng2014-11-25-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently cpu_init_interrupts() is called from cpu_init_r() to setup the interrupt and exception of the cpu core, but at that time the i8259 has not been initialized to mask all the irqs and remap the master i8259 interrupt vector base, so the whole system is at risk of being interrupted, and if interrupted, wrong interrupt/exception message is shown. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * | x86: Add Intel speedstep and turbo mode codeSimon Glass2014-11-25-0/+219
| | | | | | | | | | | | | | | | | | | | | Intel chips have a turbo mode where they can run faster for a short period until they reach thermal limits. Add code to adjust and query this feature. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: ivybridge: Set up XHCI USBSimon Glass2014-11-25-0/+34
| | | | | | | | | | | | | | | | | | Add init for XHCI so that high-speed USB can be used. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: ivybridge: Set up EHCI USBSimon Glass2014-11-25-0/+33
| | | | | | | | | | | | | | | | | | Add init for EHCI so that USB can be used. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: dts: Add SATA settings for linkSimon Glass2014-11-25-0/+7
| | | | | | | | | | | | | | | | | | Add the requires settings to enable SATA on link. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: ivybridge: Add SATA initSimon Glass2014-11-25-0/+306
| | | | | | | | | | | | | | | | | | Add code to set up the SATA interfaces on boot. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: dts: Add LPC settings for linkSimon Glass2014-11-25-0/+8
| | | | | | | | | | | | | | | | | | Add some settings required to set up the LPC correctly. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: dts: Move PCI peripherals into a pci nodeSimon Glass2014-11-25-13/+15
| | | | | | | | | | | | | | | | | | | | | | | | These peripherals should not be at the top level, since they exist inside the PCI bus. We don't have a full device tree node for pci yet, but we should at least put it at the right level. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: ivybridge: Add additional LPC initSimon Glass2014-11-25-1/+528
| | | | | | | | | | | | | | | | | | | | | Set up all the remaining pieces of the LPC (low-pin-count) peripheral in PCH (Peripheral Controller Hub). Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: ivybridge: Add PCH initSimon Glass2014-11-25-0/+173
| | | | | | | | | | | | | | | | | | Add required init for the Intel Platform Controller Hub in ivybridge. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Add a simple header file for ACPISimon Glass2014-11-25-0/+24
| | | | | | | | | | | | | | | | | | | | | We don't use many features yet, so this only has a few declarations. It will be expanded as needed. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: ivybridge: Add support for BD82x6x PCHSimon Glass2014-11-25-0/+167
| | | | | | | | | | | | | | | | | | Add basic setup for the PCH. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Set up edge triggering on interrupt 9Simon Glass2014-11-25-0/+49
| | | | | | | | | | | | | | | | | | | | | Add this additional init in case it is needed by the OS. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: pci: Add handlers before and after a PCI hose scanSimon Glass2014-11-25-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | Some boards will want to do some setup before and after a PCI hose is scanned. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Add ioapic.h headerSimon Glass2014-11-25-0/+38
| | | | | | | | | | | | | | | | | | Add definitions for the I/O Advanced Peripheral Interrupt Controller. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Factor out common values in the link scriptSimon Glass2014-11-25-7/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | Define the reset base in config.mk so that it does not need to be calculated twice in the link script. Also tidy up the START_16 and RESET_VEC_LOC values to fit with this new approach. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Ensure that all relocation data is included in the imageSimon Glass2014-11-25-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some toolchains put the relocation data into separate sections. Adjust the linker script to catch this case. Without relocation data, U-Boot will not boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Panic if there is no relocation dataSimon Glass2014-11-25-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | This normally indicates a problem which will prevent relocation from functioning, resulting in a hang. Panic in this case to make it easier to debug. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Remove board_early_init_r()Simon Glass2014-11-25-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | This function is not needed. Remove it to improve the generic init sequence slightly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Add ivybridge directory to MakefileSimon Glass2014-11-25-0/+2
| | | | | | | | | | | | | | | | | | | | | It is now required to add subdirectories in the x86 cpu Makefile. Add this to fix a build breakage for chromebook_link. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2014-11-27-6/+374
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| * | | ARM: UniPhier: enable Device Tree controlMasahiro Yamada2014-11-28-0/+1
| | | | | | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | usb: UniPhier: support OF configurationMasahiro Yamada2014-11-28-3/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_OF_CONTROL is defined, search device tree nodes that are compatible with "panasonic,uniphier-ehci" and take the base address from their "reg" property. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Marek Vasut <marex@denx.de>
| * | | serial: UniPhier: support OF configurationMasahiro Yamada2014-11-28-0/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit implements the ofdata_to_platdata handler for the UniPhier serial driver and adds serial device nodes to the device tree sources. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | ARM: UniPhier: add device tree sourcesMasahiro Yamada2014-11-28-0/+181
| | | | | | | | | | | | | | | | | | | | | | | | This commit adds basic device tree sources for UniPhier SoCs/boards. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | ARM: UniPhier: add dummy gpio.h to enable CONFIG_OF_CONTROLMasahiro Yamada2014-11-28-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled. It includes <asm/gpio.h> and then <asm/gpio.h> includes <asm/arch/gpio.h>. Consequently, all the SoCs that enable CONFIG_OF_CONTROL must have <asm/arch/gpio.h> even if they do not support GPIO. In the first place, GPIO has nothing to do with OF_CONTROL. It is wrong that lib/fdtdec.c includes GPIO functions; it should be split into two files, FDT-common things and GPIO things. It is, however, a pretty big work to fix that correctly. This is a compromised commit to add a dummy <asm/arch/gpio.h> to support OF_CONTROL for UniPhier platform. This dummy header will be removed after FDT-GPIO stuff is fixed correctly. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | ARM: UniPhier: do not compile platform data when CONFIG_OF_CONTROL=yMasahiro Yamada2014-11-28-3/+3
| | |/ | |/| | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2014-11-27-330/+30
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| * | | MIPS: bootm: remove unused or redundant header filesDaniel Schwierzeck2014-11-27-3/+0
| | | | | | | | | | | | | | | | Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | MIPS: bootm: add missing initramfs relocationDaniel Schwierzeck2014-11-27-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The initramfs is currently only relocated if the user calls the bootm ramdisk subcommand. If bootm should be used without subcommands, the arch-specific bootm code needs to implement the relocation. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
generated by cgit v1.1 at 2024-11-04 18:15:53 +0000