summaryrefslogtreecommitdiff
path: root/arch
Commit message (Collapse)AuthorAgeLines
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-11-26-0/+16
|\ | | | | | | | | | | | | Conflicts: drivers/mmc/fsl_esdhc.c Signed-off-by: Tom Rini <trini@ti.com>
| * net/fm: add 2.5G SGMII supportShengzhou Liu2014-11-19-0/+16
| | | | | | | | | | | | | | | | | | | | As auto-negotiation is not supported for 2.5G SGMII, we need to add a new type PHY_INTERFACE_MODE_SGMII_2500 to differentiate SGMII-1G and SGMII-2.5G with different setting for auto-negotiation. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | Merge branch 'master' of http://git.denx.de/u-boot-samsungTom Rini2014-11-26-20/+286
|\ \
| * | arm: odroid: usb: add support for usb host including ethernetSuriyan Ramasami2014-11-17-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | This change adds support for enabling the USB host features of the board. This includes the USB3503A hub and the SMC LAN9730 ethernet controller as well. Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | arm: odroid: enable/disable usb host phy for exynos4412Suriyan Ramasami2014-11-17-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | Enable/disable the usb host phy on the odroid U/X2 boards which are based on the Exynos4412 SOC. Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | exynos: dts: Correct USB vbus-gpio numbering for SnowSjoerd Simons2014-11-17-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current vbus GPIOs on snow make very little sense, their number is far above the maximum. As a result, USB doesn't work on snow. Correct the GPIO numbering so they match the current scheme for exynos5. Tested both EHCI and XHCI to correctly work after this change. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Peach-Pi: Use the enhanced usb_copy() prototypeVadim Bendebury2014-11-17-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Exynos5800 IROM has a different, from 5250 and 5420, prototype of the usb_copy() function. Luckily the earlier version did not expect any arguments, which means the same code could be used with old and new SoCs, the old ones just ignoring the arguments. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Exynos5: ddr3: Choose between single or double channel configAkshay Saraswat2014-11-17-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a 4G configuration and choose it based on the number of banks declared in config file. A board with 4 SDRAM banks declared (as per CONFIG_NR_DRAM_BANKS) will end up with the 2G confiuration. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | DMC: Exynos5: Enable update mode for DREX controllerAlim Akhtar2014-11-17-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per Exynos5800 UM ver 0.00 section 17.13.2.1 CONCONTROL register bit 3 [update_mode], Exynos5800 does not support the PHY initiated update. And it is recommanded to set this field to 1'b1 during initialization. This patch sets this bit. Applying MC-initiated mode makes DDL tracking ON, that helps in compensate MIF voltage variation. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Config: Exynos5800: Enable build for Peach-PiAkshay Saraswat2014-11-17-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds following things : - New config and defconfig for Peach-Pi board. - Alterations in Kconfig and MAINTAINERS. - Addition of CONFIG_EXYNOS5800. - ADdition of exynos5800-peach-pi in dts list. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Exynos5800: Add DTS for new board Peach-PiAkshay Saraswat2014-11-17-1/+159
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have a new board Peach-Pi similar to Peach-Pit. Peach-Pi differs from Peach-Pit in configuration factors like display resolution, memory size, SoC version etc. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Exynos5800: Introduce new proid for Exynos5800Akshay Saraswat2014-11-17-14/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch intends to add a new proid for Exynos5800 which is a variant of Exynos5420. Product id for Exynos5800 is 0x5422. Both Exynos5420 and Exynos5800 are pin to pin compitable. This gives us an advantage of reusing Exynos5420 clock, pinmux, memory and other settings. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2014-11-26-7/+364
|\ \ \
| * | | sun6i: Drop some "unknown magic" from dram initHans de Goede2014-11-25-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allwinner tells us that this bit of code is the rtc ram being used to detect coming out of "super-standby" mode, and if that is the case, going out of self-refresh mode. Since we do not support "super-standby" mode, this can be dropped. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sun6i: Add gmac support for sun6i boardsHans de Goede2014-11-25-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Hookup the gmac found on the sun6i / A31 SoCs. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sunxi: video: Add simplefb supportLuc Verhaegen2014-11-25-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add simplefb support, note this depends on the kernel having support for the clocks property which has recently been added to the simplefb devicetree binding. Signed-off-by: Luc Verhaegen <libv@skynet.be> [hdegoede@redhat.com: Use pre-populated simplefb node under /chosen as disussed on the devicetree list] Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>.
| * | | sunxi: video: Add cfb console driver for sunxiLuc Verhaegen2014-11-25-0/+185
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a fixed mode hdmi driver for the sunxi platform. The fixed mode is a relatively safe 1024x768, more complete EDID handling is currently not provided. Only HDMI is supported today. This code is enabled when HPD detects an attached monitor. Current config is such that 8MB is shaved off at the top of the RAM. This avoids several memory handling issues, most significant is the fact that on linux on ARM you are not allowed to remap known RAM as IO. A clued in display driver will be able to recycle this reserved RAM in future though. cfbconsole was chosen as it provides the most important functionality: a working u-boot console, allowing for the debugging of certain issues without the need for a UART. Signed-off-by: Luc Verhaegen <libv@skynet.be> [hdegoede@redhat.com: Major cleanups and some small bugfixes] Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Anatolij Gustschin <agust@denx.de> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sunxi: Add video pll clock functionsHans de Goede2014-11-25-1/+161
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a preparation patch for adding support for HDMI out. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sun4i: Rename dram_clk_cfg to dram_clk_gateHans de Goede2014-11-25-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The data sheet just calls it DRAM_CLK_REG, and on sun6i we've both a dram_clk_cfg and dram_clk_gate, and the sun4i reg matches dram_clk_gate on sun6i, so name it the same on sun4i. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | | | Merge git://git.denx.de/u-boot-fdtTom Rini2014-11-26-4/+11
|\ \ \ \ | |/ / / |/| | |
| * | | fdt: Allow ft_board_setup() to report failureSimon Glass2014-11-21-4/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function can fail if the device tree runs out of space. Rather than silently booting with an incomplete device tree, allow the failure to be detected. Unfortunately this involves changing a lot of places in the code. I have not changed behvaiour to return an error where one is not currently returned, to avoid unexpected breakage. Eventually it would be nice to allow boards to register functions to be called to update the device tree. This would avoid all the many functions to do this. However it's not clear yet if this should be done using driver model or with a linker list. This work is left for later. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-11-24-5/+66
|\ \ \ \
| * | | | ARM: bootm: Allow booting in secure mode on hyp capable systemsHans de Goede2014-11-24-5/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Older Linux kernels will not properly boot in hyp mode, add support for a bootm_boot_mode environment variable, which can be set to "sec" or "nonsec" to force booting in secure or non-secure mode when build with non-sec support. The default behavior can be selected through CONFIG_ARMV7_BOOT_SEC_DEFAULT, when this is set booting in secure mode is the default. The default setting for this Kconfig option is N, preserving the current behavior of booting in non-secure mode by default when non-secure mode is supported. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
| * | | | ARM: Add arch/arm/cpu/armv7/Kconfig with non-secure and virt optionsHans de Goede2014-11-24-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add arch/arm/cpu/armv7/Kconfig with non-secure and virt options, this is a preparation patch for adding an env variable to choose between secure / non-secure boot on non-secure boot capable systems, specifically this prepares for adding CONFIG_ARMV7_BOOT_SEC_DEFAULT as a proper Kconfig option. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-11-24-73/+277
|\ \ \ \ \
| * | | | | arm: imx: stop sata on bootNikita Kiryanov2014-11-24-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ideally, the Linux kernel should get the hardware in its most untouched state. For the most part, U-Boot does not reset the various subsystems it touches before boot, and usually Linux deals with it, but on some boards (cm_fx6) the Linux kernel fails to detect the ssd correctly if sata is used by U-Boot. Power off sata on OS boot so that Linux will have a clean state to work with. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de>
| * | | | | sata: implement reset_sata for dwc_ahsataNikita Kiryanov2014-11-24-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add reset_sata() to the sata driver interface and implement it for dwc_ahsata. This function cleans up after sata_init(), and therefore accepts a device number like sata_init() does. A dummy implementation is provided for the rest of the drivers. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de>
| * | | | | arm: mx6: introduce disable_sata_clockNikita Kiryanov2014-11-24-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement disable_sata_clock for mx6 SoCs. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de>
| * | | | | mx6: thermal: Check cpu temperature via thermal sensorYe.Li2014-11-21-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add imx6 thermal device to mx6 soc file. Read the cpu temperature using this device to access onchip thermal sensor. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
| * | | | | mx6: clock: Add thermal clock enable functionNitin Garg2014-11-21-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add api to check and enable pll3 as required for thermal sensor driver. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
| * | | | | mx6: add weim registersFabio Estevam2014-11-20-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | | | imx: consolidate set_chipselect_size functionFabio Estevam2014-11-20-41/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move MX5 specific set_chipselect_size function into generic i.MX part, such that MX6 based boards are able to use this function as well. While doing this the iomuxc gpr member needed to be consolidated between MX5 and MX6. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | | | mx6: Use a common SPL configuration fileFabio Estevam2014-11-20-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many boards use a minimal .cfg file in the SPL case. Introduce spl_sd.cfg so that we can reuse it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * | | | | imx: fix exception vectors relocation in imx27Albert ARIBAUD2014-11-20-28/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 3ff46cc4 fixed exception vectors setting in the general ARM case, by either copying the exception and indirect vector tables to normal (0x00000000) or high (0xFFFF0000) vectors address, or setting VBAR to U-Boot's base if applicable. i.MX27 SoC is ARM926E-JS, thus has only normal and high options, but does not provide RAM at 0xFFFF0000 and has only ROM at 0x00000000; it is therefore not possible to move or change its exception vectors. Besides, i.MX27 ROM code does provide an indirect vectors table but at a non-standard address and with the reset and reserved vectors missing. Turn the current vector relocation code into a weak routine called after relocate_code from crt0, and add strong version for i.MX27. Series-Cc: Heiko Schocher <hs@denx.de> Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: Stefano Babic <sbabic@denx.de> Tested-by: Stefano Babic <sbabic@denx.de> Tested-by: Philippe Reynes <tremyfr@gmail.com> Tested-by: Philippe Reynes <tremyfr@yahoo.fr>
| * | | | | cosmetic: arm: fix whitespace in arch/arm/lib/relocate.SAlbert ARIBAUD2014-11-20-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
| * | | | | ARM: mxs: tools: Add support for boot progress display flagAlexey Ignatov2014-11-20-0/+3
| | |_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mkimage -T mxs now support new flag in config file: DISPLAYPROGRESS - makes boot process print HTLLC characters for each BootROM instruction. Signed-off-by: Alexey Ignatov <lexszero@gmail.com>
* | | | | Merge git://git.denx.de/u-boot-dmTom Rini2014-11-24-2/+46
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/serial/serial-uclass.c Signed-off-by: Tom Rini <trini@ti.com>
| * | | | | dm: arm: spl: Make driver model linker lists availableSimon Glass2014-11-21-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The linker lists feature is useful in SPL as it holds the driver model platform data. So don't throw away the lists. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com>
| * | | | | dm: arm: spl: Allow simple malloc() in SPLSimon Glass2014-11-21-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For SPL it is sometimes useful to have a simple malloc() just to permit driver model to work, in the cases where the full malloc() is not made available by the board config. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | | dm: at91: Add driver model support for the serial driverSimon Glass2014-11-21-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add driver model support while retaining the existing legacy code. This allows the driver to support boards that have converted to driver model as well as those that have not. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | | dm: at91: Add platform data for GPIO on at91sam9260-based boardsSimon Glass2014-11-21-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These boards all have the same GPIO arrangement, so add some common platform data that can be used by all boards. Remove the configs which are no longer required. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | | dm: at91: Add driver model support for atmel GPIO driverSimon Glass2014-11-21-0/+6
| | |_|/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | Modify this driver to support driver model, with platform data required to determine the GPIOs that it controls. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | | Merge git://git.denx.de/u-boot-x86Tom Rini2014-11-24-175/+6391
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/x86/cpu/Makefile Signed-off-by: Tom Rini <trini@ti.com>
| * | | | | x86: Rename chromebook-x86 to corebootSimon Glass2014-11-21-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename this vendor since it is intended to be used on any platform where coreboot runs at reset and then loads U-Boot. So far it is only tested on link. When other boards are supported it is likely that we will need to move to multiple board names, all under the 'coreboot' vendor. So while it would be possible to remove the vendor for now, that would be short-sighted. Suggested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | | x86: ivybridge: Implement SDRAM initSimon Glass2014-11-21-5/+1861
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in the board directory and the SDRAM SPD information in the device tree. This also needs the Intel Management Engine (me.bin) to work. Binary blobs everywhere: so far we have MRC, ME and microcode. SDRAM init works by setting up various parameters and calling the MRC. This in turn does some sort of magic to work out how much memory there is and the timing parameters to use. It also sets up the DRAM controllers. When the MRC returns, we use the information it provides to map out the available memory in U-Boot. U-Boot normally moves itself to the top of RAM. On x86 the RAM is not generally contiguous, and anyway some RAM may be above 4GB which doesn't work in 32-bit mode. So we relocate to the top of the largest block of RAM we can find below 4GB. Memory above 4GB is accessible with special functions (see physmem). It would be possible to build U-Boot in 64-bit mode but this wouldn't necessarily provide any more memory, since the largest block is often below 4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit kernels directly so this does not pose a limitation in that area. Also there are probably parts of U-Boot that will not work correctly in 64-bit mode. The MRC is one. There is some work remaining in this area. Since memory init is very slow (over 500ms) it is possible to save the parameters in SPI flash to speed it up next time. Suspend/resume support is not fully implemented, or at least it is not efficient. With this patch, link boots to a prompt. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | | x86: ivybridge: Add LAPIC supportSimon Glass2014-11-21-0/+163
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The local advanced programmable interrupt controller is not used much in U-Boot but we do need to set it up. Add basic support for this, which will be extended as needed. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | | x86: Make show_boot_progress() commonSimon Glass2014-11-21-24/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function can probably be used on all x86 boards, so move it into the common file. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | | x86: chromebook_link: Enable GPIO supportSimon Glass2014-11-21-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable GPIO support and provide the required GPIO setup information to the driver. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | | x86: ivybridge: Add support for early GPIO initSimon Glass2014-11-21-6/+158
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When not relying on Coreboot for GPIO init the GPIOs must be set up correctly. This is currently done statically through a rather ugly method. As the GPIOs are figured out they can be moved to the device tree and set up as needed rather than all at the start. In this implementation, board files should call ich_gpio_set_gpio_map() before the GPIO driver is used in order to provide the GPIO information. We use the early PCI interface so that this driver can now be used before relocation. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | | x86: ivybridge: Add early init for PCH devicesSimon Glass2014-11-21-1/+524
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many PCH devices are hard-coded to a particular PCI address. Set these up early in case they are needed. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-10-22 13:31:41 +0000