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* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2012-09-21-269/+448
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| * Merge remote-tracking branch 'u-boot-imx/master'Albert ARIBAUD2012-09-21-190/+218
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| | * MX6: drop binary constants from iomux headerStefano Babic2012-09-17-62/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Constants set with binary value (0b...) are not compiled from old toolchain when used by the clrsetbits_le32 macro. Replaces them with the corresponding hex value. The error reported (for example with the mx6qsabrelite board) is something like: mx6qsabrelite.c:369:1: error: invalid suffix "b101" on integer constant mx6qsabrelite.c:369:1: error: invalid suffix "b10010" on integer constant mx6qsabrelite.c:369:1: error: invalid suffix "b0000" on integer constant mx6qsabrelite.c:369:1: error: invalid suffix "b10001" on integer constant Signed-off-by: Stefano Babic <sbabic@denx.de>
| | * MX: set a common place to share code for Freescale i.MXStefano Babic2012-09-10-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Up now only MX5 and MX6 can share code, because they have a common source directory in cpu/armv7. Other not armv7 i.MX can profit of the same shared code. Move these files into a directory accessible for all, similar to plat-mxc in linux. Signed-off-by: Stefano Babic <sbabic@denx.de>
| | * mx31: Define default SoC input clock frequenciesBenoît Thébaudeau2012-09-06-10/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define default SoC input clock frequencies for i.MX31 in order to get rid of duplicated definitions. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Helmut Raiger <helmut.raiger@hale.at>
| | * Fix mx31_decode_pllBenoît Thébaudeau2012-09-06-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | The MFN bit-field of the PLL registers represents a signed value. See the reference manual. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
| | * mx35 timer: Switch to 32-kHz sourceBenoît Thébaudeau2012-09-06-17/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch the mx35 timer driver to the 32-kHz clock source to avoid calling mxc_get_clock() again and again, and to be consistent with the timer drivers of other i.MX SoCs. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
| | * mx35: Define default SoC input clock frequenciesBenoît Thébaudeau2012-09-06-28/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | Define default SoC input clock frequencies for i.MX35 in order to get rid of duplicated definitions. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
| | * mx25: Define default SoC input clock frequenciesBenoît Thébaudeau2012-09-06-9/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define default SoC input clock frequencies for i.MX25 in order to get rid of duplicated definitions. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Matthias Weisser <weisserm@arcor.de>
| | * mx35: Fix clock dividersBenoît Thébaudeau2012-09-06-59/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | The clock dividers that were used do not match at all the reference manual. They were either completely broken, or came from an early silicon revision incompatible with the current one. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
| | * mx35: Add definitions for clock gate valuesBenoît Thébaudeau2012-09-06-0/+6
| | | | | | | | | | | | | | | Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
| | * mx35: Fix decode_pllBenoît Thébaudeau2012-09-06-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | The MFN bit-field of the PLL registers represents a signed value. See the reference manual. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
| | * MX28: Fixup the ad-hoc use of DIGCTL_MICROSECONDSMarek Vasut2012-09-04-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use proper struct-based access for this register in the SPL code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * | Tegra: Change Tegra20 to Tegra in common code, prep for T30Tom Warren2012-09-10-43/+171
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert TEGRA20_ defines to either TEGRA_ or NV_PA_ where appropriate. Convert tegra20_ source file and function names to tegra_, also. Upcoming Tegra30 port will use common code/defines/names where possible. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
| * | tegra20: usb: rework set_host_modeLucas Stach2012-09-10-16/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows for two things: - VBus GPIO may be used on other ports than the OTG one - VBus GPIO may be low active if specified by DT Signed-off-by: Lucas Stach <dev@lynxeye.de> CC: Stephen Warren <swarren@wwwdotorg.org> CC: Tom Warren <TWarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra: nand: Add Tegra NAND driverJim Lin2012-09-07-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A device tree is used to configure the NAND, including memory timings and block/pages sizes. If this node is not present or is disabled, then NAND will not be initialized. Signed-off-by: Jim Lin <jilin@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra: fdt: Add NAND controller binding and definitionsSimon Glass2012-09-07-0/+7
| | | | | | | | | | | | | | | | | | | | | Add a NAND controller along with a bindings file for review. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra: Add NAND support to funcmuxSimon Glass2012-09-07-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | Add selection of NAND flash pins to the funcmux. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | Merge remote-tracking branch 'u-boot-ti/master' into mAlbert ARIBAUD2012-09-05-21/+15
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| | * | am33xx: Remove redundant timer configTom Rini2012-09-04-20/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have the timer code in arch/arm/cpu/armv7/omap-common/timer.c that has been configuring and enabling the timer, so remove our code that does the same thing by different methods. Tested on EVM GP, SK-EVM and Beaglebone. Signed-off-by: Tom Rini <trini@ti.com>
| | * | OMAP3: video: add macros to set display parametersStefano Babic2012-09-04-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a common macros to set the registers for horizontal and vertical timing. Signed-off-by: Stefano Babic <sbabic@denx.de>
| | * | video: drop duplicate set of DISPC_CONFIG registerStefano Babic2012-09-04-1/+0
| | | | | | | | | | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
| | * | OMAP3: add definition of CTRL_WKUP_CTRL registerArnout Vandecappelle (Essensium/Mind)2012-09-04-0/+5
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | AM/DM37x SoCs add the CTRL_WKUP_CTRL register. It contains the GPIO_IO_PWRDNZ bit, which is required to be set to enable the I/O pads of gpio_126, gpio_127 and gpio_129. Signed-off-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be> Cc: Tom Rini <trini@ti.com>
| * | arm: Adds board_postclk_init to the init_sequence.Markus Hubig2012-09-04-0/+3
| |/ | | | | | | | | | | | | | | | | The board_postclk_init() function can be used to perform operations that requires a working timer early within the U-Boot init_sequence. Signed-off-by: Markus Hubig <mhubig@imko.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * kw_spi: fix clock prescaler computationValentin Longchamp2012-09-03-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The computation was not correct with low clock values: setting a 1MHz clock would result in an overlap that would then configure a 25Mhz clock. This patch implements a correct computation method according to the kirkwood functionnal spec. table 600 (Serial Memory Interface Configuration Register). Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Holger Brunck <holger.brunck@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> Acked-by: Prafulla Wadaskar <Prafulla@marvell.com> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
| * edminiv2: orion5x: fix GPIO inits and valuesAlbert ARIBAUD2012-09-03-0/+2
| | | | | | | | | | | | | | | | | | Orion5x did not actually write GPIO output values or input polarities, and ED Mini V2 had bad or missing values for GPIO settings. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-By: Prafulla Wadaskar <prafulla@marvell.com>
* | Flex bus definition update for Coldfire 5253.Jason Jin2012-09-20-0/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | originally work by Jate Sujjavanich <jsujjavanich@syntech-fuelmaster.com> ---- The defines in arch/m68k/include/coldfire/flexbus.h are not compatible with the 5235 processor. The registers in struct fbcs are different sizes from those in the 5235. Also, the defines are a little different. This is what I have so far. Comments? ---- Reformat the patch manually by Jason Jin Signed-off-by: Jate Sujjavanich <jsujjavanich@syntech-fuelmaster.com> Signed-off-by: Jason Jin <Jason.jin@freescale.com>
* | ColdFire: Queued SPI driverRichard Retanubun2012-09-20-2/+41
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds a driver for Freescale Colfire Queued SPI bus. Coded to work with 8 bits per transfer to use with SPI flash. CPOL, CPHA, and CS_ACTIVE_HIGH can be configured. Tested with MCF5270 which have 4 chip selects. Activate by #define CONFIG_CF_QSPI in board config. Signed-off-by: Richard Retanubun <richardretanubun@ruggedcom.com>
* | ColdFire: Clean up checkpatch warnings for MCF54451 and MCF54455Alison Wang2012-09-20-187/+201
| | | | | | | | Signed-off-by: Alison Wang <b18965@freescale.com>
* | ColdFire: Clean up checkpatch warnings for MCF547x and MCF548xAlison Wang2012-09-20-112/+122
| | | | | | | | Signed-off-by: Alison Wang <b18965@freescale.com>
* | ColdFire: Clean up checkpatch warnings for MCF523xAlison Wang2012-09-20-84/+96
| | | | | | | | Signed-off-by: Alison Wang <b18965@freescale.com>
* | ColdFire: Clean up checkpatch warnings for MCF532x/MCF537x/MCF5301xAlison Wang2012-09-20-203/+226
| | | | | | | | Signed-off-by: Alison Wang <b18965@freescale.com>
* | ColdFire: Clean up checkpatch warnings for MCF52x2Alison Wang2012-09-20-197/+229
| | | | | | | | Signed-off-by: Alison Wang <b18965@freescale.com>
* | ColdFire: Clean up checkpatch warnings for MCF5227xAlison Wang2012-09-20-101/+107
| | | | | | | | Signed-off-by: Alison Wang <b18965@freescale.com>
* | ColdFire: Add clear and set bits macros for ColdFire platformAlison Wang2012-09-20-1/+37
| | | | | | | | Signed-off-by: Alison Wang <b18965@freescale.com>
* | ColdFire: Update the bitops for ColdFire platformAlison Wang2012-09-20-32/+27
| | | | | | | | | | | | | | | | | | | | | | This patch uses the general ffs definition to replace the platform ffs definition. This patch also fixes the build error by adding hweightN definition for m5329evb and m5373evb. Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Alison Wang <b18965@freescale.com>
* | ARM: Remove apollon boardMarek Vasut2012-09-18-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | This board is the only board that still sticks to OneNAND IPL. Remove this board, since we have SPL around for a while and OneNAND is well supported in the SPL framework. The board can be revived if necessary. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Tom Rini <trini@ti.com>
* | dm: sparc: Fixup the compile warnings in sparc codeMarek Vasut2012-09-18-7/+6
| | | | | | | | | | | | Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Hellstrom <daniel@gaisler.com> Cc: u-boot-dm@lists.denx.de
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2012-09-17-1/+2
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| * | omap4 i2c: add support for i2c bus 4Koen Kooi2012-09-06-1/+2
| | | | | | | | | | | | Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2012-09-14-29/+151
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| * | | MIPS: move CONFIG_STANDALONE_LOAD_ADDR to CPU config makefilesDaniel Schwierzeck2012-08-24-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | Prepare for upcoming MIPS64 CPU support. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | MIPS: factor out endianess flag handling to arch config.mkDaniel Schwierzeck2012-08-24-22/+20
| | | | | | | | | | | | | | | | | | | | | | | | This is CPU independent and should be configured architecture-wide. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | dm: mips: Import libgcc components from LinuxMarek Vasut2012-08-17-0/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Import ashldr3, ashrdi3 and lshrdi3 to squash possible libgcc fp mismatch, resulting in the following warning: mips-linux-gnu-ld: Warning: /usr/lib/gcc/mips-linux-gnu/4.7/libgcc.a(_lshrdi3.o) uses hard float, u-boot uses soft float mips-linux-gnu-ld: Warning: /usr/lib/gcc/mips-linux-gnu/4.7/libgcc.a(_ashldi3.o) uses hard float, u-boot uses soft float Imported from Linux (linux-next 20120723) as of commit: commit 72fbfb260197a52c2bc2583f3e8f15d261d0f924 Author: Ralf Baechle <ralf@linux-mips.org> Date: Wed Jun 7 13:25:37 2006 +0100 [MIPS] Fix optimization for size build. It took a while longer than on other architectures but gcc has finally started to strike us as well ... This also fixes the damage by 6edfba1b33c701108717f4e036320fc39abe1912. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> [<daniel.schwierzeck@gmail.com>: removed USE_PRIVATE_LIBGCC = yes] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | dm: mips: Fix lb60 timer codeMarek Vasut2012-08-17-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The timer code contains more halfword writes which trigger gcc errors. The registers are again 32bit, yet written by 16bit writes, fix this: timer.c: In function ‘reset_timer_masked’: timer.c:37:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] timer.c: In function ‘get_timer_masked’: timer.c:43:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] timer.c: In function ‘timer_init’: timer.c:86:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] timer.c:88:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] timer.c:89:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] timer.c:90:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel <zpxu@ingenic.cn> Cc: Shinya Kuribayashi <skuribay@pobox.com> Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
| * | | dm: mips: Fix lb60 WDT controlMarek Vasut2012-08-17-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Write the TSCR register via 32bit write instead of 16bit one. The register is 32bit wide and bit 16 is being set, triggering gcc overflow error and making the code broken. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel <zpxu@ingenic.cn> Cc: Shinya Kuribayashi <skuribay@pobox.com> Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
* | | | Merge branch 'master' of git://www.denx.de/git/u-boot-mmcTom Rini2012-09-12-4/+4
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| * | | | mmc: s5p_sdhci: fixed wrong function argumentJaehoon Chung2012-09-05-4/+4
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Useless code is removed, and get buswidth value. buswidth value will be used to choice the 4bit or 8bit. (Now used 4bit mode in sdhci.c by default) Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungin.park@samsung.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | | | microblaze: board: Use bi_flashstart instead of CONFIG_SYS_FLASH_BASEMichal Simek2012-09-11-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Prepare for device-tree driven configuration. Signed-off-by: Michal Simek <monstr@monstr.eu> Acked-by: Stephan Linz <linz@li-pro.net>
* | | | microblaze: Clean microblaze initializationMichal Simek2012-09-11-15/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move board specific function to board_init function in board/ folder Remove externs from generic board.c Use board_init_f function in board.c file. Signed-off-by: Michal Simek <monstr@monstr.eu> Acked-by: Stephan Linz <linz@li-pro.net>
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