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* powerpc/85xx: Change timebase divisor to be defined per processorKumar Gala2011-04-28-5/+12
| | | | | | | | Introduce new CONFIG_SYS_FSL_TBCLK_DIV on 85xx platforms because different SoCs have different divisor amounts. All the PQ3 parts are /8, the P4080/P4080 is /16, and P2040/P3041/P5020 are /32. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Implement work-around for P4080 erratum SERDES-A001Timur Tabi2011-04-28-16/+65
| | | | | | | | | | | | | Bank powerdown through RCW[SRDS_LPD_Bn] for XAUI on FM2 and SGMII on FM1 are swapped. Erratum SERDES-A001 says that if bank two is kept disabled and after bank three is enabled, then the PLL for bank three won't lock properly. The work-around is to enable and then disable bank two after bank three is enabled. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Extend SERDES9 erratum work-around to SGMII, SRIO, and AURORATimur Tabi2011-04-28-17/+35
| | | | | | | | | Part of the SERDES9 erratum work-around is to set some bits in the SerDes TTLCR0 register for lanes configured as XAUI, SGMII, SRIO, or AURORA. The current code does this only for XAUI, so extend it to the other protocols. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Display SERDES 8 erratum warning if banks are not disabledTimur Tabi2011-04-28-0/+11
| | | | | | | | | The work-around for P4080 erratum SERDES-8 requires all lanes of banks two and three to be disabled (powered down) in the RCW. Display a warning message if this is not the case. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Implement work-around for P4080 erratum SERDES-A005Timur Tabi2011-04-28-0/+52
| | | | | | | | SerDes PLL bandwidth default setting is incorrect when no lanes are configured as PCI Express. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Don't set FT_FSL_PCI_SETUP if CONFIG_PCI is not setMatthew McClintock2011-04-27-1/+3
| | | | | | | | | | | | | | A lot of boards set FT_FSL_PCI_SETUP directly in their board code and don't check to see if CONFIG_PCI is actually defined. This will cause the board compilation to fail if CONFIG_PCI is not defined. The p1022ds board is one such example. Instead of fixing every board this patch wraps FT_FSL_PCI_SETUP around CONFIG_PCI so we can remove CONFIG_PCI and boards will still build properly. Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: handle both "secX.Y" and "sec-vX.Y" propertiesKim Phillips2011-04-27-0/+13
| | | | | | | | | versioned SEC properties changed names during development, so for now search and update LIODNs for both "secX.Y" and "sec-vX.Y" based properties. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Enable ESDHC111 erratum on P2040/P3041/P5010/P5020 SoCsLei Xu2011-04-27-0/+4
| | | | | | | | | The workaround for ESDHC111 should also be applied on P2040/P3041/P5010/P5020 SoCs. Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Enable Internal USB PHY for p2040, p3041, p5010 and p5020Roy Zang2011-04-27-0/+38
| | | | | | | | The P2040, P3041, P5010, and P5020 all have internal USB PHYs that we need to enable for them to function. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc: Add P3041DS/P5020DS board support (uses corenet_ds code)Kumar Gala2011-04-27-0/+1
| | | | | | | | | | | | | | | | The P3041DS & P5020DS boards are almost identical (except for the processor in them). Additionally they are based on the P4080DS board design so we use the some board code for all 3 boards. Some ngPIXIS (FPGA) registers where reserved on P4080DS and now have meaning on P3041DS/P5020DS. We utilize some of these for SERDES clock configuration. Additionally, the P3041DS/P5020DS support NAND. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* p4080/serdes: Implement the XAUI workaround for SERDES9 erratumEmil Medve2011-04-27-0/+116
| | | | | | Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: fsl_corenet_serdes code reworkEmil Medve2011-04-27-3/+43
| | | | | | | | | | | | Rework and add some new APIs to the fsl_corenet_serdes code for use by erratum and drivers. * Rename serdes_get_bank() to serdes_get_bank_by_lane() * Add serdes_get_first_lane returns which SERDES lane is used by device Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add device tree fixup for bman portalHaiying Wang2011-04-27-1/+33
| | | | | | | Fix fdt bportal to pass the bman revision number to kernel via device tree. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add support for 2nd USB controller on p1_p2_rdbRamneek Mehresh2011-04-27-0/+1
| | | | | | Second USB controller only works for SPI and SD boot because of pin muxing Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
* powerpc/85xx: Added PMUXCR1 and PMUXCR2 defines for P1010/P1014 SoCDipen Dudhat2011-04-27-0/+71
| | | | | Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Change CS timing params before changing CS properties on IFCDipen Dudhat2011-04-27-16/+15
| | | | | | | | To make sure that machine change operation work successfully, change timing parameters first before changing machine for chip select on IFC. Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc: fix implementation of out_8 to match the other out_XX functionsTimur Tabi2011-04-28-1/+4
| | | | Signed-off-by: Timur Tabi <timur@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2011-04-27-944/+1693
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| * Don't grab memory for LCD if FB address is definedMinkyu Kang2011-04-27-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | If FB address is defined specific address then don't grab memory for LCD Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Cc: Albert Aribaud <albert.aribaud@free.fr> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Kim Phillips <kim.phillips@freescale.com> Cc: Andy Fleming <afleming@gmail.com> Cc: Kumar Gala <kumar.gala@freescale.com>
| * ftsmc020: move ftsmc020 static mem controller to driver/mtdMacpaul Lin2011-04-27-131/+0
| | | | | | | | | | | | | | | | | | | | | | Move the header file and definitions of ftsmc020 static memory control unit from a320 SoC folder to "drivers/mtd" folder. This change will let other SoC which also use ftsmc020 could share the same header file. Signed-off-by: Macpaul Lin <macpaul@andestech.com>
| * ftsdmc020: move ftsdmc020.h to include/faradayMacpaul Lin2011-04-27-103/+0
| | | | | | | | | | | | | | | | | | | | Move the header file "ftsdmc020.h" (SDRAM Controller) to "include/faraday" folder. This change will let other SoC which also use ftsdmc020 could share the same header file. Signed-off-by: Macpaul Lin <macpaul@andestech.com>
| * ARMV7: OMAP3: Cleanup extern variables in mem.cLuca Ceresoli2011-04-27-32/+0
| | | | | | | | | | | | | | | | | | | | | | | | Removed boot_flash_* extern variables. boot_flash_type was totally unused. The other ones were actually constants, so they have been replaced with #defines in the board config files. Signed-off-by: Luca Ceresoli <luca.ceresoli@comelit.it> Cc: Wolfgang Denk <wd@denx.de> Cc: Albert Aribaud <albert.aribaud@free.fr> Cc: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * arm: Tegra2: GPIO: Add basic GPIO definitionsTom Warren2011-04-27-0/+60
| | | | | | | | Signed-off-by: Tom Warren <twarren@nvidia.com>
| * arm: Tegra2: Add missing PLLX initTom Warren2011-04-27-2/+33
| | | | | | | | Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: fix stack pointer adjustment in board_init_f()Eric Cooper2011-04-27-1/+1
| | | | | | | | | | | | | | | | Since addr_sp is a byte address, it should be adjusted by 12 here. Signed-off-by: Eric Cooper <ecc@cmu.edu> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Wolfgang Denk <wd@denx.de>
| * arm: Tegra2: add support for A9 CPU initTom Warren2011-04-27-1/+626
| | | | | | | | Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARMV7: OMAP3: Add GPMC_CONFIGx register value definitionsLuca Ceresoli2011-04-27-0/+95
| | | | | | | | | | Signed-off-by: Luca Ceresoli <luca.ceresoli@comelit.it> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * ARMV7: OMAP3: Fix preprocessor check for CONFIG_OMAP34XXLuca Ceresoli2011-04-27-1/+1
| | | | | | | | | | | | | | | | | | | | CONFIG_OMAP34XX must be checked for existence, not value. Signed-off-by: Luca Ceresoli <luca.ceresoli@comelit.it> Cc: Wolfgang Denk <wd@denx.de> Cc: Albert Aribaud <albert.aribaud@free.fr> Cc: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * omap3_beagle: enable EHCI and USB storage.Alexander Holler2011-04-27-0/+58
| | | | | | | | | | | | | | | | | | | | The reset sequence/configuration for ehci is highly board specific, so this will be done in the source for the board, instead of introducing several CONFIG_* which would be needed to make those few lines in beagle.c usable across different OMAP boards. Signed-off-by: Alexander Holler <holler@ahsoftware.de> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * OMAP3: Add support for DPLL5 (usbhost)Alexander Holler2011-04-27-5/+85
| | | | | | | | | | Signed-off-by: Alexander Holler <holler@ahsoftware.de> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * Replace obsolete e-mail addressAlbert ARIBAUD2011-04-27-10/+10
| | | | | | | | Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
| * a320evb: fix include path of timer fttmr010Macpaul Lin2011-04-27-1/+1
| | | | | | | | | | | | Fix include path of timer fttmr010 in a320evb. Signed-off-by: Macpaul Lin <macpaul@andestech.com>
| * fttmr010: move fttmr010 header to include/faradayMacpaul Lin2011-04-27-73/+0
| | | | | | | | | | | | | | | | | | | | | | Move the header file and definitions of fttmr010 power control unit from a320 SoC folder to "include/faraday" folder. This change will let other SoC which also use fttmr010 could share the same header file. Signed-off-by: Macpaul Lin <macpaul@andestech.com>
| * Orion5x: Correct DRAM bank detectionRogan Dawes2011-04-27-1/+2
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| * I2C: add i2c support for Armada100 platformLei Wen2011-04-27-18/+50
| | | | | | | | | | | | | | | | Add i2c support to aspenite board with Armada100 soc. Acked-by: Heiko Schocher <hs@denx.de> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Lei Wen <leiwen@marvell.com>
| * I2C: add i2c support for Pantheon platformLei Wen2011-04-27-3/+29
| | | | | | | | | | | | | | | | Add i2c support to dkb board with pantheon soc. Acked-by: Heiko Schocher <hs@denx.de> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Lei Wen <leiwen@marvell.com>
| * mv_i2c: use structure to replace the direclty defineLei Wen2011-04-27-56/+10
| | | | | | | | | | | | | | | | | | | | Add i2c_clk_enable in the cpu specific code, since previous platform it, while new platform don't need. In the pantheon and armada100 platform, this function is defined as NULL one. Acked-by: Heiko Schocher <hs@denx.de> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Lei Wen <leiwen@marvell.com>
| * pxa: move i2c driver to the common placeLei Wen2011-04-27-470/+0
| | | | | | | | | | | | | | | | | | For better sharing with other platform other than pxa's, it is more convenient to put the driver to the common place. Acked-by: Heiko Schocher <hs@denx.de> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Lei Wen <leiwen@marvell.com>
| * arm: a320: use new ftpmu010 APIPo-Yu Chuang2011-04-27-20/+3
| | | | | | | | | | | | | | ftpmu010 related code has been moved to drivers/power/. Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com> Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
| * arm: Use optimized memcpy and memset from linuxMatthias Weisser2011-04-27-2/+437
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using optimized versions of memset and memcpy from linux brings a quite noticeable speed (x2 or better) improvement for these two functions. Here are some numbers for test done with jadecpu | HEAD(1)| HEAD(1)| HEAD(2)| HEAD(2)| | | +patch | | +patch | ---------------------------+--------+--------+--------+--------+ Reset to prompt | 438ms | 330ms | 228ms | 120ms | | | | | | TFTP a 3MB img | 4782ms | 3428ms | 3245ms | 2820ms | | | | | | FATLOAD USB a 3MB img* | 8515ms | 8510ms | ------ | ------ | | | | | | BOOTM LZO img in RAM | 3473ms | 3168ms | 592ms | 592ms | where CRC is | 615ms | 615ms | 54ms | 54ms | uncompress | 2460ms | 2462ms | 450ms | 451ms | final boot_elf | 376ms | 68ms | 65ms | 65ms | | | | | | BOOTM LZO img in FLASH | 3207ms | 2902ms | 1050ms | 1050ms | where CRC is | 600ms | 600ms | 135ms | 135ms | uncompress | 2209ms | 2211ms | 828ms | 828ms | | | | | | Copy 1.4MB from NOR to RAM | 134ms | 72ms | 120ms | 70ms | (1) No dcache (2) dcache enabled in board_init *Does not work when dcache is on Size impact: C version: text data bss dec hex filename 202862 18912 266456 488230 77326 u-boot ASM version: text data bss dec hex filename 203798 18912 266288 488998 77626 u-boot 222712 u-boot.bin Signed-off-by: Matthias Weisser <weisserm@arcor.de>
| * OMAP3: BeagleBoard: Enable pullups on i2c2.Steve Kipisz2011-04-27-0/+14
| | | | | | | | | | | | | | | | | | This allows the reading of EEPROMS on the expansion bus without adding external pull-ups. Signed-off-by: Jason Kridner <jkridner@beagleboard.org> Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * MX31: drop warnings in get_cpu_revStefano Babic2011-04-27-1/+1
| | | | | | | | | | | | | | | | Drop warnings due to recent commit ARM: mx31: Print the silicon version Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com>
| * MX5: factor out boot cause funciton to common codeJason Liu2011-04-27-0/+28
| | | | | | | | | | | | | | factor out boot cause function to common code to avoid the duplicate code in each board support package Signed-off-by: Jason Liu <jason.hui@linaro.org>
| * ARM: MX31: Fix file name labelFabio Estevam2011-04-27-3/+3
| | | | | | | | | | | | | | | | | | Commit 5d2c154 (IMX: MX31: Cleanup include files and drop nasty #ifdef in drivers) renamed mx31-imx-regs.h to imx-regs.h. Change the file label accordingly. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * MX31: Introduce get_reset_cause()Fabio Estevam2011-04-27-1/+28
| | | | | | | | | | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Detlev Zundel <dzu@denx.de>
| * ARM: mx31: Print the silicon versionFabio Estevam2011-04-27-2/+53
| | | | | | | | | | | | | | | | | | | | | | Use the same method of the Linux kernel to print the MX31 silicon version on boot. Tested on a MX31PDK with a 2.0 silicon, where it shows: CPU: Freescale i.MX31 rev 2.0 at 531 MHz Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * IMX: MX31: Cleanup include files and drop nasty #ifdef in driversStefano Babic2011-04-27-7/+7
| | | | | | | | | | | | | | | | | | | | As exception among the i.MX processors, the i.MX31 has headers without general names (mx31-regs.h, mx31.h instead of imx-regs.h and clock.h). This requires several nasty #ifdef in the drivers to include the correct header. The patch cleans up the driver and renames the header files as for the other i.MX processors. Signed-off-by: Stefano Babic <sbabic@denx.de>
| * mx25: Make the UART port number explicit in its setup functionFabio Estevam2011-04-27-1/+1
| | | | | | | | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * MX31: add support for MX31 watchdogStefano Babic2011-04-27-1/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch add CONFIG_HW_WATCHDOG to be used with the internal watchdog timer of the MX31 processor. Two function are exported for the board maintainers: mxc_hw_watchdog_enable mxc_hw_watchdog_reset The board maintainer can decide to use mxc_hw_watchdog_reset as hw_watchdog_reset, or to implement his own function to reset the watchdog. The watchdog timer can be configured with CONFIG_SYS_WD_TIMER_SECS (value in seconds). The MX31 allows values between 0.5 (CONFIG_SYS_WD_TIMER_SECS = 0) and 128 seconds. Signed-off-by: Stefano Babic <sbabic@denx.de>
* | Respect memreserve regions specified in the device treeGrant Likely2011-04-25-0/+6
| | | | | | | | | | | | | | | | If a regions is reserved in the fdt, then it should not be used. Add the memreserve regions to the lmb so that u-boot doesn't use them to store the initrd. Signed-off-by: Grant Likely <grant.likely@linaro.org>
generated by cgit v1.1 at 2024-11-15 04:17:25 +0000