summaryrefslogtreecommitdiff
path: root/arch
Commit message (Collapse)AuthorAgeLines
* usb: phy: omap_usb_phy: implement usb_phy_power() for AM437xFelipe Balbi2014-07-09-0/+5
| | | | | | | | Newer AM437x silicon requires us to explicitly power up the USB2 PHY. By implementing usb_phy_power() we can achieve that. Signed-off-by: Felipe Balbi <balbi@ti.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-07-09-4/+3
|\
| * mx6: soc: Update the comments of set_ldo_voltage()Fabio Estevam2014-07-09-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Commit 3d622b78 (mx6: soc: Introduce set_ldo_voltage()) introduces set_ldo_voltage() function that can be used to set the voltages of any of the three LDO regulators controlled by the PMU_REG_CORE register. Prior to this commit there was a single set_vddsoc() which only configured the VDDSOC regulator. Update the comments to align with the new set_ldo_voltage() implementation. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * MX6: Correct calculation of PLL_SYSAndre Renaud2014-07-09-1/+1
| | | | | | | | | | | | | | DIV_SELECT is used as Fout = Fin * div_select / 2.0, so we should do the shift after the multiply to avoid rounding errors Signed-off-by: Andre Renaud <andre@bluewatersys.com>
* | kmake: include DTB section into u-boot.bin if CONFIG_OF_EMBED enabledAlexey Ignatov2014-07-07-0/+4
| | | | | | | | | | Fixes a bug when objcopy doesn't put .dtb.init.rodata section to resulting u-boot.bin, so u-boot was unable to find embedded DTB.
* | blackfin, powerpc: remove redundant definitions of ARRAY_SIZEMasahiro Yamada2014-07-07-5/+0
| | | | | | | | | | | | | | | | | | Since ARRAY_SIZE macro is defined in include/common.h, re-defining it in arch-specific files is redundant. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Sonic Zhang <sonic.zhang@analog.com>
* | blackfin: Add more dcache functionsVasili Galka2014-07-07-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | Add invalidate_dcache_range() and flush_dcache_range() for the blackfin architecture. Such functions already exist on this arch with different names, so just forward the call. This fixes the build of bf609-ezkit board as it uses drivers/net/designware.c which requires the above functions. Cc: Sonic Zhang <sonic.adi@gmail.com>, Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Vasili Galka <vvv444@gmail.com>
* | m68k: Fix incorrect memory access on M5235Vasili Galka2014-07-07-16/+23
| | | | | | | | | | | | | | | | | | | | | | The csarX and cscrX registers in the fbcs_t struct are 16-bit for CONFIG_M5235 and 32-bit wide otherwise. The code in cpu_init.c accessed them always as 32-bit, effectively creating a wrong memory access on M5235. Fixed that by choosing out_be16/out_be32 depending on whether CONFIG_M5235 is defined or not. Cc: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Vasili Galka <vvv444@gmail.com>
* | m68k: Fix bug, "address of" operator was forgottenVasili Galka2014-07-07-1/+1
| | | | | | | | | | | | | | | | in_be16() shall be passed a pointer to register and not its value. This is clearly a typo resulting in a wrong memory access, so fix it. Cc: Alison Wang <b18965@freescale.com>, Jason Jin <Jason.jin@freescale.com> Signed-off-by: Vasili Galka <vvv444@gmail.com>
* | mpc8xx: remove spc1920 board supportMasahiro Yamada2014-07-07-1/+0
| | | | | | | | | | | | This board is old enough and has no maintainer. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | mpc8xx: remove fads board supportMasahiro Yamada2014-07-07-112/+2
| | | | | | | | | | | | These boards are old enough and have no maintainers. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | mpc8xx: remove netta, netta2, netphone board supportMasahiro Yamada2014-07-07-20/+0
| | | | | | | | | | | | These boards are old enough and have no maintainers. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | mpc8xx: remove RPXlite_dw, quantum board supportMasahiro Yamada2014-07-07-14/+0
| | | | | | | | | | | | These boards are old enough and have no maintainers. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | mpc8xx: remove qs850, qs860t board supportMasahiro Yamada2014-07-07-10/+0
| | | | | | | | | | | | These boards are old enough and have no maintainers. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | am43xx: Tune the system to avoid DSS underflowsCooper Jr., Franklin2014-07-07-4/+49
| | | | | | | | | | * This is done by limiting the ARM's bandwidth and setting DSS priority in the EMIF controller to ensure underflows do not occur.
* | am43xx: Update EMIF DDR3 Configuration for AM43x GPFranklin S. Cooper Jr2014-07-07-0/+2
| | | | | | | | | | | | | | | | | | * Boot failures have been discovered due to a combination of routing issues and non optimal ddr3 timings in the EMIF * Since ddr3 timings are different after significant board layout changes different timings are required for alpha, beta and production boards. Signed-off-by: Franklin S. Cooper Jr <fcooper@ti.com>
* | build: define CPU only when arch/${ARCH}/cpu/${CPU} existsMasahiro Yamada2014-07-07-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The directory arch/${ARCH}/cpu/${CPU} does not exist in avr32, blackfin, microblaze, nios2, openrisc, sandbox, x86. These architectures have only one CPU type. Defining CPU should not be required for such architectures. This commit allows cpu field (= the 3rd field of boards.cfg) to be kept blank. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Sonic Zhang <sonic.zhang@analog.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Thomas Chou <thomas@wytron.com.tw> Cc: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
* | ARM: emif4: wait for CM_DLL_READYST to be setJeroen Hofstee2014-07-07-1/+1
| | | | | | | | | | | | | | | | | | The code intends for the CM_DLL_READYST to be set, but actually polls till any bit is set since the logical AND is used instead of the bitwise one is used. Fix it. cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2014-07-07-0/+2
|\ \
| * | i2c: tegra: use repeated start for readsStephen Warren2014-07-03-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I2C read transactions are typically implemented as follows: START(write) address REPEATED_START(read) data... STOP However, Tegra's I2C driver currently implements reads as follows: START(write) address STOP START(read) data... STOP This sequence confuses at least the AS3722 PMIC on the Jetson TK1 board, leading to corrupted read data in some cases. Fix the driver to chain the transactions together using repeated starts to solve this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Yen Lin <yelin@nvidia.com>
* | | socfpga: Relocate arch common functions away from boardChin Liang See2014-07-05-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To move the arch common function away from board folder to arch/arm/cpu/armv7/socfpga folder. Its to avoid code duplication for other non Altera dev kit which is using socfpga device. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Acked-by: Detlev Zundel <dzu@denx.de>
* | | arm: Fix armv8 compilation errorShaibal.Dutta2014-07-05-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix following compilation error when CONFIG_ARM64 is defined Error: unknown or missing system register name at operand 2 -- `mrs x0,daifmsr daifset,#3' Signed-off-by: Shaibal.Dutta <shaibal.dutta@broadcom.com> Signed-off-by: Darwin Rambo <drambo@broadcom.com> Reviewed-by: Darwin Rambo <drambo@broadcom.com>
* | | arm: spl: fix include guardJeroen Hofstee2014-07-05-2/+2
| | | | | | | | | | | | | | | cc: Tom Rini <trini@ti.com> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* | | socfpga: Adding Scan Manager driverChin Liang See2014-07-05-1/+305
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Scan Manager driver will be called to configure the IOCSR scan chain. This configuration will setup the IO buffer settings Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
* | | socfpga: Adding DesignWare watchdog supportChin Liang See2014-07-05-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To enable the DesignWare watchdog support at SOCFPGA Cyclone V dev kit. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com>
* | | arm: ep9315: Return back Cirrus Logic EDB9315A board supportSergey Kostanbaev2014-07-04-27/+521
| | | | | | | | | | | | | | | | | | | | | This patch returns back support for old ep93xx processors family Signed-off-by: Sergey Kostanbaev <sergey.kostanbaev@gmail.com> Cc: albert.u.boot@aribaud.net
* | | ARM: cache_v7: use __weakJeroen Hofstee2014-07-04-55/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is not only more readable but also prevents a warning about a missing prototype. The prototypes which are actually missing are added. cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Reviewed-by: Tom Rini <trini@ti.com>
* | | ARMv8/ls2085a_emu: Add LS2085A emulator and simulator board supportYork Sun2014-07-04-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS2085A is an ARMv8 implementation. This adds board support for emulator and simulator: Two DDR controllers UART2 is used as the console IFC timing is tightened for speedy booting Support DDR3 and DDR4 as separated targets Management Complex (MC) is enabled Support for GIC 500 (based on GICv3 arch) Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com> Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
* | | armv8/fsl-lsch3: Add support to load and start MC FirmwareJ. German Rivera2014-07-03-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding support to load and start the Layerscape Management Complex (MC) firmware. First, the MC GCR register is set to 0 to reset all cores. MC firmware and DPL images are copied from their location in NOR flash to DDR. MC registers are updated with the location of these images. Deasserting the reset bit of MC GCR register releases core 0 to run. Core 1 will be released by MC firmware. Stop bits are not touched for this step. U-boot waits for MC until it boots up. In case of a failure, device tree is updated accordingly. The MC firmware image uses FIT format. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Shruti Kanetkar <Shruti@Freescale.com>
* | | ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoCYork Sun2014-07-03-1/+937
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
* | | ARMv8: Adjust MMU setupYork Sun2014-07-03-30/+44
| | | | | | | | | | | | | | | | | | | | | Make MMU function reusable. Platform code can setup its own MMU tables. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn>
* | | Added 64-bit MMIO accessors for ARMv8J. German Rivera2014-07-03-0/+8
| | | | | | | | | | | | | | | | | | | | | This is needed for accessing peripherals with 64-bit MMIO registers, from ARMv8 processors. Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
* | | arm: Add support for semihosting for armv8 fastmodel targets.Darwin Rambo2014-07-03-0/+255
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The armv8 ARM Trusted Firmware (ATF) can be used to load various ATF images and u-boot, and does this for virtual platforms by using semihosting. This commit extends this idea by allowing u-boot to also use semihosting to load the kernel/ramdisk/dtb. This eliminates the need for a bootwrapper and produces a more realistic boot sequence with virtual models. Though the semihosting code is quite generic, support for armv7 in fastmodel is less useful due to the wide range of available silicon and the lack of a free armv7 fastmodel, so this change contains an untested armv7 placeholder for the service trap opcode. Please refer to doc/README.semihosting for a more detailed description of semihosting and how it is used with the armv8 virtual platforms. Signed-off-by: Darwin Rambo <drambo@broadcom.com> Cc: trini@ti.com Cc: fenghua@phytium.com.cn Cc: bhupesh.sharma@freescale.com
* | Merge remote-tracking branch 'u-boot-samsung/master'Albert ARIBAUD2014-07-01-193/+582
|\ \ | | | | | | | | | | | | | | | | | | | | | Conflicts: boards.cfg Conflict was trivial between goni maintainer change and lager_nor removal.
| * | Exynos5420: Introduce support for the Peach-Pit boardAkshay Saraswat2014-06-23-93/+281
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While the Exynos5420 chip is used in both Smdk5420 and in the Peach-Pit line of devices, there could be other boards using the same chip, so a common configuration file is being added (exynos5420.h) as well as two common device tree files (exynos54xx.dtsi & exynos5420.dtsi). The peach board as declared in boards.cfg is a copy of smdk5420 declaration. The configuration files are similar, but define different default device trees, console serial ports and prompts. The device tree files for smdk5420 and peach-pit inherit from the same common file. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Exynos5420: Let macros be used for exynos5420Akshay Saraswat2014-06-23-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Macros defined in exynos5_setup.h specific to SMDK5420 are required for Peach-Pit too. Hence, replacing CONFIG_SMDK5420 with CONFIG_EXYNOS5420 to enable these macros for all the boards based on Exynos5420. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Exynos5420: DMC: Add software read levelingAkshay Saraswat2014-06-13-7/+255
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sometimes Read DQ and DQS are not in phase. Since, this phase shift differs from board to board, we need to calibrate it at DRAM init phase, that's read DQ calibration. This patch adds SW Read DQ calibration routine to compensate this skew. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | DMC: exynos5420: Gate CLKM to when reading PHY_CON13Doug Anderson2014-06-13-5/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | when CLKM is running. If we stop CLKM when sampling it the glitches all go away, so we'll do that as per Samsung suggestion. We also check the "is it locked" bits of PHY_CON13 and loop until they show the the value sampled actually represents a locked value. It doesn't appear that the glitching and "is it locked" are related, but it seems wise to wait until the PHY tells us the value is good before we use it. In practice we will not loop more than a couple times (and usually won't loop at all). Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Exynos5420: Remove code for enabling read levelingAkshay Saraswat2014-06-13-71/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch intends to remove all code which enables hardware read leveling. All characterization environments may not cope up with h/w read leveling enabled, so we must disable this. Also, disabling h/w read leveling improves the MIF LVcc value (LVcc value is the value at which DDR will fail to work properly). Improving LVcc means we have enough voltage margin for MIF. When h/w leveling is enabled, we have almost zero volatge margin. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Exynos5: DMC: Modify the definition of ddr3_mem_ctrl_initAkshay Saraswat2014-06-13-13/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Passing fewer arguments is better and mem_iv_size is never used. Let's keep only one argument and make it cleaner. Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Revert "exynos: Enable PSHOLD in SPL"Minkyu Kang2014-06-13-2/+0
| | | | | | | | | | | | This reverts commit eb0dd9986c3883820ff888c3738b013c0a7d918c.
* | | Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'Albert ARIBAUD2014-07-01-1/+1
|\ \ \
| * | | tegra20: display: fix checking of return valueJeroen Hofstee2014-06-19-1/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The calling code seems a bit in doubt about the return value of fdtdec_lookup_phandle. Since it returns a negative value on error (and fdt_node_offset_by_phandle as well), check for that. cc: Wei Ni <wni@nvidia.com> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2014-07-01-283/+94
|\ \ \
| * | | OMAP: disable gpmc timeout safely for reenablingStefano Babic2014-06-19-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gpmc timeout is disabled and the reset counter is set to 0. However, if later a driver activates the timeout setting the reset to a valid value, the old reset value with zero is still valid for the first access. In fact, the timeout block loads the reset counter after a successful access. Found on a am335x board with a FPGA connected to the GPMC bus together with the NAND. When the FPGA driver in kernel activates the timeout, the system hangs at the first access by the NAND driver. Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | | omap3: board: trivial: add void for no argsJeroen Hofstee2014-06-19-2/+2
| | | | | | | | | | | | | | | | Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
| * | | cpu: armv7: am33x: ddr: write emif ref_ctrl_shadow registerFelipe Balbi2014-06-19-0/+1
| | | | | | | | | | | | | | | | Signed-off-by: Felipe Balbi <balbi@ti.com>
| * | | ARM: keystone: aemif: move aemif driver to drivers/memory/ti-aemif.cKhoronzhuk, Ivan2014-06-19-105/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move AEMIF driver to drivers/memory/ti-aemif.c along with AEMIF definitions collected in arch/arm/include/asm/ti-common/ti-aemif.h Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | mtd: nand: davinci: add header file for driver definitionsKhoronzhuk, Ivan2014-06-19-175/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The definitions inside emif_defs.h concern davinci nand driver and should be in it's header. So create header file for davinci nand driver and move definitions from emif_defs.h and nand_defs.h to it. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> [trini: Fixup more davinci breakage] Signed-off-by: Tom Rini <trini@ti.com>
| * | | omap: Don't enable GPMC CS0 with nothing attachedAsh Charles2014-06-19-1/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_(NAND|NOR|ONENAND) is not defined, no configuration is set for GPMC on chip select #0---size is 0. In this case, the GPMC configuration should be reset but not enabled. Enabling causes the Gumstix DuoVero board to hang when entering Linux. Signed-off-by: Ash Charles <ashcharles@gmail.com> [trini: Switch to testing base as GPMC_SIZE_256M is 0x0] Signed-off-by: Tom Rini <trini@ti.com>
generated by cgit v1.1 at 2024-11-11 10:04:10 +0000