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* Remove arch/${ARCH}/include/asm/errno.hMasahiro Yamada2016-09-23-1/+0
| | | | | | | | | | | | | | Unlike Linux, nothing about errno.h is arch-specific in U-Boot. As you see, all of arch/${ARCH}/include/asm/errno.h is just a wrapper of <asm-generic/errno.h>. Actually, U-Boot does not export headers to user-space, so we just have to care about the consistency in the U-Boot tree. Now all of include directives for <asm/errno.h> are gone. Deprecate <asm/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
* xtensa: add core information for the de212 processorMax Filippov2016-08-15-0/+839
| | | | | | | | | | DE212 is a general purpose xtensa processor without full MMU. Core information files are autogenerated from the processor description and are not meant to be edited. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* xtensa: add core information for the dc233c processorMax Filippov2016-08-15-0/+757
| | | | | | | | | | DC233C is an xtensa processor with full MMUv3 capable of running Linux. Core information files are autogenerated from the processor description and are not meant to be edited. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* xtensa: add core information for the dc232b processorChris Zankel2016-08-15-0/+674
| | | | | | | | | | | DC232B is an xtensa processor with full MMUv2 capable of running Linux. Core information files are autogenerated from the processor description and are not meant to be edited. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* xtensa: add support for the xtensa processor architecture [2/2]Chris Zankel2016-08-15-0/+1569
The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Tensilica, inc. This is the second part of the basic architecture port, adding the 'arch/xtensa' directory and a readme file. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>