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* x86: gpio: add pinctrl support from the device treeGabriel Huau2015-06-04-0/+24
| | | | | | | | | Every pin can be configured now from the device tree. A dt-bindings has been added to describe the different property available. Change-Id: I1668886062655f83700d0e7bbbe3ad09b19ee975 Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Acked-by: Simon Glass <sjg@chromium.org>
* x86: baytrail: pci region 3 is not always mapped to end of ramAndrew Bradford2015-06-04-1/+1
| | | | | | | | | | | | Baytrail physically maps the first 2 GB of SDRAM from 0x0 to 0x7FFFFFFF and additional SDRAM is mapped from 0x100000000 and up. There is a physical memory hole from 0x80000000 to 0xFFFFFFFF for other uses. Because of this, PCI region 3 should only try to use up to the amount of SDRAM or 0x80000000, which ever is less. Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: qemu: Implement PIRQ routingBin Meng2015-06-04-0/+61
| | | | | | | | | Support QEMU PIRQ routing via device tree on both i440fx and q35 platforms. With this commit, Linux booting on QEMU from U-Boot has working ATA/SATA, USB and ethernet. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: coreboot: Control I/O port 0xb2 writing via device treeBin Meng2015-06-04-3/+10
| | | | | | | | | | Writing 0xcb to I/O port 0xb2 (Advanced Power Management Control) causes U-Boot to hang on QEMU q35 target. We introduce a config option in the device tree "u-boot,no-apm-finalize" under /config node if we don't want to do that. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: qemu: Create separate i440fx and q35 device treesBin Meng2015-06-04-2/+37
| | | | | | | | | | Although the two qemu-x86 targets (i440fx and q35) share a lot in common, they still have something that cannot easily handled in one single device tree). Split to create two dedicated device tree files and make the i440fx be the default build target. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: coreboot: Fix cosmetic issuesBin Meng2015-06-04-25/+3
| | | | | | | Clean up arch/x86/cpu/coreboot.c to fix several cosmetic issues. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: kconfig: Make FSP_TEMP_RAM_ADDR depend on HAVE_FSPBin Meng2015-06-04-0/+1
| | | | | | | FSP_TEMP_RAM_ADDR should only be visible when HAVE_FSP is on. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: qemu: Adjust VGA initializationBin Meng2015-06-04-19/+17
| | | | | | | | | | | | | As VGA option rom needs to run at C segment, although QEMU PAM emulation seems to only guard E/F segments, for correctness, move VGA initialization after PAM decode C/D/E/F segments. Also since we already tested QEMU targets to differentiate I440FX and Q35 platforms, change to locate the VGA device via hardcoded b.d.f instead of dynamic search for its vendor id & device id pair. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: qemu: Enable legacy IDE I/O ports decodeBin Meng2015-06-04-0/+38
| | | | | | | | | QEMU always decode legacy IDE I/O ports on PIIX chipset. However Linux ata_piix driver does sanity check to see whether legacy ports decode is turned on. To make Linux ata_piix driver happy, turn on the decode via IDE_TIMING register. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: qemu: Turn on legacy segments decodeBin Meng2015-06-04-0/+26
| | | | | | | | | By default the legacy segments C/D/E/F do not decode to system RAM. Turn on the decode via Programmable Attribute Map (PAM) registers so that we can write configuration tables in the F segment. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: fsp_support: Correct high mem comment typoAndrew Bradford2015-06-04-1/+1
| | | | | | | | High mem starts at 4 GiB. Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Do sanity test on pirq table before writingBin Meng2015-06-04-0/+3
| | | | | | | | | If pirq_routing_table points to NULL, that means U-Boot fails to generate the table before in create_pirq_routing_table(), so we test it against NULL before actually writing it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Implement PIRQ routingBin Meng2015-06-04-15/+123
| | | | | | | | | Intel Quark SoC has the same interrupt routing mechanism as the Queensbay platform, only the difference is that PCI devices' INTA/B/C/D are harcoded and cannot be changed freely. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Refactor PIRQ routing supportBin Meng2015-06-04-300/+383
| | | | | | | | | | | | PIRQ routing is pretty much common in Intel chipset. It has several PIRQ links (normally 8) and corresponding registers (either in PCI configuration space or memory-mapped IBASE) to configure the legacy 8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing support using device tree and move it to a common place, so that we can easily add PIRQ routing support on a new platform. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: qemu: Add graphics supportBin Meng2015-06-04-1/+23
| | | | | | | | It turns out that QEMU x86 emulated graphic card has a built-in option ROM which can be run perfectly with native mode by U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Move FRAMEBUFFER_SET_VESA_MODE etc to video KconfigBin Meng2015-06-04-141/+0
| | | | | | | | | | CONFIG_FRAMEBUFFER_SET_VESA_MODE and CONFIG_FRAMEBUFFER_VESA_MODE are not x86-specific, so move them to drivers/video/Kconfig and make them depend on VIDEO_VESA driver. Some cosmetic fixes are applied to the Kconfig help text as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Make QEMU the default vendorBin Meng2015-06-04-1/+1
| | | | | | | | | Now that we have QEMU support, make it the default vendor in the 'make menuconfig' screen. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Support QEMU x86 targetsBin Meng2015-06-04-1/+259
| | | | | | | | | | | This commit introduces the initial U-Boot support for QEMU x86 targets. U-Boot can boot from coreboot as a payload, or directly without coreboot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Merged in patch 'x86: qemu: Add CMD_NET to qemu-x86_defconfig https://patchwork.ozlabs.org/patch/479745/
* x86: Enable multi-core init for Minnowboard MAXSimon Glass2015-04-30-0/+20
| | | | | | | | Enable the CPU uclass and Simple Firmware interface for Minnowbaord MAX. This enables multi-core support in Linux. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add a CPU driver for baytrailSimon Glass2015-04-30-6/+227
| | | | | | | | This driver supports multi-core init and sets up the CPU frequencies correctly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Allow CPUs to be set up after relocationSimon Glass2015-04-30-0/+54
| | | | | | | | This permits init of additional CPU cores after relocation and when driver model is ready. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add functions to set and clear bits on MSRsSimon Glass2015-04-30-0/+28
| | | | | | | | Since we do these sorts of operations a lot, it is useful to have a simpler API, similar to clrsetbits_le32(). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add multi-processor initSimon Glass2015-04-30-7/+934
| | | | | | | | | Most modern x86 CPUs include more than one CPU core. The OS normally requires that these 'Application Processors' (APs) be brought up by the boot loader. Add the required support to U-Boot to init additional APs. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Provide access to the IDTSimon Glass2015-04-29-0/+7
| | | | | | | Add a function to return the address of the Interrupt Descriptor Table. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Store the GDT pointer in global_dataSimon Glass2015-04-29-0/+2
| | | | | | | | | When we start up additional CPUs we want them to use the same Global Descriptor Table. Store the address of this in global_data so we can reference it later. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add an mfence macroSimon Glass2015-04-29-0/+5
| | | | | | | Provide access to this x86 instruction from C code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add defines for fixed MTRRsSimon Glass2015-04-29-0/+14
| | | | | | | Add MSR numbers for the fixed MTRRs. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add atomic operationsSimon Glass2015-04-29-0/+115
| | | | | | | | Add a subset of this header file from Linux 4.0 to support atomic operations in U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add support for the Simple Firmware Interface (SFI)Simon Glass2015-04-29-0/+311
| | | | | | | | | This provides a way of passing information to Linux without requiring the full ACPI horror. Provide a rudimentary implementation sufficient to be recognised and parsed by Linux. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Disable -WerrorSimon Glass2015-04-29-1/+1
| | | | | | | | | This is annoying during development and serves no useful purpose since warnings are clearly displayed now that we are using Kbuild. Remove this option. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Remove unwanted MMC debuggingSimon Glass2015-04-29-1/+0
| | | | | | | This printf() should not have made it into the code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: fsp: Use reset_cpu()Simon Glass2015-04-29-7/+0
| | | | | | | | Now that reset_cpu() functions correctly, use it instead of directly accessing the port on boards that use a Firmware Support Package (FSP). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: quark: Use reset_cpu()Simon Glass2015-04-29-1/+1
| | | | | | | | | Now that reset_cpu() functions correctly, use it instead of directly accessing the port. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Use reset_cpu()Simon Glass2015-04-29-15/+6
| | | | | | | | Now that reset_cpu() functions correctly, use it instead of directly accessing the port. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Implement reset_cpu() correctly for modern CPUsSimon Glass2015-04-29-13/+28
| | | | | | | | | | | | The existing code is pretty ancient and is unreliable on modern hardware. Generally it will hang. We can use port 0xcf9 to initiate reset on more modern hardware (say in the last 10 years). Update the reset_cpu() function to do this, and add a new 'full reset' function to perform a full power cycle. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: link: Add PCH driver to support SPI FlashSimon Glass2015-04-29-1/+12
| | | | | | | | U-Boot on coreboot does not have a driver for the PCH so cannot see the SPI peripheral now that it has moved inside the PCH. Add a simple driver so that SPI flash works again. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: minnowmax: use the correct NOR in the configurationGabriel Huau2015-04-29-1/+1
| | | | | | | | The SPI NOR on the minnowboard max is a MICRON N25Q064A Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Correct the typo in write_tables()Bin Meng2015-04-29-1/+1
| | | | | | | It should be #ifdef instead of #if. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Kconfig: Move DM_SPI & DM_SPI_FLASH to arch/KconfigBin Meng2015-04-29-6/+0
| | | | | | | | Since all x86 boards have been converted to use DM_SPI and DM_SPI_FLASH, move them to arch/Kconfig x86 section. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Kconfig: MARK_GRAPHICS_MEM_WRCOMB cosmeticsBin Meng2015-04-29-4/+4
| | | | | | | | Remove the ending period of the MARK_GRAPHICS_MEM_WRCOMB option. Also fix the indention of its help text. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Kconfig: Move platform options forwardBin Meng2015-04-29-10/+9
| | | | | | | | | | | Move platform-specific options under in arch/x86/Kconfig forward right after the board-specific options but before any architecture-specific options. When it comes to the same Kconfig option, board-specific one takes take the highest precedence, then platform-specific one, and finally architecture-specific one. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Kconfig: Divide the target selection to vendor/modelBin Meng2015-04-29-79/+13
| | | | | | | | | | Let arch/x86/Kconfig prompt board vendor first, then select the board model under that vendor. This way arch/x86/Kconfig only needs concern board vendor and leave the supported target list to board/<vendor>/Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Turn on legacy segments decodeBin Meng2015-04-29-0/+19
| | | | | | | | | By default the legacy segments (A0000h-B0000h, E0000h-F0000h) do not decode to system RAM. Turn on the decode so that we can write configuration tables in the F segment. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Check PIRQ routing table sanity in the F segmentBin Meng2015-04-29-5/+13
| | | | | | | | | | Previously the PIRQ routing table sanity check was performed against the original table provided by the platform codes. Now we switch to check its sanity on the final table in the F segment as this one is the one seen by the OS. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: minnowmax: add GPIO banks in the device treeGabriel Huau2015-04-29-0/+42
| | | | | | | | | | There are 6 banks: 4 banks for CORE: available in S0 mode 2 banks for SUS (Suspend): available in S0-S5 mode Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: baytrail: fix the GPIOBASE addressGabriel Huau2015-04-29-1/+1
| | | | | | | | The correct GPIOBASE address on the baytrail is 0x48 Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: queensbay: Implement PIRQ routingBin Meng2015-04-29-4/+440
| | | | | | | | Implement Intel Queensbay platform-specific PIRQ routing support. The chipset PIRQ routing setup is called in the arch_misc_init(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Support platform PIRQ routingBin Meng2015-04-29-0/+300
| | | | | | | | | | | | | | | On x86 boards, platform chipset receives up to four different interrupt signals from PCI devices (INTA/B/C/D), which in turn will be routed to chipset internal PIRQ lines then routed to 8259 PIC finally if configuring the whole system to work under the so-called PIC mode (in contrast to symmetric IO mode which uses IOAPIC). We add two major APIs to aid this, one for routing PIRQ and the other one for generating a PIRQ routing table. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Write configuration tables in last_stage_init()Bin Meng2015-04-29-0/+90
| | | | | | | | We can write the configuration table in last_stage_init() for all x86 boards, but not with coreboot since coreboot already has them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add a function to assign IRQ numbers to PCI deviceBin Meng2015-04-29-0/+35
| | | | | | | | | Add a function to assign an IRQ number to PCI device's interrupt line register in its configuration space, so that the PCI device can have its interrupt working under PIC mode after OS boots up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-12-23 13:51:48 +0000