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* x86: queensbay: Adapt FSP support codesBin Meng2014-12-13-18/+28
* x86: Initial import from Intel FSP release for Queensbay platformBin Meng2014-12-13-0/+1522
* x86: Add a simple superio driver for SMSC LPC47MBin Meng2014-12-13-0/+90
* x86: Add Intel Crown Bay board dts fileBin Meng2014-12-13-1/+55
* x86: ich6-gpio: Move setup_pch_gpios() to board support codesBin Meng2014-12-13-0/+7
* x86: Clean up asm-offsetsBin Meng2014-12-13-2/+3
* x86: Make ROM_SIZE configurable in KconfigBin Meng2014-12-13-1/+77
* Replace <compiler.h> with <linux/compiler.h>Masahiro Yamada2014-12-08-6/+7
* Kbuild: introduce Makefile in arch/$ARCH/Daniel Schwierzeck2014-12-08-0/+12
* x86: dts: Add video information to the device treeSimon Glass2014-11-25-0/+13
* x86: Add initial video device init for Intel GMASimon Glass2014-11-25-1/+927
* x86: Add support for running option ROMs nativelySimon Glass2014-11-25-0/+946
* x86: Add vesa mode configuration optionsSimon Glass2014-11-25-0/+149
* x86: Add GDT descriptors for option ROMsSimon Glass2014-11-25-22/+18
* x86: ivybridge: Add northbridge init functionsSimon Glass2014-11-25-1/+207
* x86: Drop some msr functions that we don't supportSimon Glass2014-11-25-11/+0
* x86: Add init for model 206AX CPUSimon Glass2014-11-25-0/+526
* x86: Add LAPIC setup codeSimon Glass2014-11-25-2/+181
* x86: Drop old CONFIG_INTEL_CORE_ARCH codeSimon Glass2014-11-25-28/+0
* x86: Refactor interrupt_init()Bin Meng2014-11-25-14/+23
* x86: Remove cpu_init_r() for x86Bin Meng2014-11-25-8/+0
* x86: Call cpu_init_interrupts() from interrupt_init()Bin Meng2014-11-25-2/+3
* x86: Add Intel speedstep and turbo mode codeSimon Glass2014-11-25-0/+219
* x86: ivybridge: Set up XHCI USBSimon Glass2014-11-25-0/+34
* x86: ivybridge: Set up EHCI USBSimon Glass2014-11-25-0/+33
* x86: dts: Add SATA settings for linkSimon Glass2014-11-25-0/+7
* x86: ivybridge: Add SATA initSimon Glass2014-11-25-0/+306
* x86: dts: Add LPC settings for linkSimon Glass2014-11-25-0/+8
* x86: dts: Move PCI peripherals into a pci nodeSimon Glass2014-11-25-13/+15
* x86: ivybridge: Add additional LPC initSimon Glass2014-11-25-1/+528
* x86: ivybridge: Add PCH initSimon Glass2014-11-25-0/+173
* x86: Add a simple header file for ACPISimon Glass2014-11-25-0/+24
* x86: ivybridge: Add support for BD82x6x PCHSimon Glass2014-11-25-0/+167
* x86: Set up edge triggering on interrupt 9Simon Glass2014-11-25-0/+49
* x86: pci: Add handlers before and after a PCI hose scanSimon Glass2014-11-25-0/+15
* x86: Add ioapic.h headerSimon Glass2014-11-25-0/+38
* x86: Factor out common values in the link scriptSimon Glass2014-11-25-7/+12
* x86: Ensure that all relocation data is included in the imageSimon Glass2014-11-25-1/+3
* x86: Panic if there is no relocation dataSimon Glass2014-11-25-0/+3
* x86: Remove board_early_init_r()Simon Glass2014-11-25-11/+0
* x86: Add ivybridge directory to MakefileSimon Glass2014-11-25-0/+2
* Merge git://git.denx.de/u-boot-x86Tom Rini2014-11-24-175/+6391
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| * x86: Rename chromebook-x86 to corebootSimon Glass2014-11-21-1/+1
| * x86: ivybridge: Implement SDRAM initSimon Glass2014-11-21-5/+1861
| * x86: ivybridge: Add LAPIC supportSimon Glass2014-11-21-0/+163
| * x86: Make show_boot_progress() commonSimon Glass2014-11-21-24/+24
| * x86: chromebook_link: Enable GPIO supportSimon Glass2014-11-21-0/+3
| * x86: ivybridge: Add support for early GPIO initSimon Glass2014-11-21-6/+158
| * x86: ivybridge: Add early init for PCH devicesSimon Glass2014-11-21-1/+524
| * x86: dts: Add microcode updates for ivybridge CPUSimon Glass2014-11-21-0/+1382
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