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* x86: Fix off-by-one error in do_elf_reloc_fixups()Duncan Laurie2012-12-06-1/+1
| | | | | | | | | | The use of post-increment with a do-while loop results in the loop going one step too far when handling relocation fixups. In about 1/100 cases this would cause it to hang. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Ignore memory >4GB when parsing Coreboot tablesDuncan Laurie2012-12-06-0/+4
| | | | | | | | U-boot is unable to actually use that memory and it can cause problems with relocation if it tries to. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Fix indirect jmp warning in zimage.cSimon Glass2012-12-06-3/+3
| | | | | | | | | | | | | | This fixes the following warning: zimage.c:312: Warning: indirect jmp without `*' Also fixed these warnings to keep checkpatch quiet: warning: arch/x86/lib/zimage.c,311: unnecessary whitespace before a quoted newline warning: arch/x86/lib/zimage.c,312: unnecessary whitespace before a quoted newline warning: arch/x86/lib/zimage.c,313: unnecessary whitespace before a quoted newline Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Clean up MTRR 7 right before jumping to the kernelStefan Reinauer2012-12-06-0/+18
| | | | | | | | This cleans up the rom caching optimization implemented in coreboot (and needed throughout U-Boot runtime). Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Import MSR/MTRR code from LinuxGraeme Russ2012-12-06-0/+913
| | | | | | Imported from Linux 3.1 with a few modifications to suit U-Boot Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Provide a function to clean up just before booting a zimageStefan Reinauer2012-12-06-0/+11
| | | | | | | | This function can be used by boards which want to do some clean-up before booting a zImage. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add basic cache operationsStefan Reinauer2012-12-06-72/+155
| | | | | | | Add functions to enable/disable the data cache. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Fill in the dram info using the e820 map on coreboot/x86Gabe Black2012-12-06-0/+15
| | | | | | | | | | | | | | | This way when that dram "banks" are displayed, there's some useful information there. The number of "banks" we claim to have needs to be adjusted so that it covers the number of RAM e820 regions we expect to have/care about. This needs to be done after "RAM" initialization even though we always run from RAM. The bd pointer in the global data structure doesn't automatically point to anything, and it isn't set up until "RAM" is available since, I assume, it would take too much space in the very constrained pre-RAM environment. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add a CBMEM timestamp generated right before the kernel startup.Vadim Bendebury2012-12-06-0/+7
| | | | | | | | | | To maintain the initialization state of the timestamp facility, thesq pointer to the CBMEM section containing the timestamp table should be kept in the .data section (so that it is maintained across u-boot relocation). Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Enable coreboot timestamp facility support in u-boot.Vadim Bendebury2012-12-06-0/+117
| | | | | | | | | | | | | | | | | | | | | This change turns on the code which allows u-boot to add timestamps to the timestamp table created by coreboot. Since u-boot does not use the tsc_t like structure to represent HW counter readings, this structure is being replaced by 64 bit integer. The timestamp_init() function is now initializing the base timer value used by u-boot to calculate the HW counter increments. Timestamp facility is initialized as soon as the timestamp table pointer is found in the coreboot table. The u-boot generated timer events' ID will start at 1000 to clearly separate u-boot events from coreboot events in the timer trace. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add function to read time stamp counterVadim Bendebury2012-12-06-0/+29
| | | | | | | | | | | Put this function in the u-boot-x86.h header file. We could instead create timer.h perhaps. We support setting a base time, and reading the time relative to this base. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: gpio: Add GPIO driver for Intel ICH6 and later.Bill Richardson2012-12-06-0/+27
| | | | | | | | | Implement <asm-generic/gpio.h> functions for Intel ICH6 and later. Only GPIOs 0-31 are handled by this code. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Don't spam POST80 codes with slow IO functionsStefan Reinauer2012-11-30-1/+1
| | | | | | | | | | | | | | This patch prevents u-boot from "spamming" random progress codes on a port 80 "post card". The previous version of this patch just removed the delays in the "slow" IO functions, as they do not need to be slow, however, this patch is less intrusive. It uses another unused port that is often used by BIOSes (and the Linux Kernel) for small delay timing purposes. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Fix typo in pcat_timer.cStefan Reinauer2012-11-30-1/+1
| | | | | | | Fix a small comment typo. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Include types.h explicitly in the i386 version of io.hGabe Black2012-11-30-0/+2
| | | | | | | | | | The i386 version of io.h depends on the phys_addr_t type which is defined in types.h. It wasn't including that explicitly, and was working presumably because the other files including it had already included types.h themselves directly or indirectly. This change fixes that. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add a dummy implementation for timer_get_usGabe Black2012-11-30-1/+18
| | | | | | | | The microsecond timer is not currently implemented, but add a dummy implementation for now. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add a default implementation for cleanup_before_linux()Gabe Black2012-11-30-0/+6
| | | | | | | | | | | This function provides an opportunity for some last minute cleanup and reconfiguration before control is handed over to Linux. It's possible this may need to do something in the future, but for now it's left empty. It's set up as a weak symbol so it can be overridden if necessary on a case by case basis. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add an fdt pointer to the global data structureGabe Black2012-11-30-0/+1
| | | | | | | | This change adds a pointer to the global data structure in x86 to point to the device tree. This mirrors an identical pointer in ARM. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Allow compiling out realmode/bios codeGabe Black2012-11-30-5/+10
| | | | | | | | We don't want this for coreboot, so provide a way of compiling it out. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: coreboot: Decode additional coreboot sysinfo tagsSimon Glass2012-11-30-29/+188
| | | | | | | | | | | Add support for decoding tags for GPIOs, compile/build info, cbmem and other features. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: coreboot: Drop sysinfo.cStefan Reinauer2012-11-30-40/+8
| | | | | | | | | | sysinfo.c only contains the lib_sysinfo data structure which is used/filled by tables.c. This split was introduced by importing code from libpayload originally, but to keep the code simple, add the single line of actual code to tables.c Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: coreboot: Implement recursively scanning PCI bussesGabe Black2012-11-28-3/+23
| | | | | | | | | | | | | | | | | | | | | | A hook is installed to configure PCI bus bridges as they encountered by u-boot. The hook extracts the secondary bus number from the bridge's config space and then recursively scans that bus. On Coreboot, the PCI bus address space has identity mapping with the physical address space, so declare it as such to ensure that the "pci_map_bar" function used by some PCI drivers is behaving properly. This fixes the EHCI PCI driver initialization on Stumpy. This was tested as follows: Ran the PCI command on Alex, saw devices on bus 0, the OXPCIe 952 on bus 1, and empty busses 2 through 5. This matches the bridges reported on bus 0 and the PCI configuration output from coreboot. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: coreboot: Tell u-boot about PCI bus 0 when initializingGabe Black2012-11-28-1/+16
| | | | | | | | | | | | | | | | | U-boot needs a host controller or "hose" to interact with the PCI busses behind them. This change installs a host controller during initialization of the coreboot "board" which implements some of X86's basic PCI semantics. This relies on some existing generic code, but also duplicates a little bit of code from the sc520 implementation. Ideally we'd eliminate that duplication at some point. It looks like in order to scan buses beyond bus 0, we'll need to tell u-boot's generic PCI configuration code what to do if it encounters a bridge, specifically to scan the bus on the other side of it. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Graeme Russ <graeme.russ@gmail.com>
* x86: coreboot: Move non-board specific files to coreboot arch directoryStefan Reinauer2012-11-28-0/+119
| | | | | | | | | | coreboot.c and coreboot_pci.c don't contain board specific but only coreboot specific code. Hence move it to the coreboot directory in arch/x86/cpu (which should probably be moved out of cpu/ in another commit) Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add some missing includesGabe Black2012-11-28-0/+5
| | | | | | | | | I suspect these includes were usually available because something else included them earlier or because they were brought in transitively. Change-Id: I6aae2ac94dc792eac6febb4345e8125f69f70988 Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Allow excluding reset vector code from u-bootGabe Black2012-11-28-2/+6
| | | | | | | | | | | | When running from coreboot we don't want this code. This version works by ifdef-ing out all of the code that would go into those sections and all the code that refers to it. The sections are then empty, and the linker will either leave them empty for the loader to ignore or remove them entirely. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add initial memory barrier macrosSimon Glass2012-11-28-0/+8
| | | | | | These are available on other architectures, so add them on x86. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add ilog2 to bitopsGraeme Russ2012-11-28-0/+5
| | | | | | | ilog2 is required by AHCI driver Signed-off-by: Graeme Russ <graeme.russ@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Remove duplicate PCI initGraeme Russ2012-11-28-3/+0
| | | | | Signed-off-by: Graeme Russ <graeme.russ@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Put global data on the stackGraeme Russ2012-11-28-52/+63
| | | | | | | | | | Putting global data on the stack simplifies the init process (and makes it slightly quicker). During the 'flash' stage of the init sequence, global data is in the CAR stack. After SDRAM is initialised, global data is copied from CAR to the SDRAM stack Signed-off-by: Graeme Russ <graeme.russ@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Forward declare gd_tGraeme Russ2012-11-28-5/+7
| | | | | | | | So it can be used as a type in struct global_data and remove an ugly typecast Signed-off-by: Graeme Russ <graeme.russ@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de>
* common: Discard the __u_boot_cmd sectionMarek Vasut2012-10-22-4/+0
| | | | | | | | | | | The command declaration now uses the new LG-array method to generate list of commands. Thus the __u_boot_cmd section is now superseded and redundant and therefore can be removed. Also, remove externed symbols associated with this section from include/command.h . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Mike Frysinger <vapier@gentoo.org>
* common: Add .u_boot_list into all linker filesMarek Vasut2012-10-22-0/+5
| | | | | | | | | | Add section for the linker-generated lists into all possible linker files, so that everyone can easily use these lists. This is mostly a mechanical adjustment. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Mike Frysinger <vapier@gentoo.org>
* x86: Change global data baudrate to intSimon Glass2012-10-19-1/+1
| | | | | | | This doesn't need to be a long, so change it. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@ti.com>
* serial: Remove CONFIG_SERIAL_MULTI from remaining sourcesMarek Vasut2012-10-15-2/+0
| | | | | | | | | | | | Remove the parts depending either on disabled CONFIG_SERIAL_MULTI or ifdefs around CONFIG_SERIAL_MULTI parts since CONFIG_SERIAL_MULTI is now enabled by default. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tom Rini <trini@ti.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Stefan Roese <sr@denx.de>
* global_data: unify global flag definesMike Frysinger2012-08-09-13/+1
| | | | | | | All the global flag defines are the same across all arches. So unify them in one place, and add a simple way for arches to extend for their needs. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* net: move bootfile init into eth_initializeMike Frysinger2012-05-15-16/+0
| | | | | | | | All arches init this the same way, so move the logic into the core net code to avoid duplicating it everywhere else. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* net: punt bd->bi_ip_addrMike Frysinger2012-05-15-13/+0
| | | | | | | | | This field gets read in one place (by "bdinfo"), and we can replace that with getenv("ipaddr"). After all, the bi_ip_addr field is kept up-to-date implicitly with the value of the ipaddr env var. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* sc520: fix build warning about unused temp varMike Frysinger2012-03-06-3/+2
| | | | | | | | | | | Building the eNET_SRAM board fails for me: sc520_timer.c: In function 'sc520_udelay': sc520_timer.c:81:7: error: variable 'temp' set but not used [-Werror=unused-but-set-variable] cc1: all warnings being treated as errors make[1]: *** [sc520_timer.o] Error 1 Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* x86: Convert board_init_f_r to a processing loopGraeme Russ2012-01-04-125/+206
| | | | | | | | | | | | | | Create an init function array for board_init_f_r - This finalises the migration to a purely array based initialisation mechanism Also tweak a few comments while we are at it so everything is 'correct' -- Changes for v2: - Renamed to a more apt name - Fix bug in set_reloc_flag_r - Re-instate gd->flags = boot_flags; in board_init_f - Added commit message
* x86: Split init functions out of board.cGraeme Russ2012-01-04-221/+438
| | | | | | This patch moves towards reducing board.c to simply a set of init cores for the three initialisation phases (Flash, Flash/RAM, and RAM), a set of three init function arrays and a init function array processing function
* x86: Move relocation code out of board.cGraeme Russ2012-01-04-67/+118
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* x86: Move setup_pcat_compatibility() out of board.cGraeme Russ2012-01-04-7/+7
| | | | | | | | | This function simply does not belong in board.c -- Changes for v2: - Added commit message
* x86: Move do_go_exec() out of board.cGraeme Russ2012-01-04-27/+65
| | | | | | -- Changes for v2: - None
* CHECKPATCH: arch/x86/lib/*Graeme Russ2012-01-04-73/+122
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* x86: Tweak IDT and GDT for alignment and readabilityGraeme Russ2012-01-04-13/+46
| | | | | | -- Changes for v2: - Renamed to better reflect nature of changes
* x86: Allow cache before copy to RAMGraeme Russ2012-01-04-5/+10
| | | | | | -- Changes for v2: - None
* x86: Create weak init_cache() and default enable_caches() functionsGraeme Russ2012-01-04-3/+17
| | | | | | -- Changes for v2: - Tweaked commit title
* x86: Set GD_FLG_RELOC after entering in-RAM copy of U-BootGraeme Russ2012-01-04-2/+2
| | | | | | -- Changes for v2: - None
* x86: Use fs for global dataGraeme Russ2012-01-04-47/+94
| | | | | | | | | | | | | | | | | | | | | | Use the base address of the 'F' segment as a pointer to the global data structure. By adding the linear address (i.e. the 'D' segment address) as the first word of the global data structure, the address of the global data relative to the 'D' segment can be found simply, for example, by: fs movl 0, %eax This makes the gd 'pointer' writable prior to relocation (by reloading the Global Desctriptor Table) which brings x86 into line with all other arches NOTE: Writing to the gd 'pointer' is expensive (but we only do it twice) but using it to access global data members (read and write) is still fairly cheap -- Changes for v2: - Rebased against changes made to patch #3 - Removed extra indent - Tweaked commit message
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